UCSB Nanofab Wiki - User contributions [en]

ICP Etching Recipes

2025-08-13T14:34:30Z

Gopimeena: /* Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etch Recipes (Fluorine ICP Etcher)==

*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.
*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
{| class="wikitable"
!50W SiO2 Etch w/ Ru Hardmask
!200W SiO2 Etch w/ Ru Hardmask (Ning Cao)
|-
|[[File:FL-ICP 50W SiO2 etch with Ru Hard Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|266x266px]]
|[[File:FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|266x266px]]
|}

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch]]

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides
[[File:SEM Image.png|thumb|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch]]

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
''Full Wafer Si etching with ~50% open area and resist mask, run weekly.''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

=== Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
''Full Wafer Si etching with ~50% open area and resist mask, run weekly.''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]

=[[ICP Etch 1 (Panasonic E646V)]]=

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==InP Ridge Etch (Oxford ICP Etcher)==
===NEW High-Temp (200°C) Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C
===OLD Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 NEW Process Control Data for "Std InP Ridge Etch" Cl2/H2/Ar/200°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots'''][[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|none|thumb|344x344px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 OLD Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
[[File:Dot Facet 00.jpg|alt=Example SEM image|thumb|170x170px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]]

ICP Etching Recipes

2025-08-13T14:34:05Z

Gopimeena: /* PR/BARC Etch (Fluorine ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etch Recipes (Fluorine ICP Etcher)==

*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.
*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
{| class="wikitable"
!50W SiO2 Etch w/ Ru Hardmask
!200W SiO2 Etch w/ Ru Hardmask (Ning Cao)
|-
|[[File:FL-ICP 50W SiO2 etch with Ru Hard Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|266x266px]]
|[[File:FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|266x266px]]
|}

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch]]

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides
[[File:SEM Image.png|thumb|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch]]

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue
==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
''Full Wafer Si etching with ~50% open area and resist mask, run weekly.''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

=== Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
''Full Wafer Si etching with ~50% open area and resist mask, run weekly.''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]

=[[ICP Etch 1 (Panasonic E646V)]]=

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==InP Ridge Etch (Oxford ICP Etcher)==
===NEW High-Temp (200°C) Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C
===OLD Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 NEW Process Control Data for "Std InP Ridge Etch" Cl2/H2/Ar/200°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots'''][[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|none|thumb|344x344px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 OLD Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
[[File:Dot Facet 00.jpg|alt=Example SEM image|thumb|170x170px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]]

ICP Etching Recipes

2025-08-13T14:33:39Z

Gopimeena: /* Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etch Recipes (Fluorine ICP Etcher)==

*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.
*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
{| class="wikitable"
!50W SiO2 Etch w/ Ru Hardmask
!200W SiO2 Etch w/ Ru Hardmask (Ning Cao)
|-
|[[File:FL-ICP 50W SiO2 etch with Ru Hard Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|266x266px]]
|[[File:FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|266x266px]]
|}

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch]]'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides

[[File:SEM Image.png|thumb|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch]]'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue
==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
''Full Wafer Si etching with ~50% open area and resist mask, run weekly.''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

=== Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
''Full Wafer Si etching with ~50% open area and resist mask, run weekly.''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]

=[[ICP Etch 1 (Panasonic E646V)]]=

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==InP Ridge Etch (Oxford ICP Etcher)==
===NEW High-Temp (200°C) Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C
===OLD Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 NEW Process Control Data for "Std InP Ridge Etch" Cl2/H2/Ar/200°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots'''][[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|none|thumb|344x344px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 OLD Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
[[File:Dot Facet 00.jpg|alt=Example SEM image|thumb|170x170px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]]

ICP Etching Recipes

2025-08-13T14:32:40Z

Gopimeena: /* Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etch Recipes (Fluorine ICP Etcher)==

*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.
*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
{| class="wikitable"
!50W SiO2 Etch w/ Ru Hardmask
!200W SiO2 Etch w/ Ru Hardmask (Ning Cao)
|-
|[[File:FL-ICP 50W SiO2 etch with Ru Hard Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|266x266px]]
|[[File:FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|266x266px]]
|}

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by PostBARC Etch/PR Strip (STD) with 2min over etch]]'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides
'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue
[[File:SEM Image.png|thumb|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch]]

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
''Full Wafer Si etching with ~50% open area and resist mask, run weekly.''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

=== Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
''Full Wafer Si etching with ~50% open area and resist mask, run weekly.''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]

=[[ICP Etch 1 (Panasonic E646V)]]=

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==InP Ridge Etch (Oxford ICP Etcher)==
===NEW High-Temp (200°C) Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C
===OLD Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 NEW Process Control Data for "Std InP Ridge Etch" Cl2/H2/Ar/200°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots'''][[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|none|thumb|344x344px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 OLD Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
[[File:Dot Facet 00.jpg|alt=Example SEM image|thumb|170x170px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]]

Wet Etching Recipes

2025-06-09T23:35:02Z

Gopimeena: /* Table of Wet Etching Recipes */

__TOC__

==Chemicals Available==

*[[Chemical List|'''The Chemical Lists''']] show stocked chemicals, photolithography chemicals, and how to bring new chemicals.

==Table of Wet Etching Recipes==
''Use the ↑ ↓ Arrows in the header row to sort the entire table by material, selectivity, etchant etc.''
{| class="wikitable sortable"
|-
!Material!!Etchant!!Rate (nm/min)!!Anisotropy!!Selective to!!Selectivity!!Ref.!!Notes!!Confirmed By/Date
|-
|Photoresist, polymers/organics
|H2SO4:H2O2 = 3:1
[[Wet Etching Recipes#Organic%20removal|Piranha Solution]]
|typ. 5-10min etch for polymer residue
|
|Cr, W, Au, Pt, Si, SiO2, SiN
|
|
|'''''Dangerous''''' boiling hazard - see '''''[[Wet Etching Recipes#Piranha%20Solution|Piranha Solution]]'''''
section below. Etches Ti, Ni, Hf
|[[Demis D. John]], 2017
|-
|InP
|H3PO4:HCl = 3:1
|~1000
|Highly
|InGaAsP
|High
|[http://tel.archives-ouvertes.fr/docs/00/76/94/02/PDF/VA2_LAMPONI_MARCO_15032012.pdf Lamponi (p.102)]
|
|
|-
|InGaAsP
|''To Be Added''
|
|
|InP
|High
|
|
|
|-
|InP||H3PO4:HCl = 3:1||~1000||Highly||InGaAs||High||[http://tel.archives-ouvertes.fr/docs/00/76/94/02/PDF/VA2_LAMPONI_MARCO_15032012.pdf Lamponi (p.102)]||
|
|-
|InP
|HCl:H2O = 3:1
|~5000
|
|InGaAs
~200nm stop-etch
|High
|
|Bubbles while etching
|
|-
|InGaAs
|H2SO4:H2O2:H2O = 1:1:10
|~600
|
|InP
|High
|
|Exothermic, may reduce selectivity if hot
|
|-
|GaAs
|NH4OH:H2O2 = 1:30
|
| -
|AlGaAs,
Al > 80%

~200nm stop-etch
|High
|
|
|Garrett Cole
|-
|AlGaAs,
Al ≥80%
|HF:H2O = 1:20
|
| -
|GaAs
|High
|
|
|Garrett Cole
|-
|Oxide of InP
|NH4OH:H2O = 1:10
|1min to remove
|
|InP
|unknown
|
|
|[[Ning Cao]]
|-
|Oxide of GaAs
|HCl:H2O = 1:10
|1min to remove
|
|GaAs
|unknown
|
|
|[[Demis D. John]]
|-
|Al2O3 ''(ALD Plasma 300C)''||Developer: 300MIF||~1.6||None
|Most non-Al Materials.
|High||Measured in-house||Rate slows with time.||JTB
|-
|Al2O3 ''(ALD Plasma 300C)''||Developer: 400K||~2.2||None
|Most non-Al Materials.
|High||Measured in-house||Rate slows with time.||JTB
|-
|Al2O3 ''(ALD Plasma 300C)''||Developer: 400K (1:4)||~1.6||None
|Most non-Al Materials.
|High||Measured in-house||Rate slows with time.||JTB
|-
|Al2O3 ''(ALD Plasma 300C)''||NH4OH:H2O2:H2O (1:2:50)||~<0.5|| || || ||Measured in-house||Rate slows with time||JTB
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Al2O3 ''(IBD)'']
|HF ("Buffered HF Improved", Transene)
|~170
|None
|Photoresist
|High
|Measured in-house
|May need to increase adhesion with thin SiO2 layer, and 100°C baked HMDS.
|Biljana Stamenic,
2017-12
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Al2O3 ''(IBD)'']
|Developer: 726 MiF
|3.5
|None
|Most non-Al Materials.
|High
|Measured in-house
|
|Demis D. John,
2017-11
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 Al2O3 ''(AJA#4)'']
|Developer: 300 MiF
|4.30
|None
|Most non-Al Materials.
|High
|Measured in-house
|
|Demis D. John
2018-02
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=PECVD_Recipes#SiO2_deposition_.28PECVD_.231.29 SiO2 ''(PECVD #1)'']
|HF ("Buffered HF Improved", Transene)
|~550
|None
|Photoresist
|High
|Measured in-house
|May need to increase adhesion with 100°C baked HMDS.
|Biljana Stamenic
2023
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=PECVD_Recipes#SiO2_deposition_.28PECVD_.232.29 SiO2 ''(PECVD #2)'']
|HF ("Buffered HF Improved", Transene)
|~680
|None
|Photoresist
|High
|Measured in-house
|May need to increase adhesion with 100°C baked HMDS.
|Biljana Stamenic
2023
|-
|SiO2 ''(ALD -BDEAS 300C)''
|HF ("Buffered")
Diluted with DI
BHF:H2O = 1:100
|~7.46
|
|
|
|Measured in-house
|
|Biljana Stamenic
2024
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#SiO2_deposition_.28IBD.29 SiO2 (IBD)]
|HF ("Buffered HF Improved", Transene)
|~260
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanofab.ucsb.edu/wiki/PECVD_Recipes#ICP-PECVD_.28Unaxis_VLR.29 SiO2 LDR ''(Unaxis VLR)'']
|HF ("Buffered HF Improved", Transene)
|~170
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanofab.ucsb.edu/wiki/PECVD_Recipes#ICP-PECVD_.28Unaxis_VLR.29 SiO2 HDR ''(Unaxis VLR)'']
|HF ("Buffered HF Improved", Transene)
|~230
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=PECVD_Recipes#SiN_deposition_.28PECVD_.231.29 Si3N4 (PECVD#1)]
|HF ("Buffered HF Improved", Transene)
|~120
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=PECVD_Recipes#SiN_deposition_.28PECVD_.232.29 Si3N4 (PECVD#2)]
|HF ("Buffered HF Improved", Transene)
|~35
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=PECVD_Recipes#Low-Stress_SiN_deposition_.28PECVD_.232.29 Si3N4 Low-Stress (PECVD#2)]
|HF ("Buffered HF Improved", Transene)
|~30
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Si3N4_deposition_.28IBD.29 Si3N4 (IBD)]
|HF ("Buffered HF Improved", Transene)
|~5
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanofab.ucsb.edu/wiki/PECVD_Recipes#ICP-PECVD_.28Unaxis_VLR.29 SiN ''(Unaxis VLR)'']
|HF ("Buffered HF Improved", Transene)
|~10
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanofab.ucsb.edu/wiki/PECVD_Recipes#ICP-PECVD_.28Unaxis_VLR.29 SiN Low Stress ''(Unaxis VLR)'']
|HF ("Buffered HF Improved", Transene)
|~135
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Ta2O5_deposition_.28IBD.29 Ta2O5 (IBD)]
|HF ("Buffered HF Improved", Transene)
|0.07
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#TiO2_deposition_.28IBD.29 TiO2 (IBD)]
|HF ("Buffered HF Improved", Transene)
|1.0–2.0
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2014-12
|-
|Si (<100> crystalline)
|KOH (45%) @ 87°C
|~730
|High, Crystallographic, ~55°
|Low-Stress Si3N4 - either [[PECVD Recipes#Low-Stress SiN deposition .28PECVD .232.29|PECVD #2]] or Commercial LPCVD Si3N4
Other Si3N4 also OK.
|LS-SiN: High
PR etches quickly, SiO2 etches slowly.
|Measured In-House
- Search online.
|Use the Covered, Heated vertical bath ([[Wet Benches#Wafer Toxic Corrosive Benches|Dedi cated bath in Bay 4]]). Slight Bubbler.
|Brian Thibeault
2017
|-
!Material!!Etchant!!Rate (nm/min)!!Anisotropy!!Selective to!!Selectivity!!Ref.!!Notes!!Confirmed By/Date
|}

==Wet Etching References==

#[http://ieeexplore.ieee.org/abstract/document/546406/ Etch rates for Micromachining Processing (IEEE Jnl. MEMS, 1996)] - includes tables of etch rates of numerous metals vs. various wet and dry etchants.
#[http://ieeexplore.ieee.org/abstract/document/1257354/ Etch rates for micromachining-Part II (IEEE Jnl. MEMS, 2003)] - expanded tables containing resists, dielectrics, metals and semiconductors vs. many wet etch chemicals.
#[http://www.sciencedirect.com/science/article/pii/S0927796X00000279 Guide to references on III±V semiconductor chemical etching] - exhaustive list of wet etchants for etching various semiconductors, including selective etches.
#[http://transene.com/etch-compatibility/ Transene's Chemical Compatibility Chart] provides a useful quick-reference for which Transene etchants attack which materials.
##As a side-note, [http://transene.com/ Transene] provides many pre-mixed solutions that you can order, saving you the time and uncertainty of measuring/mixing such chemicals yourself. Make sure you check with us before ordering so we know how to handle the chemical before it arrives.

===Compound Semiconductor Etching===
[http://www.sciencedirect.com/science/article/pii/S0927796X00000279 Guide to references on III±V semiconductor chemical etching (A.R. Clawson, 2001)]

* Impressively vast list of various III-V wet etches, organized by various applications (eg. "selective GaAs against AlGaAs" or "non-selective InP/InGaAsP" etc.)
* Please add any confirmed etches from this reference to the {{HLink|Wet Etching Recipes|The Master Table of Wet Etching (Include All Materials)}}.

===Metal Etching===

*[//wiki.nanotech.ucsb.edu/w/images/c/c3/Ta_and_Cr_E-beam_deposition_and_wet_etch_test.pdf Selective Wet Etch of Cr over Ta using Cr Etchant]
*[//wiki.nanotech.ucsb.edu/w/images/d/dc/ITO_Deposition-250C-Ebeam2-HCl-Wet-Etch.pdf Wet Etch of ITO using Heated, Diluted HCl Solution]

===Silicon etching===
[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=546406 Etch rates for micromachining processing]

[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1257354 Etch rates for micromachining processing-part II]

Please add any confirmed etches from this reference to the {{HLink|Wet Etching Recipes|The Master Table of Wet Etching (Include All Materials)}}.

==Organic removal==

===Piranha Solution===

*'''Careful!''' Read about how to prepare and handle this safely:
**[http://web.mit.edu/cortiz/www/PiranhaSafety.doc MIT's Piranha Solution safety document]
**[https://www.ehs.harvard.edu/sites/default/files/lab_safety_guideline_piranha_etch.pdf Harvard EHS's Handling Document]
**Used for etching away Photoresist residues after dry etching.

===PureStrip (Transene)===

*Heat to @ 70°C
**[[Wet Benches#Wafer Toxic Corrosive Benches|Vertical heated bath on Wafer Toxic-Corrosive bench in Bay 4]]
**After a few days heated, it loses potency - must drain + replenish with fresh solution.
**~30-90min will remove stubborn, microscopic PR residues from dry etching.

==[[Gold Plating Bench|Gold Plating Bench (Technic SEMCON 1000)]]==
Standard plating recipes are described and taught during the equipment training for this tool.

Electroplating first requires a Gold seed layer to be present on all surfaces to be plated. Common ways to produce this are to:

*[[Tool List#Sputter Deposition|Sputter-coat]] a thin (~10nm) Au layer on all surfaces of the wafer, being careful to consider shadowing effects during the dep (eg. in high-aspect ratio trenches).
*Perform photolithography to protect (and prevent plating) in desired areas - areas with no photoresist will be plated.
*Perform the electroplating on the [[Gold Plating Bench|Technic SemCon]], contacting the seed layer with electrodes and executing the program for the desired current/time to achieve the plating thickness (typically microns).
*Strip the photoresist using standard solvents.
*Use the [[CAIBE (Oxford Ion Mill)|Oxford Ion Mill]] to blanket etch the 10nm seed layer all over the wafer (the 10nm removed from the plated regions will be negligible).

==[[Chemical-Mechanical Polisher (Logitech)|Chemi-Mechanical Polishing (CMP)]]==
''To Be Added''

==[[Mechanical Polisher (Allied)|Mechanical Polishing (Allied)]]==
''To Be Added''
[[Category:Processing]]

ICP Etching Recipes

2025-02-11T16:32:12Z

Gopimeena: /* Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|465x465px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|407x407px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:Copy of 22 013 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 16.32µm Deep Etched Silicon with UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===

*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

==Si Etching (Fluorine ICP Etcher)==
'''Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)'''

*'''SiVertHFv2 (⭐️Production)''' - Full Wafer Si etching with ~50% open area and resist mask
**This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]][[File:PRStrip 019 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etching (Fluorine ICP Etcher)==

*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min[[File:SEM Image of wafer after PR strip.png|thumb|402x402px|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by PostBARC Etch/PR Strip (STD) with 2min over etch]]

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides[[File:SEM Image.png|thumb|400x400px|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by PostBARC Etch/PR Strip (STD)_V2 with 2min over etc]]
'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue
==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]][[File:Dot Facet 00.jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]

==InP Ridge Etch (Oxford ICP Etcher)==
===Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

ICP Etching Recipes

2025-01-28T18:54:01Z

Gopimeena: /* Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|465x465px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|407x407px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:Copy of 22 013 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 16.32µm Deep Etched Silicon with UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===

*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

==Si Etching (Fluorine ICP Etcher)==
'''Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)'''

*'''SiVertHFv2 (⭐️Production)''' - Full Wafer Si etching with ~50% open area and resist mask
**This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]][[File:PRStrip 019 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etching (Fluorine ICP Etcher)==

*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min[[File:SEM Image of wafer after PR strip.png|thumb|402x402px|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by PostBARC Etch/PR Strip (STD) with 2min over etch]]
===Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)===
Old PR strip recipe: PostBARC Etch/PR Strip (STD)
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides[[File:SEM Image.png|thumb|400x400px|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by PostBARC Etch/PR Strip (STD)_V2 with 2min over etc]]
New PR strip recipe: PostBARC Etch/PR Strip (STD)_V2
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue
==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]][[File:Dot Facet 00.jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]

==InP Ridge Etch (Oxford ICP Etcher)==
===Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

ICP Etching Recipes

2025-01-28T18:53:28Z

Gopimeena: /* Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|465x465px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|407x407px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:Copy of 22 013 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 16.32µm Deep Etched Silicon with UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===

*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

==Si Etching (Fluorine ICP Etcher)==
'''Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)'''

*'''SiVertHFv2 (⭐️Production)''' - Full Wafer Si etching with ~50% open area and resist mask
**This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]][[File:PRStrip 019 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etching (Fluorine ICP Etcher)==

*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min
[[File:SEM Image of wafer after PR strip.png|thumb|402x402px|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by PostBARC Etch/PR Strip (STD) with 2min over etch]]

===Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)===
Old PR strip recipe: PostBARC Etch/PR Strip (STD)
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides[[File:SEM Image.png|thumb|400x400px|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by PostBARC Etch/PR Strip (STD)_V2 with 2min over etc]]
New PR strip recipe: PostBARC Etch/PR Strip (STD)_V2
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue
==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]][[File:Dot Facet 00.jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]

==InP Ridge Etch (Oxford ICP Etcher)==
===Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

ICP Etching Recipes

2025-01-28T18:53:10Z

Gopimeena: /* Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|465x465px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|407x407px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:Copy of 22 013 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 16.32µm Deep Etched Silicon with UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===

*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

==Si Etching (Fluorine ICP Etcher)==
'''Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)'''

*'''SiVertHFv2 (⭐️Production)''' - Full Wafer Si etching with ~50% open area and resist mask
**This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]][[File:PRStrip 019 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etching (Fluorine ICP Etcher)==

*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min
[[File:SEM Image of wafer after PR strip.png|thumb|402x402px|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by PostBARC Etch/PR Strip (STD) with 2min over etch]]

===Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)===
Old PR strip recipe: PostBARC Etch/PR Strip (STD)
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides[[File:SEM Image.png|thumb|400x400px|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by PostBARC Etch/PR Strip (STD)_V2 with 2min over etc]]
New PR strip recipe: PostBARC Etch/PR Strip (STD)_V2
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]][[File:Dot Facet 00.jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]

==InP Ridge Etch (Oxford ICP Etcher)==
===Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

ICP Etching Recipes

2025-01-28T18:52:56Z

Gopimeena: /* Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|465x465px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|407x407px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:Copy of 22 013 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 16.32µm Deep Etched Silicon with UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===

*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

==Si Etching (Fluorine ICP Etcher)==
'''Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)'''

*'''SiVertHFv2 (⭐️Production)''' - Full Wafer Si etching with ~50% open area and resist mask
**This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]][[File:PRStrip 019 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etching (Fluorine ICP Etcher)==

*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min
[[File:SEM Image of wafer after PR strip.png|thumb|402x402px|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by PostBARC Etch/PR Strip (STD) with 2min over etch]]

===Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)===
Old PR strip recipe: PostBARC Etch/PR Strip (STD)
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides[[File:SEM Image.png|thumb|400x400px|Wafer had UV6 or UVN30 as mask. 5min Si etch followed by PostBARC Etch/PR Strip (STD)_V2 with 2min over etc]]
New PR strip recipe: PostBARC Etch/PR Strip (STD)_V2
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue
==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]][[File:Dot Facet 00.jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]

==InP Ridge Etch (Oxford ICP Etcher)==
===Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

File:SEM Image.png

2025-01-28T18:50:16Z

Gopimeena:

Wafer had UV6 or UVN30 as mask. 5min Si etch followed by PostBARC Etch/PR Strip (STD)_V2 with 2min over etch

File:SEM Image.png

2025-01-28T18:47:03Z

Gopimeena:

Mask

File:SEM Image of wafer after PR strip.png

2025-01-28T18:36:26Z

Gopimeena:

PR used as mask for 5min Si etch. Followed by PR strip with 2min over etch

ICP Etching Recipes

2025-01-27T22:57:51Z

Gopimeena: /* GaN Etch (Oxford ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|465x465px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|407x407px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:Copy of 22 013 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 16.32µm Deep Etched Silicon with UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===

*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

==Si Etching (Fluorine ICP Etcher)==
'''Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)'''

*'''SiVertHFv2 (⭐️Production)''' - Full Wafer Si etching with ~50% open area and resist mask
**This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]][[File:PRStrip 019 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etching (Fluorine ICP Etcher)==

*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min

===Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)===

**O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
**75W Bias can be helpful for difficult to remove polymers, eg. 2min
**Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]][[File:Dot Facet 00.jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]

==InP Ridge Etch (Oxford ICP Etcher)==
===Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

Stepper 3 (ASML DUV)

2025-01-27T20:00:26Z

Gopimeena: /* UCSB Photomasks Available */

{{tool|{{PAGENAME}}
|picture=ASML.jpg
|type = Lithography
|super= Demis D. John
|location=Bay 7
|description = Deep-UV Stepper Photolithography
|model = PAS 5500/300
|manufacturer = [http://www.asml.com ASML]
|ToolType = Lithography
|recipe = Lithography
|materials =
|toolid=51
}}

==About==

===General Capabilities/Overview===
The ASML 5500 stepper is a 248nm (KrF) DUV stepper for imaging dense features down to below 200nm and isolated line structures down to below 150nm (with effort). 300nm+ features are relatively "easy" to resolve. Layer-to-layer overlay accuracy is better than 30nm.

The system is configured for 4” wafers. The system is designed for high throughput, so shooting multiple 4" wafers is extremely fast, typically minutes per wafer, but any size other than 4-inch is difficult to work with (see below for more info). Additionally, exposure jobs are highly programmable, allowing for very flexible exposures of multiple aligned patterns from multiple masks/reticles in a single session, allowing for process optimization of large vs. small features in a single lithography.

The full field useable exposure area is limited to the intersection of a 31mm diameter circle and a rectangle of dimensions 22mm x 27mm. Users have stitched multiple photomasks together with success. See the [[Stepper 3 (ASML DUV)#Mask Design and CAD files|Mask Making Guidelines page]] for more info on exposure field sizes and how to order your mask plates.

'''Tutorial:''' If you are not familiar with the differences between Contact Litho and Stepper Litho, please review this short tutorial: [https://wiki.nanofab.ucsb.edu/w/images/c/cb/Demis_D_John_-_Stepper_Reticle_Layout_vs_Wafer_Layout.pdf Demis D. John - Stepper_Reticle_Layout_vs_Wafer_Layout.pdf]

===Photoresists Available===
''See [https://wiki.nanotech.ucsb.edu/w/index.php?title=Lithography_Recipes#Photolithography_Recipes PhotoLith. Recipes] for full process info & links to PR datasheets.''

*UV210-0.3 - Positive: 300nm nominal thickness
*UV6-0.8 - Positive: 800nm nominal thickness
*UV26-2.5 - Positive: 2.5um nominal thickness
*UVN2300-0.5 - Negative: 500nm nominal thickness

*DUV42P-6/DS-K101 - Bottom Anti-Reflective Coatings “BARC”
*PMGI/LOL1000/LOL2000 - Underlayers

AZ300MIF Developer for all processes

Many of these DUV PR's are also able to be exposed with [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]].

===Part Size Limits===
With staff support, mounted pieces down to 14mm in size can be exposed using a 4” wafer as a carrier. Flatness will typically be worse in this situation, so small <<500nm features will usually have bad uniformity across the mounted part due to focus variations. Edge bead on irregular pieces (eg. quarter-wafers/squares) will significantly reduce yield/uniformity.

Multi-layer Alignment on mounted parts is particularly difficult, requiring either semi-permanent mounting to the carrier (eg. BCB, SU8 etc.) or significant difficulty/effort to re-align the part to the carrier wafer on each lithography (≤100µm re-mounting accuracy needed).

At this time the maximum wafer size is 4” (100mm) wafers with SEMI standard wafer flat (not Notch).

===Service Provider===

*[http://www.asml.com ASML] - ASML performs quarterly periodic maintenance and provides on-demand support.

==Process Information==

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Lithography_Recipes#Photolithography_Recipes '''Process Recipes Page'''] '''> "Stepper 3"''' - ''Established recipes and corresponding linewidths, photoresists etc.''
*Sample size: 100 mm wafers with SEMI std. major flat
**''Piece-parts process is possible but difficult - contact supervisor for info''
*Alignment Accuracy: < 50 nm
*Minimum Feature Size: ≤150 nm isolated lines, ≤200 nm dense patterns
**''To achieve ≤200nm features with high uniformity, we recommend wafers with total thickness variation (TTV) ≤5µm, and designing your CAD with a smaller Image Size for the high-res. feature''.
*Wafer Thickness: Minimum ≈ 200µm, Maximum ≈ 1.1 mm
*Maximum Dose: ~100mJ
**''Non-chemically amplified EBL resists are not permissible due to this limit.''

===Maximum Wafer Bow===
Measured over 90mm on the [[Film Stress (Tencor Flexus)|Tencor Flexus]]

*'''Do not run wafers with bow values higher than the following values''', contact supervisor for advice if needed.
*Silicon wafers (~550µm thick): 100 µm will likely fail.
*Sapphire (less pliable), ≥60µm bow will intermittently fail - DO NOT RUN
**This applies especially for GaN-on-Sapphire, which often have high wafer bow.
*''Near these values, and you may lose the wafer inside the machine due to wafer vacuum error - DO NOT RUN if unsure.''
*''Substrate material and substrate thickness affect this limit - please contact [[Demis D. John|supervisor]] for advice.''
*You can '''stress-compensate''' wafers to reduce the wafer bow, eg. via dep. on the back side of the wafer. If you wafer is concave down, then depositing a compressive film on the back will reduce its curvature. Coat the backside of the wafer with compressive PECVD SiO2 or [[Sputtering Recipes#Si3N4 deposition .28IBD.29|IBD SiN]], or other compressive films for concave-down bow.

==Operating Procedures==
'''All procedures are access-restricted only to authorized users with a UCSB NetID (''YourNetID''@ucsb.edu), by vendor request.
Please contact [[Demis D. John|supervisor]] for access/training.'''

[https://drive.google.com/drive/folders/1U9-03qU2htQp_5x39LNq-mn5Q3vXXLDf?usp=drive_link '''ASML Operating Procedures'''] - access-restricted google drive folder of PAS 5500/300 operating procedures.

[https://docs.google.com/document/d/17jPek8P_SF1qRADS09ApoDgUiB_v0NFJsIVpkL-Kdag/edit#heading=h.fmorc9eu8hfz '''Stepper #3 Training Videos'''] - these provide bookmarked quick-reference to various tool procedures & programming.

*''To access, you must log in with your UCSB NetID, formatted like'' MyNetID''@ucsb.edu'' ''- this is a Google login!''
*''Please contact the [[Demis D. John|tool supervisor]] if you need access.''
*[[UCSB NetID Login Troubleshooting|'''''Trouble accessing?''''' ''Please click here for tips.'']]

===Training Procedure===
To get access to this tool, please do the following:

#Email the [[Demis D. John|supervisor]] for access to the training materials. Please provide your UCSB NetID.
#Study the [https://docs.google.com/document/d/17jPek8P_SF1qRADS09ApoDgUiB_v0NFJsIVpkL-Kdag/edit#heading=h.fmorc9eu8hfz training videos].
##If you are a technician and will never program jobs, only Part 1 is necessary.
#"Shadow" someone in your group who uses the machine, until you are completely comfortable with (1) wafer cleaning (critical), (2) reticle load/unload and (3) running a pre-made job. When you are ready, do step 4:
#Contact [[Demis D. John|the supervisor]] for an short hands-on check-off, after which you'll get [http://signupmonkey.ece.ucsb.edu SignupMonkey] access.

==Design Tools==

===Mask Design and CAD files===

*[https://wiki.nanofab.ucsb.edu/wiki/Stepper_Mask-Making_Guidelines_(Generic) '''Stepper Mask-Making Guidelines'''] - Generic info needed to design and order a reticle for any Stepper system. This is minimal unrestricted info that is viewable without additional paperwork.

*'''[https://docs.google.com/document/d/1b9YT11RPsl-UlLvN74hrQvG01OcYDL16r6I5lPOlBEo/edit?usp=sharing ASML-specific Mask Making Guidelines]''' - All the detailed info you need to design and order a reticle for this specific ASML system.
**''Access is restricted to trained users only - please contact [[Demis D. John|tool supervisor]] for access.''
*Tutorial: [https://wiki.nanofab.ucsb.edu/w/images/c/cb/Demis_D_John_-_Stepper_Reticle_Layout_vs_Wafer_Layout.pdf Demis D. John - Stepper_Reticle_Layout_vs_Wafer_Layout.pdf]

*See the [[Calculators + Utilities#CAD%20Files%20.26%20Templates|Calculators + Utilities > '''CAD Files & Templates''']] page for other useful CAD files, such as overlay verniers, vented fonts etc.

===UCSB Photomasks Available===

*[[ASML Stepper 3 - UCSB Test Reticles|UCSB DUV Reticles]] - Photomasks available with various Alignment Markers (contact, EBL), Resolution Testing etc.

=== Optical Proximity Correction: Going below resolution limit ===

* [https://drive.google.com/file/d/1Ivjq8_jd_1msA7Ap7ellArTZZ3soSLPe/view?usp=sharing General information and guide lines] - Provides information on OPC, use case examples, performance comparisons, how to order etc
* UCSB Nanofab users have access to order photomask plates with OPC corrections to help go below resolution limits of the tool
* [https://www.photronics.com/ Photronics] - OPC corrected mask plate provider for UCSB Nanofab

=== [[ASML Stepper 3 - Job Creator|JobCreator]] ===

* Create ASML Job files using python. Click the above [[ASML Stepper 3 - Job Creator|link for more info]].

==Recipes==

* '''[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Recipes > Lithography > Stepper Recipes > Stepper #3]]''' - starting processes for various DUV photoresists, including Dose/Focus values.

To calibrate your own Litho processes, you will need to:

* Run your own Focus Exposure Matrix - [https://docs.google.com/document/d/1_QIsYtew1uDlbUJCniApLz9_TYG2izwTxNpmoCbSuLI/edit?usp=drive_link this procedure] shows how to do this on the ASML software
* [[Lithography Calibration - Analyzing a Focus-Exposure Matrix]] - how to analyze an FEM

Litho. recipes for all our photolith. tools can be found on the [[Lithography Recipes#Photolithography Recipes|Photolithography Recipes]] page.

==Process Control Data==

*''The Process Group regularly measures the lithography Critical Dimension ("CD") and Wafer-stage Particulate Contamination for this tool, using a sensitive lithography process that will reveal small changes in Dose repeatability and wafer flatness.''
*[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0 '''Data Table for CD Uniformity and Particulate Contamination''']
*[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281 '''Plots of CD Repeatability''']

{|
|[[File:ASML CD Cals - Example Table.jpg|alt=ASML CD Calibration data - Screenshot of Table|none|thumb|300x300px|''Example of Data Table with SEM's of 320nm features. [https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0 Click for full data table.]''|link=https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0]]
|[[File:ASML CD Cals - Example Plot.jpg|alt=ASML CD Calibration Data - Screenshot of SPC Plot|none|thumb|''Example SPC Chart - Measured Critical Dimension "CD" versus Date.'' ''[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281 Click for current charts.]''|link=https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281]]
|}

Stepper 3 (ASML DUV)

2025-01-27T19:58:33Z

Gopimeena: /* Design Tools */

{{tool|{{PAGENAME}}
|picture=ASML.jpg
|type = Lithography
|super= Demis D. John
|location=Bay 7
|description = Deep-UV Stepper Photolithography
|model = PAS 5500/300
|manufacturer = [http://www.asml.com ASML]
|ToolType = Lithography
|recipe = Lithography
|materials =
|toolid=51
}}

==About==

===General Capabilities/Overview===
The ASML 5500 stepper is a 248nm (KrF) DUV stepper for imaging dense features down to below 200nm and isolated line structures down to below 150nm (with effort). 300nm+ features are relatively "easy" to resolve. Layer-to-layer overlay accuracy is better than 30nm.

The system is configured for 4” wafers. The system is designed for high throughput, so shooting multiple 4" wafers is extremely fast, typically minutes per wafer, but any size other than 4-inch is difficult to work with (see below for more info). Additionally, exposure jobs are highly programmable, allowing for very flexible exposures of multiple aligned patterns from multiple masks/reticles in a single session, allowing for process optimization of large vs. small features in a single lithography.

The full field useable exposure area is limited to the intersection of a 31mm diameter circle and a rectangle of dimensions 22mm x 27mm. Users have stitched multiple photomasks together with success. See the [[Stepper 3 (ASML DUV)#Mask Design and CAD files|Mask Making Guidelines page]] for more info on exposure field sizes and how to order your mask plates.

'''Tutorial:''' If you are not familiar with the differences between Contact Litho and Stepper Litho, please review this short tutorial: [https://wiki.nanofab.ucsb.edu/w/images/c/cb/Demis_D_John_-_Stepper_Reticle_Layout_vs_Wafer_Layout.pdf Demis D. John - Stepper_Reticle_Layout_vs_Wafer_Layout.pdf]

===Photoresists Available===
''See [https://wiki.nanotech.ucsb.edu/w/index.php?title=Lithography_Recipes#Photolithography_Recipes PhotoLith. Recipes] for full process info & links to PR datasheets.''

*UV210-0.3 - Positive: 300nm nominal thickness
*UV6-0.8 - Positive: 800nm nominal thickness
*UV26-2.5 - Positive: 2.5um nominal thickness
*UVN2300-0.5 - Negative: 500nm nominal thickness

*DUV42P-6/DS-K101 - Bottom Anti-Reflective Coatings “BARC”
*PMGI/LOL1000/LOL2000 - Underlayers

AZ300MIF Developer for all processes

Many of these DUV PR's are also able to be exposed with [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]].

===Part Size Limits===
With staff support, mounted pieces down to 14mm in size can be exposed using a 4” wafer as a carrier. Flatness will typically be worse in this situation, so small <<500nm features will usually have bad uniformity across the mounted part due to focus variations. Edge bead on irregular pieces (eg. quarter-wafers/squares) will significantly reduce yield/uniformity.

Multi-layer Alignment on mounted parts is particularly difficult, requiring either semi-permanent mounting to the carrier (eg. BCB, SU8 etc.) or significant difficulty/effort to re-align the part to the carrier wafer on each lithography (≤100µm re-mounting accuracy needed).

At this time the maximum wafer size is 4” (100mm) wafers with SEMI standard wafer flat (not Notch).

===Service Provider===

*[http://www.asml.com ASML] - ASML performs quarterly periodic maintenance and provides on-demand support.

==Process Information==

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Lithography_Recipes#Photolithography_Recipes '''Process Recipes Page'''] '''> "Stepper 3"''' - ''Established recipes and corresponding linewidths, photoresists etc.''
*Sample size: 100 mm wafers with SEMI std. major flat
**''Piece-parts process is possible but difficult - contact supervisor for info''
*Alignment Accuracy: < 50 nm
*Minimum Feature Size: ≤150 nm isolated lines, ≤200 nm dense patterns
**''To achieve ≤200nm features with high uniformity, we recommend wafers with total thickness variation (TTV) ≤5µm, and designing your CAD with a smaller Image Size for the high-res. feature''.
*Wafer Thickness: Minimum ≈ 200µm, Maximum ≈ 1.1 mm
*Maximum Dose: ~100mJ
**''Non-chemically amplified EBL resists are not permissible due to this limit.''

===Maximum Wafer Bow===
Measured over 90mm on the [[Film Stress (Tencor Flexus)|Tencor Flexus]]

*'''Do not run wafers with bow values higher than the following values''', contact supervisor for advice if needed.
*Silicon wafers (~550µm thick): 100 µm will likely fail.
*Sapphire (less pliable), ≥60µm bow will intermittently fail - DO NOT RUN
**This applies especially for GaN-on-Sapphire, which often have high wafer bow.
*''Near these values, and you may lose the wafer inside the machine due to wafer vacuum error - DO NOT RUN if unsure.''
*''Substrate material and substrate thickness affect this limit - please contact [[Demis D. John|supervisor]] for advice.''
*You can '''stress-compensate''' wafers to reduce the wafer bow, eg. via dep. on the back side of the wafer. If you wafer is concave down, then depositing a compressive film on the back will reduce its curvature. Coat the backside of the wafer with compressive PECVD SiO2 or [[Sputtering Recipes#Si3N4 deposition .28IBD.29|IBD SiN]], or other compressive films for concave-down bow.

==Operating Procedures==
'''All procedures are access-restricted only to authorized users with a UCSB NetID (''YourNetID''@ucsb.edu), by vendor request.
Please contact [[Demis D. John|supervisor]] for access/training.'''

[https://drive.google.com/drive/folders/1U9-03qU2htQp_5x39LNq-mn5Q3vXXLDf?usp=drive_link '''ASML Operating Procedures'''] - access-restricted google drive folder of PAS 5500/300 operating procedures.

[https://docs.google.com/document/d/17jPek8P_SF1qRADS09ApoDgUiB_v0NFJsIVpkL-Kdag/edit#heading=h.fmorc9eu8hfz '''Stepper #3 Training Videos'''] - these provide bookmarked quick-reference to various tool procedures & programming.

*''To access, you must log in with your UCSB NetID, formatted like'' MyNetID''@ucsb.edu'' ''- this is a Google login!''
*''Please contact the [[Demis D. John|tool supervisor]] if you need access.''
*[[UCSB NetID Login Troubleshooting|'''''Trouble accessing?''''' ''Please click here for tips.'']]

===Training Procedure===
To get access to this tool, please do the following:

#Email the [[Demis D. John|supervisor]] for access to the training materials. Please provide your UCSB NetID.
#Study the [https://docs.google.com/document/d/17jPek8P_SF1qRADS09ApoDgUiB_v0NFJsIVpkL-Kdag/edit#heading=h.fmorc9eu8hfz training videos].
##If you are a technician and will never program jobs, only Part 1 is necessary.
#"Shadow" someone in your group who uses the machine, until you are completely comfortable with (1) wafer cleaning (critical), (2) reticle load/unload and (3) running a pre-made job. When you are ready, do step 4:
#Contact [[Demis D. John|the supervisor]] for an short hands-on check-off, after which you'll get [http://signupmonkey.ece.ucsb.edu SignupMonkey] access.

==Design Tools==

===Mask Design and CAD files===

*[https://wiki.nanofab.ucsb.edu/wiki/Stepper_Mask-Making_Guidelines_(Generic) '''Stepper Mask-Making Guidelines'''] - Generic info needed to design and order a reticle for any Stepper system. This is minimal unrestricted info that is viewable without additional paperwork.

*'''[https://docs.google.com/document/d/1b9YT11RPsl-UlLvN74hrQvG01OcYDL16r6I5lPOlBEo/edit?usp=sharing ASML-specific Mask Making Guidelines]''' - All the detailed info you need to design and order a reticle for this specific ASML system.
**''Access is restricted to trained users only - please contact [[Demis D. John|tool supervisor]] for access.''
*Tutorial: [https://wiki.nanofab.ucsb.edu/w/images/c/cb/Demis_D_John_-_Stepper_Reticle_Layout_vs_Wafer_Layout.pdf Demis D. John - Stepper_Reticle_Layout_vs_Wafer_Layout.pdf]

*See the [[Calculators + Utilities#CAD%20Files%20.26%20Templates|Calculators + Utilities > '''CAD Files & Templates''']] page for other useful CAD files, such as overlay verniers, vented fonts etc.

===UCSB Photomasks Available===

*[[ASML Stepper 3 - UCSB Test Reticles|UCSB DUV Reticles]] - Photomasks available with various Alignment Markers (contact, EBL), Resolution Testing etc.

=== Optical Proximity Correction: Going below resolution limit ===

* [https://drive.google.com/file/d/1Ivjq8_jd_1msA7Ap7ellArTZZ3soSLPe/view?usp=sharing General information and guide lines] - Provides information on OPC, use case examples, performance comparisons, how to order etc
* UCSB Nanofab users have access to order photomask plates with OPC corrections to help go below resolution limits of the tool
* [https://www.photronics.com/ Photronics] - UCSB Nanofabs OPC corrected mask plate provider

=== [[ASML Stepper 3 - Job Creator|JobCreator]] ===

* Create ASML Job files using python. Click the above [[ASML Stepper 3 - Job Creator|link for more info]].

==Recipes==

* '''[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Recipes > Lithography > Stepper Recipes > Stepper #3]]''' - starting processes for various DUV photoresists, including Dose/Focus values.

To calibrate your own Litho processes, you will need to:

* Run your own Focus Exposure Matrix - [https://docs.google.com/document/d/1_QIsYtew1uDlbUJCniApLz9_TYG2izwTxNpmoCbSuLI/edit?usp=drive_link this procedure] shows how to do this on the ASML software
* [[Lithography Calibration - Analyzing a Focus-Exposure Matrix]] - how to analyze an FEM

Litho. recipes for all our photolith. tools can be found on the [[Lithography Recipes#Photolithography Recipes|Photolithography Recipes]] page.

==Process Control Data==

*''The Process Group regularly measures the lithography Critical Dimension ("CD") and Wafer-stage Particulate Contamination for this tool, using a sensitive lithography process that will reveal small changes in Dose repeatability and wafer flatness.''
*[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0 '''Data Table for CD Uniformity and Particulate Contamination''']
*[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281 '''Plots of CD Repeatability''']

{|
|[[File:ASML CD Cals - Example Table.jpg|alt=ASML CD Calibration data - Screenshot of Table|none|thumb|300x300px|''Example of Data Table with SEM's of 320nm features. [https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0 Click for full data table.]''|link=https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0]]
|[[File:ASML CD Cals - Example Plot.jpg|alt=ASML CD Calibration Data - Screenshot of SPC Plot|none|thumb|''Example SPC Chart - Measured Critical Dimension "CD" versus Date.'' ''[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281 Click for current charts.]''|link=https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281]]
|}

ICP Etching Recipes

2025-01-27T19:13:47Z

Gopimeena: /* GaAs Etch (Oxford ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|465x465px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|407x407px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:Copy of 22 013 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 16.32µm Deep Etched Silicon with UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===

*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

==Si Etching (Fluorine ICP Etcher)==
'''Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)'''

*'''SiVertHFv2 (⭐️Production)''' - Full Wafer Si etching with ~50% open area and resist mask
**This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]][[File:PRStrip 019 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etching (Fluorine ICP Etcher)==

*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min

===Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)===

**O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
**75W Bias can be helpful for difficult to remove polymers, eg. 2min
**Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]][[File:Dot Facet 00.jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]

==InP Ridge Etch (Oxford ICP Etcher)==
===Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1D39CagbK0rQcq3Dw-laTFUFcO3MQoL7M/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1D57XEbtQ4WvyFQURpLsWadxGNEwVRNkY/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

ICP Etching Recipes

2025-01-27T19:10:57Z

Gopimeena: /* GaAs Etch (Oxford ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|465x465px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|407x407px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:Copy of 22 013 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 16.32µm Deep Etched Silicon with UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===

*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

==Si Etching (Fluorine ICP Etcher)==
'''Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)'''

*'''SiVertHFv2 (⭐️Production)''' - Full Wafer Si etching with ~50% open area and resist mask
**This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]][[File:PRStrip 019 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etching (Fluorine ICP Etcher)==

*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min

===Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)===

**O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
**75W Bias can be helpful for difficult to remove polymers, eg. 2min
**Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]][[File:Dot Facet 00.jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]

==InP Ridge Etch (Oxford ICP Etcher)==
===Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1D39CagbK0rQcq3Dw-laTFUFcO3MQoL7M/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1D57XEbtQ4WvyFQURpLsWadxGNEwVRNkY/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20 Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

ICP Etching Recipes

2025-01-09T23:51:01Z

Gopimeena: /* GaAs Etch (Oxford ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|465x465px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|407x407px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:Copy of 22 013 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 16.32µm Deep Etched Silicon with UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===

*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

==Si Etching (Fluorine ICP Etcher)==
'''Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)'''

*'''SiVertHFv2 (⭐️Production)''' - Full Wafer Si etching with ~50% open area and resist mask
**This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]][[File:PRStrip 019 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etching (Fluorine ICP Etcher)==

*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min

===Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)===

**O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
**75W Bias can be helpful for difficult to remove polymers, eg. 2min
**Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]][[File:Dot Facet 00.jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]

==InP Ridge Etch (Oxford ICP Etcher)==
===Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1D39CagbK0rQcq3Dw-laTFUFcO3MQoL7M/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1D57XEbtQ4WvyFQURpLsWadxGNEwVRNkY/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Ie6_7lI9oAbOihy27W6gMjLz-FUG211P/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20 Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

ICP Etching Recipes

2025-01-09T23:48:53Z

Gopimeena: /* GaAs Etch (Oxford ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|465x465px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|407x407px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:Copy of 22 013 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 16.32µm Deep Etched Silicon with UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===

*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

==Si Etching (Fluorine ICP Etcher)==
'''Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)'''

*'''SiVertHFv2 (⭐️Production)''' - Full Wafer Si etching with ~50% open area and resist mask
**This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]][[File:PRStrip 019 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etching (Fluorine ICP Etcher)==

*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min

===Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)===

**O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
**75W Bias can be helpful for difficult to remove polymers, eg. 2min
**Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]][[File:Dot Facet 00.jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]

==InP Ridge Etch (Oxford ICP Etcher)==
===Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1D39CagbK0rQcq3Dw-laTFUFcO3MQoL7M/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1D57XEbtQ4WvyFQURpLsWadxGNEwVRNkY/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
*''[https://docs.google.com/document/d/1DHklT0LJloydprdeqyQEPZuWRRAVMBzF/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Std GaAs Etch - BCl3/Ar - 20 Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

ICP Etching Recipes

2025-01-07T01:09:13Z

Gopimeena: /* Process Control Data (Oxford ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|465x465px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|407x407px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:Copy of 22 013 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 16.32µm Deep Etched Silicon with UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===

*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

==Si Etching (Fluorine ICP Etcher)==
'''Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)'''

*'''SiVertHFv2 (⭐️Production)''' - Full Wafer Si etching with ~50% open area and resist mask
**This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]][[File:PRStrip 019 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etching (Fluorine ICP Etcher)==

*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min

===Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)===

**O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
**75W Bias can be helpful for difficult to remove polymers, eg. 2min
**Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiN mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]][[File:Dot Facet 00.jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]

==InP Ridge Etch (Oxford ICP Etcher)==
===Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1D39CagbK0rQcq3Dw-laTFUFcO3MQoL7M/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1D57XEbtQ4WvyFQURpLsWadxGNEwVRNkY/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
This recipe also provides a starting point for '''GaSb'''-based etches.

*GaAs-based materials - etch recipe available on tool - ''provided by Oxford, not yet qualified internally''
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

ICP Etching Recipes

2025-01-07T01:08:45Z

Gopimeena: /* GaN Etch (Oxford ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

==Process Control Data (DSEiii)==
'''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)'''

* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots'''][[File:DSE plot.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281]]

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|465x465px|Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|407x407px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:Copy of 22 013 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 16.32µm Deep Etched Silicon with UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}
::

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Process Control Data (Fluorine ICP Etcher)==

===SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===

*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots'''][[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]

==Si Etching (Fluorine ICP Etcher)==
'''Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)'''

*'''SiVertHFv2 (⭐️Production)''' - Full Wafer Si etching with ~50% open area and resist mask
**This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots'''][[File:FICP-Si.png|alt=example of Process Control Charts|none|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]][[File:PRStrip 019 (1).jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

==SiO2 Etching (Fluorine ICP Etcher)==

*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
**''Ning Cao & Bill Mitchell, 2019-06''
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Etch also works well with PR masking''
**''Chemistry: CHF3/CF4''
**''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**50W Bias: ('''recommended''')
***Selectivity to photoresist: 1.10–1.20
***SiO2 selectivity to Ru: 36
***SiO2 etch rate: 263nm/min
**200W Bias:
***SiO2 selectivity to Ru: 38
***SiO2 etch rate: 471nm/min
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===

*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**1min

===Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)===

**O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
**75W Bias can be helpful for difficult to remove polymers, eg. 2min
**Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

==Process Control Data (Panasonic 2)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 2)===

*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl2N2]

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

==Process Control Data (Oxford ICP Etcher)==

===[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Process Control Data for "Std InP Ridge Etch" Cl2/CH4/H2/60°C]===
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

=== [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 Process Control Data for "GaN Etch" (Cl2/BCl3/Ar/200°C)] ===
Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiO2 mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]][[File:Dot Facet 00.jpg|alt=Example SEM image|none|thumb|412x412px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]

==InP Ridge Etch (Oxford ICP Etcher)==
===Low-Temp (60°C) Process===

*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''[https://drive.google.com/file/d/1D39CagbK0rQcq3Dw-laTFUFcO3MQoL7M/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1D57XEbtQ4WvyFQURpLsWadxGNEwVRNkY/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==GaAs Etch (Oxford ICP Etcher)==
This recipe also provides a starting point for '''GaSb'''-based etches.

*GaAs-based materials - etch recipe available on tool - ''provided by Oxford, not yet qualified internally''
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

Lithography Recipes

2024-09-17T22:55:07Z

Gopimeena: /* Recipes Table (S-Cubed Flexi) */ Added developer recipes from 25sec to 45sec

__NOTOC__
{| class="wikitable"
|+
!Table of Contents
|-
|
==='''<big>Photolithography Processes</big>'''===

#'''UV Optical Lithography'''
#*[[#PositivePR |'''Stocked Lithography Chemical + Datasheets''']]
#**''Lists all stocked photolith. chemicals, PRs, strippers, developers, and links to the chemical's application notes/datasheet, which detail the spin curves and nominal processes.''
#*[[#Photolithography_Recipes |'''Photo Lithography Recipe section''']]
#**''Starting recipes (spin, bake, exposure, develop etc.) for all photolith. tools.''
#**''Substrate/surface materials/pattern size can affect process parameters. Users may need to run Focus/Exposure Arrays/Matrix (FEA's/FEM's) with these processes to achieve high-resolution.''
#**[[Contact Alignment Recipes|Contact Aligner Recipes]]
#***[[Contact Alignment Recipes#Suss Aligners .28SUSS MJB-3.29|Suss MJB Aligners]]
#***[[Contact Alignment Recipes#Contact Aligner .28SUSS MA-6.29|Suss MA6]]
#**[[Stepper Recipes|Stepper Recipes]]
#***[[Stepper Recipes#Stepper 1 .28GCA 6300.29|Stepper #1: GCA 6300]] (I-Line)
#***[[Stepper Recipes#Stepper 2 .28AutoStep 200.29|Stepper #2: GCA Autostep 200]] (I-Line)
#***[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Stepper #3: ASML PAS 5500/300]] (DUV)
#**[[Direct-Write Lithography Recipes|Direct-Write Recipes]]
#***[[Direct-Write Lithography Recipes#Maskless Aligner .28Heidelberg MLA150.29|Heidelberg MLA150]]
#***[[Lithography Recipes#E-Beam Lithography Recipes|JEOL JBX-6300FS EBL]]
#***[[Lithography Recipes#FIB Lithography Recipes .28Raith Velion.29|Raith Velion FIB]]
#**[[Lithography Recipes#Automated Coat.2FDevelop System Recipes .28S-Cubed Flexi.29|Automated Coater Recipes (S-Cubed Flexi)]]
#[[Lithography Recipes#General Photolithography Techniques|'''General Photolithography Techniques''']]
#*''Techniques for improving litho. or solving common photolith. problems.''
#'''[[Lithography Recipes#Lift-Off Recipes|Lift-Off Recipes]]'''
#*''Verified Recipes for lift-off using various photolith. tools''
#*''General educational description of this technique and it's limitations/considerations.''
#'''E-beam Lithography'''
#*[[#E-Beam_Lithography_Recipes |E-Beam Lithography Recipes]]
#**''Has links to starting recipes. Substrates and patterns play a large role in process parameters.''
#*[[#EBLPR |EBL Photoresist Datasheets]]
#**''Provided for reference, also showing starting recipes and usage info.''
#'''[[Lithography Recipes#Holography Recipes|Holography]]'''
#*''For 1-D and 2-D gratings with 220nm nominal period, available on substrates up to 1 inch square.''
#*''Recipes for silicon substrates are provided, and have been translated to other substrates by users.''
#*''Datasheets are provided with starting recipes and usage info.''
#'''[[Lithography Recipes#Edge-Bead Removal Techniques|Edge-Bead Removal]]'''
#*''Edge photoresist removal methods needed for clamp-based etchers''
#*''Improves resolution for contact lithography''
|-
|

==='''<big>Photolithography Chemicals/Materials</big>'''===

#'''[[#Underlayers |Underlayers]]'''
#*''These are used beneath resists for both adhesive purposes and to enable bi-layer lift-off profiles for use with photoresist.''
#*''Datasheets are provided.''
#'''[[#AntiReflectionCoatings |Anti-Reflection Coatings]]''':
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Bottom Anti-Reflection Coatings (BARC) are used in the stepper systems, underneath the resists to eliminate substrate reflections that can affect resolution and repeatability for small, near resolution limited, feature sizes.''
#*''Datasheets are provided for reference on use of the materials.''
#'''[[#ContrastEnhancement |Contrast Enhancement Materials (CEM)]]'''
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Used for resolution enhancement. Not for use in contact aligners, typically used on I-Line Steppers.''
#*''Datasheets provided with usage info.''
#'''[[#AdhesionPromoters |Adhesion Promoters]]'''
#*''These are used to improve wetting of photoresists to your substrate.''
#*''Datasheets are provided on use of these materials.''
#'''[[#SpinOnDielectrics |Low-K Spin-on Dielectrics]]'''
#*[[Lithography Recipes#SpinOnDielectrics|Spin-On Dielectrics]]
#**''Datasheets for BCB, Photo-BCB, and SOG (spin-on-glass) for reference on use.''
#*[[#Low-K_Spin-On_Dielectric_Recipes |Low-K Spin-On Dielectric Recipes]]
#**''Recipes for usage of some spin-on dielectrics.''
#'''[[#Developers |Developers and Removers]]'''
#*''Datasheets provided for reference.''
#*''Remover and Photoresist Strippers are used to dissolve PR during lift-off or after etching.''
|}

==General Photolithography Techniques==

====[[Photolithography - Improving Adhesion Photoresist Adhesion|'''HMDS Process for Improving Adhesion''']]====

*''Use these procedures if you are finding poor adhesion PR lifting-off), or for chemicals (like BHF) that attack the PR adhesion interface strongly.''

====[[Photolithography - Manual Edge-Bead Removal Techniques|'''Edge-Bead Removal Techniques''']]====

*''These techniques are required for loading full-wafers into etchers that use top-side clamps, to prevent photoresist from sticking to the clamp (and potentially destroying your wafer).''
*''For contact lithography, this improves the proximity of the mask plate and sample, improving resolution. For some projection systems, such as the [[Maskless Aligner (Heidelberg MLA150)|Maskless Aligner]], EBR can help with autofocus issues.''

====[https://www.microchemicals.com/technical_information/reflow_photoresist.pdf '''Photoresist reflow (MicroChem)''']====

*''To create slanted sidewalls or curved surfaces.''

==Photolithography Recipes==

*'''R''': ''Recipe is available. Clicking this link will take you to the recipe.''
*'''A''': ''Material is available for use, but no recipes are provided.''

==='''Process Ranking Table'''===
Processes in the table above are ranked by their "''Process Maturity Level''" as follows:
{| class="wikitable"
!Process Level
! colspan="11" |Description of Process Level Ranking
|-
|A
| colspan="11" |Process '''A'''llowed and materials available but never done
|-
|R1
| colspan="11" |Process has been run at least once
|-
|R2
| colspan="11" |Process has been run and/or procedure is documented or/and data available
|-
|R3
| colspan="11" |Process has been run, procedure is documented, and data is available
|-
|R4
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''or''' lookahead/in-situ control available
|-
|R5
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''and''' lookahead/in-situ control available
|-
|R6
| colspan="11" |Process has a documented procedure, regular ( ≥4x per year) data, and control charts & limits available
|}

''Click the tool title to go to recipes for that tool.''

''Click the photoresist title to get the datasheet, also found in [[Lithography Recipes#Chemicals Stocked .2B Datasheets|Stocked Chemicals + Datasheets]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|-
! colspan="7" height="45" |<div style="font-size: 150%;">Photolithography Recipes</div>

|-
| bgcolor="#EAECF0" |
! colspan="2" align="center" |'''[[Contact Alignment Recipes|<big>Contact Aligner Recipes</big>]]'''
! colspan="3" align="center" |'''[[Stepper Recipes|<big>Stepper Recipes</big>]]'''
! align="center" |[[Direct-Write Lithography Recipes|Direct-Write Litho. Recipes]]
|-
! width="150" bgcolor="#D0E7FF" align="center" |'''Positive Resists'''
{{LithRecipe Table}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[[:File:AXP4000pb-Datasheet.pdf|AZ4110]]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)|R1}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4210]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)|R1}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4330RS]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/a2/Az_p4620_photoresist_data_package.pdf AZ4620]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/8b/OCG825-Positive-Resist-Datasheet.pdf OCG 825-35CS]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-0.9]
|A
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)|R4}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)|R5}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)|R4}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-1.8]
|A
|A
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)|R4}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)|R4}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-3.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)|R4}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)|R4}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-7.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)|R4}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)|R4}}
|
|{{rl|MLA Recipes|Positive_Resist_.28MLA150.29}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/be/3600_D%2C_D2v_Spin_Speed_Curve.pdf THMR-IP3600 HP D]
|
|
|A
|A
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)|R5}}
|
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/ff/UV210-Positive-Resist-Datasheet.pdf UV210-0.3]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/UV26-Positive-Resist-Datasheet.pdf UV26-2.5]
|
|
|
|
|A
|
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Negative Resists'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/b0/AZ5214-Negative-Resist-Datasheet.pdf AZ5214-EIR]
|{{rl|Contact_Alignment_Recipes|Negative Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2020]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)|R4}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)|R4}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)|R4}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2035]
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |
| bgcolor="EEFFFF" |A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2070]
|A
|A
|{{Rl|Stepper_Recipes|Negative_Resist_.28GCA_6300.29|R2}}
|A
|
|A
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/82/AZnLOF5510-Negative-Resist-Datasheet.pdf AZnLOF 5510]
|A
|A
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/c/c9/UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf UVN30-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Negative Resist (ASML DUV)|R6}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/7/78/SU-8-2015-revA.pdf SU-8 2005,2010,2015]
|A
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/2c/SU-8-2075-revA.pdf SU-8 2075]
|A
|A
|A
|A
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |NR9-[//wiki.nanotech.ucsb.edu/w/images/8/8f/NR9-1000PY-revA.pdf 1000],[//wiki.nanotech.ucsb.edu/w/images/7/71/NR9-3000PY-revA.pdf 3000],[//wiki.nanotech.ucsb.edu/w/images/f/f9/NR9-6000PY-revA.pdf 6000]PY
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)|R4}}
|
|A
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Anti-Reflection Coatings'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/33/XHRiC-Anti-Reflective-Coating.pdf XHRiC-11]
|
|
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/DUV42P-Anti-Reflective-Coating.pdf DUV42-P]
|
|
|
|
|{{rl|Stepper Recipes|DUV-42P-6|R3}}
|
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101-304]
|
|
|
|
|{{rl|Stepper Recipes|DS-K101-304|R3}}
|
|-
! bgcolor="#D0E7FF" align="center" |
{{LithRecipe Table}}
|}


==Lift-Off Recipes==

*{{fl|Liftoff-Techniques.pdf|Lift-Off Description/Tutorial}}
**How it works, process limits and considerations for designing your process
*[[Lift-Off with I-Line Imaging Resist + LOL2000 Underlayer|I-Line Lift-Off: Bi-Layer Process with LOL2000 Underlayer]]
**''Single Expose/Develop process for simplicity''
**''Up to ~130nm metal thickness & ≥500nm-1000nm gap between metal.''
**''Can use any I-Line litho tool (GCA Stepper, Contact aligner, MLA)''
*{{fl|Bi-LayerContactprocesswithPMGI.pdf|I-Line Lift-Off: Bi-Layer Process with PMGI Underlayer and Contact Aligner}}
**''Multiple processes for Metal thicknesses ~800nm to ~2.5µm''
**''Uses multiple DUV Flood exposure/develop cycles to create undercut.''
**''Can be transferred to other I-Line litho tools (Stepper, MLA etc.)''
*[[Lift-Off with DUV Imaging + PMGI Underlayer|DUV Lift-Off: UV6 Imaging Resist + PMGI Underlayer]]
**''Single-expose/develop process''
**''Up to ~65nm metal thickness & ~350nm gap between metal''
**''Use thicker PMGI for thicker metals''

==[[E-Beam Lithography System (JEOL JBX-6300FS)|E-Beam Lithography Recipes (JEOL JBX-6300FS)]]==

*Under Development.

==[[Focused Ion-Beam Lithography (Raith Velion)|FIB Lithography Recipes (Raith Velion)]]==
''To Be Added''

==[[Automated Coat/Develop System (S-Cubed Flexi)|Automated Coat/Develop System Recipes (S-Cubed Flexi)]]==
Recipes pre-loaded on the S-Cubed Flexi automated coat/bake/develop system. Only staff may write new recipes, contact the tool supervisor for more info.

===Available Variations===

*We have different recipes with varyious UV6 spin speeds - the same spin speed optionss as found on our manual Headway spinners. This allows for PR thickness control. See the linked UV6 datasheets below for thickness vs. rpm spin curves.
*DSK is recommended to be spun at 1.5krpm (~40nm) for best anti-reflection properties. 5krpm (~20nm) recipes are also provided for historical/legacy processes.
*DSK can be baked at either 220C to act as a Dry-etchable BARC (similar to DUV-42P), or at lower temps as a developable BARC (no dry etch required).
*"Chain" recipes (with DSK+UV6 spin/cured in succession) are only available for DSK Baked at 185C & 220C, and all UV6 Spin-speed variations. For the other DSK temps you can use the single-PR "Routes".

===Recipes Table (S-Cubed Flexi)===
{| class="wikitable"
|+''Ask [[Tony Bosch|Staff]] if you need a new recipe.''
|'''''Coating Material'''''
|'''''Route/Chain'''''
|'''''Name''': (User: "UCSB Users")''
|'''''Spin Speed (krpm)'''''
|'''''Bake Temp'''''
|'''''Notes'''''
|-
! colspan="6" |
|-
! colspan="6" |BEFORE LITHOGRAPHY (PR Coat and Bake)
|-
! colspan="6" |
|-
|'''''Hotplate Set'''''
|Route
| colspan="4" |To pre-set the DSK Hotplate temp (HP4).
Note: Only HP4 can be changed. HP1-HP3 remains fixed. HP1=135°C, HP2=170°C & HP3=170°C
|-
|
|
|HP4-SET-220C
|
|220°C
|Will over shoot +-2°C when done.
|-
|
|
|HP4-SET-210C
|
|210°C
|
|-
|
|
|HP4-SET-200C
|
|200°C
|
|-
|
|
|HP4-SET-185C
|
|185°C
|
|-
| colspan="6" |
|-
|'''''[https://wiki.nanotech.ucsb.edu/wiki/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101]'''''
|Route
| colspan="4" |''DSK101 Develop Rate depends on Bake temp - you can use this to control undercut.'' ''See: [[DS-K101-304 Bake Temp. versus Develop Rate|DSK Bake vs. Dev rate]]''
DSK101 spun at 1.5K is equivalent to DUV-42P. See: [[Stepper Recipes#Anti-Reflective Coatings]]

185°C bake allows the DSK to dissolve during develop, and allows for undercut (may lift-off small features)

220°C bake allows DSK to be used as dry-etchable BARC, requiring O2 etch to remove.

'''Note: All PR coat recipes have EBR backside clean steps included in the recipe.'''
|-
|1.5krpm recipes
|
|COAT-DSK101-304[1.5K]-185C
|1.5krpm
|185°C
|Requires: HP4=185°C,
|-
|
|
|COAT-DSK101-304[1.5K]-200C
|1.5krpm
|200°C
|Requires: HP4=200°C
|-
|
|
|COAT-DSK101-304[1.5K]-210C
|1.5krpm
|210°C
|Requires: HP4=210°C
|-
|
|
|COAT-DSK101-304[1.5K]-220C
|1.5krpm
|220°C
|Requires: HP4=220°C,
|-
| colspan="6" |
|-
|5krpm recipes
|
|COAT-DSK101-304[5K]-185C
|5.0krpm
|185°C
|Requires: HP4=185°C,
|-
|
|
|COAT-DSK101-304[5K]-200C
|5.0krpm
|200°C
|Requires: HP4=200°C
|-
|
|
|COAT-DSK101-304[5K]-210C
|5.0krpm
|210°C
|Requires: HP4=210°C
|-
|
|
|COAT-DSK101-304[5K]-220C
|5.0krpm
|220°C
|Requires: HP4=220°C,
|-
| colspan="6" |
|-
|'''''[https://wiki.nanofab.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]'''''
|Route
|COAT-UV6[2K]-135C
|2.0krpm
|135°C
|Requires: HP1=135°C
|-
|varying spin speed
|
|COAT-UV6[2.5K]-135C
|2.5krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[3K]-135C
|3.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[3.5K]-135C
|3.5krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[4K]-135C
|4.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[5K]-135C
|5.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[6K]-135C
|6.0krpm
|135°C
|Requires: HP1=135°C
|-
| colspan="6" |'''''UV6 Coat with Developable BARC underlayer:'''''
|-
|'''''DS-K101 @ 185°C'''''
'''''+ UV6'''''
|Chain
|COAT-DSK101[1.5K]-185C-UV6[2K]-135C
|DSK: 1.5krpm
UV6: 2.0krpm
|DSK: 185°C
UV6: 135°C
|Requires:
– HP4=185°C

– HP1=135°C

Plan for ~10-15 min per wafer.
|-
|1.5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[1.5K]-185C-UV6[2.5K]-135C
|DSK: 1.5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3K]-135C
|DSK: 1.5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3.5K]-135C
|DSK: 1.5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[4K]-135C
|DSK: 1.5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[5K]-135C
|DSK: 1.5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[6K]-135C
|DSK: 1.5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |
|-
|5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[5K]-185C-UV6[2K]-135C
|DSK: 5krpm
UV6: 2.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[2.5K]-135C
|DSK: 5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3K]-135C
|DSK: 5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3.5K]-135C
|DSK: 5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[4K]-135C
|DSK: 5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[5K]-135C
|DSK: 5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[6K]-135C
|DSK: 5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |'''''UV6 Coat with Dry-Etchable BARC underlayer:'''''
|-
|'''''DS-K101 @ 220°C'''''
'''''+ UV6'''''
|Chain
|COAT-DSK101[1.5K]-220C-UV6[2K]-135C
|DSK: 1.5krpm
UV6: 2.0krpm
|DSK: 220°C
UV6: 135°C
|Requires:
– HP4=220°C

– HP1=135°C

Plan for ~10-15 min per wafer.
|-
|1.5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[1.5K]-220C-UV6[2.5K]-135C
|DSK: 1.5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3K]-135C
|DSK: 1.5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3.5K]-135C
|DSK: 1.5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[4K]-135C
|DSK: 1.5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[5K]-135C
|DSK: 1.5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[6K]-135C
|DSK: 1.5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |
|-
|5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[5K]-220C-UV6[2K]-135C
|DSK: 5krpm
UV6: 2.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[2.5K]-135C
|DSK: 5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3K]-135C
|DSK: 5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3.5K]-135C
|DSK: 5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[4K]-135C
|DSK: 5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[5K]-135C
|DSK: 5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[6K]-135C
|DSK: 5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
! colspan="6" |
|-
! colspan="6" |AFTER LITHOGRAPHY (PEB and Developing)
|-
! colspan="6" |
|-
|'''''PEB Wafer Bake'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) for 90sec and cool for 15sec
|-
|
|
|BAKE-135C-90S
|
|135°C
|Requires: HP1=135°C
|-
| colspan="6" |
|-
|'''''PEB and Developing'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) 90sec, cool 15sec, develop using AZ300MIF and water rinse 60sec

WARNING: DONOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE
|-
|Varying developer time
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-10S
|Developer chuck: 300rpm
|135°C
|Requires: HP1=135°C
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-15S
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-20S
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-25S
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-30S
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-35S
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-40S
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-45S
|same as above
|same as above
|same as above
|-
| colspan="6" |
|-
|'''Developing'''
|Route
| colspan="4" |To only develop wafer using AZ300MIF and water rinse 60sec

WARNING: DONOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE
|-
|Varying developer time
|
|DEV[MIF300]-SPIN[300RPM]-10S
|Developer chuck: 300rpm
|135°C
|Requires: HP1=135°C
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-15S
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-20S
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-25S
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-30S
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-35S
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-40S
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-45S
|same as above
|same as above
|same as above
|-
|
|
|
|
|
|
|}
==[[Holographic Lith/PL Setup (Custom)|Holography Recipes]]==
''The Holography recipes here use the BARC layer XHRiC-11 & the high-res. I-Line photoresist THMR-IP3600HP-D.''

*{{fl|Holography_Process_for_1D-lines_and_2D-dots_%28ARC-11_%26_THMR-IP3600HP-D%29-updated-4-8-2021.pdf|Standard Holography Process - on SiO2 on Si}}
*{{fl|Holography-Process-Variation-revA.pdf|Holography Process Variations - Set-up Angle - Etching into SiO2 and Si}}
*{{fl|05-SiO2_Nano-structure_Etch.pdf|Etch SiO2 Nano-structure - Changing Side-wall Angle - Etching into Si with a different line-width}}
*{{fl|30-Redicing_Nanowire_Diameter_by_Thermal_Oxidation_and_Vapored_HF_Etch.pdf|Reduce SiO2 Nanowire Diameter - Thermal Oxidation - Vapor HF Etching}}

==Low-K Spin-On Dielectric Recipes==

*{{fl|Lithography-BCB-photo-lowk-dielectric-spinon-4024-40-revA.docx|Photo BCB (4024-40)}}
*{{fl|BCB-cyclotene-3000-revA.pdf|Standard BCB (3022-46)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|SOG (T512B)}}

==Chemicals Stocked + Datasheets==
''The following is a list of the lithography chemicals we stock in the lab, with links to the datasheets for each. The datasheets will often have important processing info such as spin-speed vs. thickness curves, typical process parameters, bake temps/times etc.''
{|
|- valign="top"
| width="400" |
;<div id="PositivePR"><big>Positive Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AXP4000pb-Datasheet.pdf|AZP4000 (AZ4110, AZ4210, AZ4330)}}
*{{Fl|Az_p4620_photoresist_data_package.pdf|AZ P4620}}
*{{fl|OCG825-Positive-Resist-Datasheet.pdf|OCG825}}
*{{fl|SPR220-Positive-Resist-Datasheet.pdf|SPR220 (SPR220-3, SPR220-7)}}
*{{fl|SPR955-Positive-Resist-Datasheet.pdf|SPR955CM (SPR955CM-0.9, SPR955CM-1.8)}}
*THMR-3600HP (Thin I-Line & Holography)
**{{fl|THMR_iP_3500_iP3600.pdf|Evaluation Results: THMR-3600HP}}
**{{fl|3600_D,_D2v_Spin_Speed_Curve.pdf|Spin Curves for THMR-3600HP}}
**{{fl|THMR-iP3600_HP_D_20140801_(B)_GHS_US.pdf|Safety Datasheet for THMR-3600HP}}

'''''DUV-248nm'''''

*{{fl|UV210-Positive-Resist-Datasheet.pdf|UV210-0.3}}
*{{fl|UV6-Positive-Resist-Datasheet.pdf|UV6-0.8}}
*{{fl|UV26-Positive-Resist-Datasheet.pdf|UV26-2.5}}

;<div id="NegativePR"><big>Negative Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AZ5214-Negative-Resist-Datasheet.pdf|AZ5214}}
*{{fl|AZnLOF5510-Negative-Resist-Datasheet.pdf|AZnLOF5510}}
*{{fl|AZnLOF2020-Negative-Resist-Datasheet.pdf|AZnLOF2000 (AZnLOF2020, AZnLOF2035, AZnLOF2070)}}
*{{fl|NR9-1000PY-revA.pdf|Futurrex NR9-1000PY(use AZ300MIF dev)}}
*{{fl|NR9-3000PY-revA.pdf|Futurrex NR9-3000PY(use AZ300MIF dev)}}
*{{fl|NR9-6000PY-revA.pdf|Futurrex NR9-6000PY(use AZ300MIF dev)}}
*{{fl|SU-8-2015-revA.pdf|SU-8-2005,2010, 2015}}
*{{fl|SU-8-2075-revA.pdf|SU-8-2075}}

'''''DUV-248nm'''''

*{{fl|UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf|UVN-30-0.8}}

;<div id="Underlayers"><big>Underlayers</big></div>

*{{fl|PMGI-Underlayer-Datasheet.pdf|PMGI (PMGI SF3,5,8,11,15)}}
*{{fl|LOL2000-Underlayer-Datasheet.pdf|Shipley LOL2000}}

;<div id="EBLPR"><big>E-beam resists</big></div>

*{{fl|PMMA-E-Beam-Resist-Datasheet.pdf|PMMA (PMMA, P(MMA-MAA) copolymer)}}
*{{fl|maN2403-E-Beam-Resist-Datasheet.pdf|maN 2403}}

;<div id="NanoImprinting"><big>Nanoimprinting</big></div>

*{{fl|NX1020-Nanoimprinting-Datasheet.pdf|NX1020}}
*{{fl|MRI-7020-Nanoimprinting-Datasheet.pdf|MRI-7020}}
*{{fl|Mr-UVCur21.pdf|MR-UVCur21}}
*{{fl|OrmoStamp-NIL-Lithography-UV-Soft-RevA.pdf|Ormostamp}}

|
;<div id="ContrastEnhancement"><big>Contrast Enhancement Materials</big></div>

*{{fl|CEM365iS-Contrast-Enhancement-Datasheet.pdf|CEM365iS}}

;<div id="AntiReflectionCoatings"><big>Anti-Reflection Coatings</big></div>

*{{fl|XHRiC-Anti-Reflective-Coating.pdf|XHRiC-11 (i-line)}}
*{{fl|DUV42P-Anti-Reflective-Coating.pdf|DUV42P-6 (DUV) (For AR2 replacement)}}
*{{fl|DS-K101-304-Anti-Reflective-Coating.pdf|DS-K101-304 (DUV developable BARC)}}

;<div id="AdhesionPromoters"><big>Adhesion Promoters</big></div>

*HMDS
*AP3000 BCB Adhesion Promoter
*{{fl|OMNICOAT-revA.pdf|Omnicoat, SU-8 Adhesion Promoter}}
*{{fl|OrmoPrime-NIL-Adhesion-RevA.pdf|Ormoprime08-Ormostsmp Adhesion Promoter}}

;<div id="SpinOnDielectrics"><big>Spin-On Dielectrics</big></div>

''Low-K Spin-On Dielectrics such as Benzocyclobutane and Spin-on Glass''

*{{fl|BCB-cyclotene-3000-revA.pdf|BCB, Cyclotene 3022-46(Not Photosensitive)}}
*{{fl|BCB-cyclotene-4000-revA.pdf|PhotoBCB, Cyclotene 4024-40(Negative Polarity)}}
*{{fl|BCB-adhesion.pdf|BCB Adhesion Notes from Vendor}}
*{{fl|BCB-rework.pdf|BCB rework Notes from Vendor}}
*{{fl|512B-Datasheet-revA.pdf|Spin-on-Glass, Honeywell 512B (Not Photosensitive)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|Honeywell 512B Apps Data}}

;<div id="Developers"><big>Developers</big></div>

*{{fl|AZ400K-Developer-Datasheet.pdf|AZ400K (AZ400K, AZ400K1:4)}}
*{{fl|AZ300MIF-Developer-Datasheet.pdf|AZ300MIF}}
*DS2100 BCB Developer
*SU-8 Developer
*101A Developer (for DUV Flood Exposed PMGI)

;<div id="PRRemovers"><big>Photoresist Removers</big></div>

*[http://www.microchemicals.com/products/remover_stripper/nmp.html AZ NMP]
**''This replaces {{fl|1165-Resist-Remover.pdf|1165}}''
*{{fl|AZ300T-Resist-Remover.pdf|AZ300T}}
*{{fl|RemoverPG-revA.pdf|Remover PG, SU-8 stripper}}
*AZ EBR ("Edge Bead Remover", PGMEA)

|}

[[Category: Processing]]
[[category: Lithography]]
[[category: Recipes]]

Gopikrishnan G M

2024-08-15T14:52:03Z

Gopimeena: /* About */ Updated Gopi's personal page

{{staff|{{PAGENAME}}
|position = Process Scientist
|room = 1109B
|phone = (805) 893-5223
|cell =
|email = gopimeena@ucsb.edu
}}
==About==
Gopikrishnan Gopalakrishnan Meena graduated with his Ph.D in 2021 from the [https://photon.soe.ucsc.edu/ Applied Optics] research group of Prof. Holger Schmidt as UCSC. He worked on creating various photonic platforms integrated with microfluidics for clinical diagnostics application. His Ph.D work was done in collaboration with Prof. Aaron Hawkin’s [https://hawkins.byu.edu/ Semiconductor Devices and Microfabrication] lab at BYU and has been published in more than 10 journal papers with 5 first author ships. From 2021 till 2024 he worked at ULL Technologies as a senior research scientist overseeing the development of various novel photonics platforms using SiN and worked on active-passive device integration.

==Current Work==
Gopi is the process scientist at the UCSB Nanofab. He is involved in developing new fabrication processes aimed at end product quality improvement, reliability & repeatability. He also does research on novel processes beneficial for the Nanofab users. He provides advice on tool operating and fabrication procedures for optimal tool performance, utilization and improved uptime. Adidtionaly, he executes the “remote fabrication jobs” for the external/internal customers and provides engineering guidance and help design experiments for users on various processing related issues. His work is spread across various dry etching, vacuum deposition, lithography, metrology and packaging tools in the Nanofab.

==Tools==
Gopi is the supervisor for the following tools:

*Gopi currently does not supervise any tools but welcomes processing related queries from lab users.

==External Professional Websites==

*LinkedIn: https://www.linkedin.com/in/ggmeena/
*Google Scholar: https://scholar.google.com/citations?user=cMvXwisAAAAJ

S-Cubed Flexi - Operating Procedure

2024-08-12T15:44:19Z

Gopimeena: Updated SOP (SOP file in Nanofab equipment folder)

{{WIP}}
'''Only staff & designated maintenance users are allowed to write recipes on this tool! '''
Maintaining low particle counts on this tool is extremely important, so users must strictly follow the training procedures. The Underside of your wafers must be clean to avoid contamination!
==='''Procedure:'''===

# Check if the correct user account is selected. Only use the “'''UCSB User'''” account.
## Click “Home” -> “Change User”. User Name: “''UCSB Users''”, Password: “''ucsb''”
# Make sure the system is not running a process. Lot view shows no wafers or batches running.
# Check if PR containers are empty. PR bottles that are available to use are UV6-0.8 in POD#4 and DSK101 in POD#5. If bottles are empty (if you see large bubbles in the supply tube) use the “report tool issue” in signupmonkey. '''''Users are not authorized to change or add any chemistries.'''''
# Check the PR nozzle “bath” (small white tray underneath ''Arm 1''). Make sure it’s not clogged (should have a bit of liquid, but not above the drain hole). If the bath is clogged use the “report tool issue” in signupmonkey. Users are not authorized to clean the nozzle bath or the nozzle tips. To unclog or clean, the robot arms need to be raised up. Or else nozzles can get bumped and change its positions. '''''Only staff is allowed to manually raise the robot arm and clean the nozzle tips & bath.'''''
# Make sure all wafers to be used in the S-Cube have extremely clean backsides. If wafers have dirt, clean the backside following the steps given in the “''How to clean wafer backside before use''” section, before using in the S-Cube.
# Check if hot plates are set to required temperatures for your process. If not, run Temp-change recipes:
## Note only Hot Plate 4 (HP4) temperature can be changed. HP1(135C), HP2(170C) & HP3(170C) temperatures are set and cannot be changed.
## Load dummy wafer ('''''With extremely clean underside''''')
## Run Staff -> HP4-SET-***C recipe. HP4 can be set to 185C, 200C, 210C or 220C.
### Ex: HP4-SET-220C will set hot plate 4 to 2200C
## Check that the hotplate reaches the desired temperature (will overshoot by ~2C - 3C).
## After 5 min wafer bake, make sure the temperature is ±2C before running the actual process.
# Load a test “mechanical” wafer ('''''With extremely clean underside''''') and run a test run of your desired recipe and make sure spin looks ok. This is important for the first UV6-0.8 run after more than 6 hrs of idle time. The 1st mechanical test wafer will likely show radial non uniformity as dried PR is ejected. 2nd test wafer should spin with high uniformity. If the nozzle is clogged, report tool issue in signupmonkey.
# Load your wafers into the left Cassette at Load Port 1 (LP1 labeled with “1”).
# Select the Route/Chain to run (see available recipes table). Use filter [staff] for all the available routes.
# Select wafer slots to run in the LP1 section
# Click [Run] to run your route. Do not open the tool door while process is running.

=== '''Process currently available to lab users:''' ===

* Coat DSK at:
** Varying speeds (1.5 & 5 krpm)
** Varying temperatures (185C, 200C, 210C, 220C)
* Coat UV6-0.8 at:
** Varying speeds (2, 2.5, 3, 3.5, 4, 5 & 6 krpm)
** Single temperature (135C)
* Combination of the above two:
** DSK @ 1.5K or 5K @ 220C + UV6 @ 2K – 6K @ 135C
** DSK @ 1.5K or 5K @ 185C + UV6 @ 2K – 6K @ 135C
* PEB Bake at 135C for 90 sec
* Develop at single spin speed of 300 rpm and varying develop time (10, 15 & 20 sec)
* Combination of PEB bake and develop: Bake @ 135C 90sec + Develop @ 300rpm @ 10 – 20 sec
* '''''DO NOT run developer recipes that are not in "UCSB Users"! There are experimental Develop recipes in the other logins that can damage and bring tool down for extended period of time!'''''

=== '''Troubleshooting:''' ===

# Air bubbles in the PR, EBR-PG or AZ300MIF tubes.
## Use [Report Tool issue] on SignupMonkey to report the problem & get help.
# If PR nozzle bath (small white tray underneath ''Arm 1'') or the nozzle tip is clogged.
## Use [Report Tool issue] on SignupMonkey to report the problem & get help.
## Users are not authorized to manually raise the nozzle tips and clean them.
# Robot arms are not moving after 5min – 10min after starting a route.
## Use [Report Tool issue] on SignupMonkey to report the problem & get help.
## Tool may need full system reset. Users are not allowed to manually initialize the tool.
# If wafer is lost in tool.
## Use [Report Tool issue] on SignupMonkey to report the problem & get help.
## Do not try to retrieve the wafer on your own.
# The Run button cannot be toggled after clicking “no” at “Run Selected Route” prompt in LP1.
## Physically remove the black wafer carrier from LP1 and wait for 2 sec.
## Put the wafer carrier back in its place in LP1.
## LP1 tabs in the Run section will get re-initialized.
# Unknowingly ran a developer recipe not in “UCSB Users” login.
## As a precaution, '''''DO NOT run developer recipes that are not in "UCSB Users" login!'''''
## Notify staff immediately!
# If new or other variations of standard recipe is needed, contact staff.

=== '''How to clean wafer backside before use:''' ===

# Place the wafer upside down in the POLOS spinner using a non-contact chuck.
# Set spin speed to 2000 rpm. Program “backside”.
# Spin wafer, wait until at top speed.
# Squirt “Remover PG” 10 sec, then Acetone 3 seconds, then ISO for 3 sec
# Spin Dry while blowing with N2. Wait ~5 sec before stopping spin.

===Available PR Spin Recipes===
'''Recipes > Lithography >''' [[Lithography Recipes#Automated Coat.2FDevelop System Recipes .28S-Cubed Flexi.29|'''Automated Coater Recipes''']] - See all available spin-coat recipes for this machine. Only Staff may edit/create recipes.

Lithography Recipes

2024-07-11T16:19:59Z

Gopimeena: /* Recipes Table (S-Cubed Flexi) */ Reverted back to previous view

__NOTOC__
{| class="wikitable"
|+
!Table of Contents
|-
|
==='''<big>Photolithography Processes</big>'''===

#'''UV Optical Lithography'''
#*[[#PositivePR |'''Stocked Lithography Chemical + Datasheets''']]
#**''Lists all stocked photolith. chemicals, PRs, strippers, developers, and links to the chemical's application notes/datasheet, which detail the spin curves and nominal processes.''
#*[[#Photolithography_Recipes |'''Photo Lithography Recipe section''']]
#**''Starting recipes (spin, bake, exposure, develop etc.) for all photolith. tools.''
#**''Substrate/surface materials/pattern size can affect process parameters. Users may need to run Focus/Exposure Arrays/Matrix (FEA's/FEM's) with these processes to achieve high-resolution.''
#**[[Contact Alignment Recipes|Contact Aligner Recipes]]
#***[[Contact Alignment Recipes#Suss Aligners .28SUSS MJB-3.29|Suss MJB Aligners]]
#***[[Contact Alignment Recipes#Contact Aligner .28SUSS MA-6.29|Suss MA6]]
#**[[Stepper Recipes|Stepper Recipes]]
#***[[Stepper Recipes#Stepper 1 .28GCA 6300.29|Stepper #1: GCA 6300]] (I-Line)
#***[[Stepper Recipes#Stepper 2 .28AutoStep 200.29|Stepper #2: GCA Autostep 200]] (I-Line)
#***[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Stepper #3: ASML PAS 5500/300]] (DUV)
#**[[Direct-Write Lithography Recipes|Direct-Write Recipes]]
#***[[Direct-Write Lithography Recipes#Maskless Aligner .28Heidelberg MLA150.29|Heidelberg MLA150]]
#***[[Lithography Recipes#E-Beam Lithography Recipes|JEOL JBX-6300FS EBL]]
#***[[Lithography Recipes#FIB Lithography Recipes .28Raith Velion.29|Raith Velion FIB]]
#**[[Lithography Recipes#Automated Coat.2FDevelop System Recipes .28S-Cubed Flexi.29|Automated Coater Recipes (S-Cubed Flexi)]]
#[[Lithography Recipes#General Photolithography Techniques|'''General Photolithography Techniques''']]
#*''Techniques for improving litho. or solving common photolith. problems.''
#'''[[Lithography Recipes#Lift-Off Recipes|Lift-Off Recipes]]'''
#*''Verified Recipes for lift-off using various photolith. tools''
#*''General educational description of this technique and it's limitations/considerations.''
#'''E-beam Lithography'''
#*[[#E-Beam_Lithography_Recipes |E-Beam Lithography Recipes]]
#**''Has links to starting recipes. Substrates and patterns play a large role in process parameters.''
#*[[#EBLPR |EBL Photoresist Datasheets]]
#**''Provided for reference, also showing starting recipes and usage info.''
#'''[[Lithography Recipes#Holography Recipes|Holography]]'''
#*''For 1-D and 2-D gratings with 220nm nominal period, available on substrates up to 1 inch square.''
#*''Recipes for silicon substrates are provided, and have been translated to other substrates by users.''
#*''Datasheets are provided with starting recipes and usage info.''
#'''[[Lithography Recipes#Edge-Bead Removal Techniques|Edge-Bead Removal]]'''
#*''Edge photoresist removal methods needed for clamp-based etchers''
#*''Improves resolution for contact lithography''
|-
|

==='''<big>Photolithography Chemicals/Materials</big>'''===

#'''[[#Underlayers |Underlayers]]'''
#*''These are used beneath resists for both adhesive purposes and to enable bi-layer lift-off profiles for use with photoresist.''
#*''Datasheets are provided.''
#'''[[#AntiReflectionCoatings |Anti-Reflection Coatings]]''':
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Bottom Anti-Reflection Coatings (BARC) are used in the stepper systems, underneath the resists to eliminate substrate reflections that can affect resolution and repeatability for small, near resolution limited, feature sizes.''
#*''Datasheets are provided for reference on use of the materials.''
#'''[[#ContrastEnhancement |Contrast Enhancement Materials (CEM)]]'''
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Used for resolution enhancement. Not for use in contact aligners, typically used on I-Line Steppers.''
#*''Datasheets provided with usage info.''
#'''[[#AdhesionPromoters |Adhesion Promoters]]'''
#*''These are used to improve wetting of photoresists to your substrate.''
#*''Datasheets are provided on use of these materials.''
#'''[[#SpinOnDielectrics |Low-K Spin-on Dielectrics]]'''
#*[[Lithography Recipes#SpinOnDielectrics|Spin-On Dielectrics]]
#**''Datasheets for BCB, Photo-BCB, and SOG (spin-on-glass) for reference on use.''
#*[[#Low-K_Spin-On_Dielectric_Recipes |Low-K Spin-On Dielectric Recipes]]
#**''Recipes for usage of some spin-on dielectrics.''
#'''[[#Developers |Developers and Removers]]'''
#*''Datasheets provided for reference.''
#*''Remover and Photoresist Strippers are used to dissolve PR during lift-off or after etching.''
|}

==General Photolithography Techniques==

====[[Photolithography - Improving Adhesion Photoresist Adhesion|'''HMDS Process for Improving Adhesion''']]====

*''Use these procedures if you are finding poor adhesion PR lifting-off), or for chemicals (like BHF) that attack the PR adhesion interface strongly.''

====[[Photolithography - Manual Edge-Bead Removal Techniques|'''Edge-Bead Removal Techniques''']]====

*''These techniques are required for loading full-wafers into etchers that use top-side clamps, to prevent photoresist from sticking to the clamp (and potentially destroying your wafer).''
*''For contact lithography, this improves the proximity of the mask plate and sample, improving resolution. For some projection systems, such as the [[Maskless Aligner (Heidelberg MLA150)|Maskless Aligner]], EBR can help with autofocus issues.''

====[https://www.microchemicals.com/technical_information/reflow_photoresist.pdf '''Photoresist reflow (MicroChem)''']====

*''To create slanted sidewalls or curved surfaces.''

==Photolithography Recipes==

*'''R''': ''Recipe is available. Clicking this link will take you to the recipe.''
*'''A''': ''Material is available for use, but no recipes are provided.''

''Click the tool title to go to recipes for that tool.''

''Click the photoresist title to get the datasheet, also found in [[Lithography Recipes#Chemicals Stocked .2B Datasheets|Stocked Chemicals + Datasheets]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|-
! colspan="7" height="45" |<div style="font-size: 150%;">Photolithography Recipes</div>

|-
| bgcolor="#EAECF0" |
! colspan="2" align="center" |'''[[Contact Alignment Recipes|<big>Contact Aligner Recipes</big>]]'''
! colspan="3" align="center" |'''[[Stepper Recipes|<big>Stepper Recipes</big>]]'''
! align="center" |[[Direct-Write Lithography Recipes|Direct-Write Litho. Recipes]]
|-
! width="150" bgcolor="#D0E7FF" align="center" |'''Positive Resists'''
{{LithRecipe Table}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[[:File:AXP4000pb-Datasheet.pdf|AZ4110]]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4210]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4330RS]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/a2/Az_p4620_photoresist_data_package.pdf AZ4620]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/8b/OCG825-Positive-Resist-Datasheet.pdf OCG 825-35CS]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-0.9]
|A
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-1.8]
|A
|A
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-3.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-7.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive_Resist_.28MLA150.29}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/be/3600_D%2C_D2v_Spin_Speed_Curve.pdf THMR-IP3600 HP D]
|
|
|A
|A
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/ff/UV210-Positive-Resist-Datasheet.pdf UV210-0.3]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/UV26-Positive-Resist-Datasheet.pdf UV26-2.5]
|
|
|
|
|A
|
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Negative Resists'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/b0/AZ5214-Negative-Resist-Datasheet.pdf AZ5214-EIR]
|{{rl|Contact_Alignment_Recipes|Negative Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2020]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2035]
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |
| bgcolor="EEFFFF" |A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2070]
|A
|A
|A
|A
|
|A
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/82/AZnLOF5510-Negative-Resist-Datasheet.pdf AZnLOF 5510]
|A
|A
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/c/c9/UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf UVN30-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Negative Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/7/78/SU-8-2015-revA.pdf SU-8 2005,2010,2015]
|A
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/2c/SU-8-2075-revA.pdf SU-8 2075]
|A
|A
|A
|A
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |NR9-[//wiki.nanotech.ucsb.edu/w/images/8/8f/NR9-1000PY-revA.pdf 1000],[//wiki.nanotech.ucsb.edu/w/images/7/71/NR9-3000PY-revA.pdf 3000],[//wiki.nanotech.ucsb.edu/w/images/f/f9/NR9-6000PY-revA.pdf 6000]PY
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Anti-Reflection Coatings'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/33/XHRiC-Anti-Reflective-Coating.pdf XHRiC-11]
|
|
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/DUV42P-Anti-Reflective-Coating.pdf DUV42-P]
|
|
|
|
|{{rl|Stepper Recipes|DUV-42P-6}}
|
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101-304]
|
|
|
|
|{{rl|Stepper Recipes|DS-K101-304}}
|
|-
! bgcolor="#D0E7FF" align="center" |
{{LithRecipe Table}}
|}


==Lift-Off Recipes==

*{{fl|Liftoff-Techniques.pdf|Lift-Off Description/Tutorial}}
**How it works, process limits and considerations for designing your process
*[[Lift-Off with I-Line Imaging Resist + LOL2000 Underlayer|I-Line Lift-Off: Bi-Layer Process with LOL2000 Underlayer]]
**''Single Expose/Develop process for simplicity''
**''Up to ~130nm metal thickness & ≥500nm-1000nm gap between metal.''
**''Can use any I-Line litho tool (GCA Stepper, Contact aligner, MLA)''
*{{fl|Bi-LayerContactprocesswithPMGI.pdf|I-Line Lift-Off: Bi-Layer Process with PMGI Underlayer and Contact Aligner}}
**''Multiple processes for Metal thicknesses ~800nm to ~2.5µm''
**''Uses multiple DUV Flood exposure/develop cycles to create undercut.''
**''Can be transferred to other I-Line litho tools (Stepper, MLA etc.)''
*[[Lift-Off with DUV Imaging + PMGI Underlayer|DUV Lift-Off: UV6 Imaging Resist + PMGI Underlayer]]
**''Single-expose/develop process''
**''Up to ~65nm metal thickness & ~350nm gap between metal''
**''Use thicker PMGI for thicker metals''

==[[E-Beam Lithography System (JEOL JBX-6300FS)|E-Beam Lithography Recipes (JEOL JBX-6300FS)]]==

*Under Development.

==[[Focused Ion-Beam Lithography (Raith Velion)|FIB Lithography Recipes (Raith Velion)]]==
''To Be Added''

==[[Automated Coat/Develop System (S-Cubed Flexi)|Automated Coat/Develop System Recipes (S-Cubed Flexi)]]==
Recipes pre-loaded on the S-Cubed Flexi automated coat/bake/develop system. Only staff may write new recipes, contact the tool supervisor for more info.

===Available Variations===

*We have different recipes with varyious UV6 spin speeds - the same spin speed optionss as found on our manual Headway spinners. This allows for PR thickness control. See the linked UV6 datasheets below for thickness vs. rpm spin curves.
*DSK is recommended to be spun at 1.5krpm (~40nm) for best anti-reflection properties. 5krpm (~20nm) recipes are also provided for historical/legacy processes.
*DSK can be baked at either 220C to act as a Dry-etchable BARC (similar to DUV-42P), or at lower temps as a developable BARC (no dry etch required).
*"Chain" recipes (with DSK+UV6 spin/cured in succession) are only available for DSK Baked at 185C & 220C, and all UV6 Spin-speed variations. For the other DSK temps you can use the single-PR "Routes".

===Recipes Table (S-Cubed Flexi)===
{| class="wikitable"
|+''Ask [[Tony Bosch|Staff]] if you need a new recipe.''
|'''''Coating Material'''''
|'''''Route/Chain'''''
|'''''Name''': (User: "UCSB Users")''
|'''''Spin Speed (krpm)'''''
|'''''Bake Temp'''''
|'''''Notes'''''
|-
! colspan="6" |
|-
! colspan="6" |BEFORE LITHOGRAPHY (PR Coat and Bake)
|-
! colspan="6" |
|-
|'''''Hotplate Set'''''
|Route
| colspan="4" |To pre-set the DSK Hotplate temp (HP4).
Note: Only HP4 can be changed. HP1-HP3 remains fixed. HP1=135°C, HP2=170°C & HP3=170°C
|-
|
|
|HP4-SET-220C
|
|220°C
|Will over shoot +-2°C when done.
|-
|
|
|HP4-SET-210C
|
|210°C
|
|-
|
|
|HP4-SET-200C
|
|200°C
|
|-
|
|
|HP4-SET-185C
|
|185°C
|
|-
| colspan="6" |
|-
|'''''[https://wiki.nanotech.ucsb.edu/wiki/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101]'''''
|Route
| colspan="4" |''DSK101 Develop Rate depends on Bake temp - you can use this to control undercut.'' ''See: [[DS-K101-304 Bake Temp. versus Develop Rate|DSK Bake vs. Dev rate]]''
DSK101 spun at 1.5K is equivalent to DUV-42P. See: [[Stepper Recipes#Anti-Reflective Coatings]]

'''Note: All PR coat recipes have EBR backside clean steps included in the recipe.'''
|-
|1.5krpm recipes
|
|COAT-DSK101-304[1.5K]-185C
|1.5krpm
|185°C
|Requires: HP4=185°C,
|-
|
|
|COAT-DSK101-304[1.5K]-200C
|1.5krpm
|200°C
|Requires: HP4=200°C
|-
|
|
|COAT-DSK101-304[1.5K]-210C
|1.5krpm
|210°C
|Requires: HP4=210°C
|-
|
|
|COAT-DSK101-304[1.5K]-220C
|1.5krpm
|220°C
|Requires: HP4=220°C,
|-
| colspan="6" |
|-
|5krpm recipes
|
|COAT-DSK101-304[5K]-185C
|5.0krpm
|185°C
|Requires: HP4=185°C,
|-
|
|
|COAT-DSK101-304[5K]-200C
|5.0krpm
|200°C
|Requires: HP4=200°C
|-
|
|
|COAT-DSK101-304[5K]-210C
|5.0krpm
|210°C
|Requires: HP4=210°C
|-
|
|
|COAT-DSK101-304[5K]-220C
|5.0krpm
|220°C
|Requires: HP4=220°C,
|-
| colspan="6" |
|-
|'''''[https://wiki.nanofab.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]'''''
|Route
|COAT-UV6[2K]-135C
|2.0krpm
|135°C
|Requires: HP1=135°C
|-
|varying spin speed
|
|COAT-UV6[2.5K]-135C
|2.5krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[3K]-135C
|3.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[3.5K]-135C
|3.5krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[4K]-135C
|4.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[5K]-135C
|5.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[6K]-135C
|6.0krpm
|135°C
|Requires: HP1=135°C
|-
| colspan="6" |'''''UV6 Coat with Developable BARC underlayer:'''''
|-
|'''''DS-K101 @ 185°C'''''
'''''+ UV6'''''
|Chain
|COAT-DSK101[1.5K]-185C-UV6[2K]-135C
|DSK: 1.5krpm
UV6: 2.0krpm
|DSK: 185°C
UV6: 135°C
|Requires:
– HP4=185°C

– HP1=135°C

Plan for ~10-15 min per wafer.
|-
|1.5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[1.5K]-185C-UV6[2.5K]-135C
|DSK: 1.5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3K]-135C
|DSK: 1.5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3.5K]-135C
|DSK: 1.5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[4K]-135C
|DSK: 1.5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[5K]-135C
|DSK: 1.5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[6K]-135C
|DSK: 1.5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |
|-
|5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[5K]-185C-UV6[2K]-135C
|DSK: 5krpm
UV6: 2.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[2.5K]-135C
|DSK: 5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3K]-135C
|DSK: 5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3.5K]-135C
|DSK: 5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[4K]-135C
|DSK: 5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[5K]-135C
|DSK: 5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[6K]-135C
|DSK: 5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |'''''UV6 Coat with Dry-Etchable BARC underlayer:'''''
|-
|'''''DS-K101 @ 220°C'''''
'''''+ UV6'''''
|Chain
|COAT-DSK101[1.5K]-220C-UV6[2K]-135C
|DSK: 1.5krpm
UV6: 2.0krpm
|DSK: 220°C
UV6: 135°C
|Requires:
– HP4=220°C

– HP1=135°C

Plan for ~10-15 min per wafer.
|-
|1.5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[1.5K]-220C-UV6[2.5K]-135C
|DSK: 1.5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3K]-135C
|DSK: 1.5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3.5K]-135C
|DSK: 1.5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[4K]-135C
|DSK: 1.5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[5K]-135C
|DSK: 1.5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[6K]-135C
|DSK: 1.5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |
|-
|5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[5K]-220C-UV6[2K]-135C
|DSK: 5krpm
UV6: 2.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[2.5K]-135C
|DSK: 5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3K]-135C
|DSK: 5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3.5K]-135C
|DSK: 5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[4K]-135C
|DSK: 5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[5K]-135C
|DSK: 5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[6K]-135C
|DSK: 5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
! colspan="6" |
|-
! colspan="6" |AFTER LITHOGRAPHY (PEB and Developing)
|-
! colspan="6" |
|-
|'''''PEB Wafer Bake'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) for 90sec and cool for 15sec
|-
|
|
|BAKE-135C-90S
|
|135°C
|Requires: HP1=135°C
|-
| colspan="6" |
|-
|'''''PEB and Developing'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) 90sec, cool 15sec, develop using AZ300MIF and water rinse 60sec

WARNING: DONOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE
|-
|Varying developer time
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-10S
|Developer chuck: 300rpm
|135°C
|Requires: HP1=135°C
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-15S
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-20S
|same as above
|same as above
|same as above
|-
| colspan="6" |
|-
|'''Developing'''
|Route
| colspan="4" |To only develop wafer using AZ300MIF and water rinse 60sec

WARNING: DONOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE
|-
|Varying developer time
|
|DEV[MIF300]-SPIN[300RPM]-10S
|Developer chuck: 300rpm
|135°C
|Requires: HP1=135°C
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-15S
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-20S
|same as above
|same as above
|same as above
|-
|
|
|
|
|
|
|}
==[[Holographic Lith/PL Setup (Custom)|Holography Recipes]]==
''The Holography recipes here use the BARC layer XHRiC-11 & the high-res. I-Line photoresist THMR-IP3600HP-D.''

*{{fl|Holography_Process_for_1D-lines_and_2D-dots_%28ARC-11_%26_THMR-IP3600HP-D%29-updated-4-8-2021.pdf|Standard Holography Process - on SiO2 on Si}}
*{{fl|Holography-Process-Variation-revA.pdf|Holography Process Variations - Set-up Angle - Etching into SiO2 and Si}}
*{{fl|05-SiO2_Nano-structure_Etch.pdf|Etch SiO2 Nano-structure - Changing Side-wall Angle - Etching into Si with a different line-width}}
*{{fl|30-Redicing_Nanowire_Diameter_by_Thermal_Oxidation_and_Vapored_HF_Etch.pdf|Reduce SiO2 Nanowire Diameter - Thermal Oxidation - Vapor HF Etching}}

==Low-K Spin-On Dielectric Recipes==

*{{fl|Lithography-BCB-photo-lowk-dielectric-spinon-4024-40-revA.docx|Photo BCB (4024-40)}}
*{{fl|BCB-cyclotene-3000-revA.pdf|Standard BCB (3022-46)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|SOG (T512B)}}

==Chemicals Stocked + Datasheets==
''The following is a list of the lithography chemicals we stock in the lab, with links to the datasheets for each. The datasheets will often have important processing info such as spin-speed vs. thickness curves, typical process parameters, bake temps/times etc.''
{|
|- valign="top"
| width="400" |
;<div id="PositivePR"><big>Positive Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AXP4000pb-Datasheet.pdf|AZP4000 (AZ4110, AZ4210, AZ4330)}}
*{{Fl|Az_p4620_photoresist_data_package.pdf|AZ P4620}}
*{{fl|OCG825-Positive-Resist-Datasheet.pdf|OCG825}}
*{{fl|SPR220-Positive-Resist-Datasheet.pdf|SPR220 (SPR220-3, SPR220-7)}}
*{{fl|SPR955-Positive-Resist-Datasheet.pdf|SPR955CM (SPR955CM-0.9, SPR955CM-1.8)}}
*THMR-3600HP (Thin I-Line & Holography)
**{{fl|THMR_iP_3500_iP3600.pdf|Evaluation Results: THMR-3600HP}}
**{{fl|3600_D,_D2v_Spin_Speed_Curve.pdf|Spin Curves for THMR-3600HP}}
**{{fl|THMR-iP3600_HP_D_20140801_(B)_GHS_US.pdf|Safety Datasheet for THMR-3600HP}}

'''''DUV-248nm'''''

*{{fl|UV210-Positive-Resist-Datasheet.pdf|UV210-0.3}}
*{{fl|UV6-Positive-Resist-Datasheet.pdf|UV6-0.8}}
*{{fl|UV26-Positive-Resist-Datasheet.pdf|UV26-2.5}}

;<div id="NegativePR"><big>Negative Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AZ5214-Negative-Resist-Datasheet.pdf|AZ5214}}
*{{fl|AZnLOF5510-Negative-Resist-Datasheet.pdf|AZnLOF5510}}
*{{fl|AZnLOF2020-Negative-Resist-Datasheet.pdf|AZnLOF2000 (AZnLOF2020, AZnLOF2035, AZnLOF2070)}}
*{{fl|NR9-1000PY-revA.pdf|Futurrex NR9-1000PY(use AZ300MIF dev)}}
*{{fl|NR9-3000PY-revA.pdf|Futurrex NR9-3000PY(use AZ300MIF dev)}}
*{{fl|NR9-6000PY-revA.pdf|Futurrex NR9-6000PY(use AZ300MIF dev)}}
*{{fl|SU-8-2015-revA.pdf|SU-8-2005,2010, 2015}}
*{{fl|SU-8-2075-revA.pdf|SU-8-2075}}

'''''DUV-248nm'''''

*{{fl|UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf|UVN-30-0.8}}

;<div id="Underlayers"><big>Underlayers</big></div>

*{{fl|PMGI-Underlayer-Datasheet.pdf|PMGI (PMGI SF3,5,8,11,15)}}
*{{fl|LOL2000-Underlayer-Datasheet.pdf|Shipley LOL2000}}

;<div id="EBLPR"><big>E-beam resists</big></div>

*{{fl|PMMA-E-Beam-Resist-Datasheet.pdf|PMMA (PMMA, P(MMA-MAA) copolymer)}}
*{{fl|maN2403-E-Beam-Resist-Datasheet.pdf|maN 2403}}

;<div id="NanoImprinting"><big>Nanoimprinting</big></div>

*{{fl|NX1020-Nanoimprinting-Datasheet.pdf|NX1020}}
*{{fl|MRI-7020-Nanoimprinting-Datasheet.pdf|MRI-7020}}
*{{fl|Mr-UVCur21.pdf|MR-UVCur21}}
*{{fl|OrmoStamp-NIL-Lithography-UV-Soft-RevA.pdf|Ormostamp}}

|
;<div id="ContrastEnhancement"><big>Contrast Enhancement Materials</big></div>

*{{fl|CEM365iS-Contrast-Enhancement-Datasheet.pdf|CEM365iS}}

;<div id="AntiReflectionCoatings"><big>Anti-Reflection Coatings</big></div>

*{{fl|XHRiC-Anti-Reflective-Coating.pdf|XHRiC-11 (i-line)}}
*{{fl|DUV42P-Anti-Reflective-Coating.pdf|DUV42P-6 (DUV) (For AR2 replacement)}}
*{{fl|DS-K101-304-Anti-Reflective-Coating.pdf|DS-K101-304 (DUV developable BARC)}}

;<div id="AdhesionPromoters"><big>Adhesion Promoters</big></div>

*HMDS
*AP3000 BCB Adhesion Promoter
*{{fl|OMNICOAT-revA.pdf|Omnicoat, SU-8 Adhesion Promoter}}
*{{fl|OrmoPrime-NIL-Adhesion-RevA.pdf|Ormoprime08-Ormostsmp Adhesion Promoter}}

;<div id="SpinOnDielectrics"><big>Spin-On Dielectrics</big></div>

''Low-K Spin-On Dielectrics such as Benzocyclobutane and Spin-on Glass''

*{{fl|BCB-cyclotene-3000-revA.pdf|BCB, Cyclotene 3022-46(Not Photosensitive)}}
*{{fl|BCB-cyclotene-4000-revA.pdf|PhotoBCB, Cyclotene 4022-40(Negative Polarity)}}
*{{fl|BCB-adhesion.pdf|BCB Adhesion Notes from Vendor}}
*{{fl|BCB-rework.pdf|BCB rework Notes from Vendor}}
*{{fl|512B-Datasheet-revA.pdf|Spin-on-Glass, Honeywell 512B (Not Photosensitive)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|Honeywell 512B Apps Data}}

;<div id="Developers"><big>Developers</big></div>

*{{fl|AZ400K-Developer-Datasheet.pdf|AZ400K (AZ400K, AZ400K1:4)}}
*{{fl|AZ300MIF-Developer-Datasheet.pdf|AZ300MIF}}
*DS2100 BCB Developer
*SU-8 Developer
*101A Developer (for DUV Flood Exposed PMGI)

;<div id="PRRemovers"><big>Photoresist Removers</big></div>

*[http://www.microchemicals.com/products/remover_stripper/nmp.html AZ NMP]
**''This replaces {{fl|1165-Resist-Remover.pdf|1165}}''
*{{fl|AZ300T-Resist-Remover.pdf|AZ300T}}
*{{fl|RemoverPG-revA.pdf|Remover PG, SU-8 stripper}}
*AZ EBR ("Edge Bead Remover", PGMEA)

|}

[[Category: Processing]]
[[category: Lithography]]
[[category: Recipes]]

Lithography Recipes

2024-07-11T16:18:22Z

Gopimeena: /* Recipes Table (S-Cubed Flexi) */ Cosmetics chages

__NOTOC__
{| class="wikitable"
|+
!Table of Contents
|-
|
==='''<big>Photolithography Processes</big>'''===

#'''UV Optical Lithography'''
#*[[#PositivePR |'''Stocked Lithography Chemical + Datasheets''']]
#**''Lists all stocked photolith. chemicals, PRs, strippers, developers, and links to the chemical's application notes/datasheet, which detail the spin curves and nominal processes.''
#*[[#Photolithography_Recipes |'''Photo Lithography Recipe section''']]
#**''Starting recipes (spin, bake, exposure, develop etc.) for all photolith. tools.''
#**''Substrate/surface materials/pattern size can affect process parameters. Users may need to run Focus/Exposure Arrays/Matrix (FEA's/FEM's) with these processes to achieve high-resolution.''
#**[[Contact Alignment Recipes|Contact Aligner Recipes]]
#***[[Contact Alignment Recipes#Suss Aligners .28SUSS MJB-3.29|Suss MJB Aligners]]
#***[[Contact Alignment Recipes#Contact Aligner .28SUSS MA-6.29|Suss MA6]]
#**[[Stepper Recipes|Stepper Recipes]]
#***[[Stepper Recipes#Stepper 1 .28GCA 6300.29|Stepper #1: GCA 6300]] (I-Line)
#***[[Stepper Recipes#Stepper 2 .28AutoStep 200.29|Stepper #2: GCA Autostep 200]] (I-Line)
#***[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Stepper #3: ASML PAS 5500/300]] (DUV)
#**[[Direct-Write Lithography Recipes|Direct-Write Recipes]]
#***[[Direct-Write Lithography Recipes#Maskless Aligner .28Heidelberg MLA150.29|Heidelberg MLA150]]
#***[[Lithography Recipes#E-Beam Lithography Recipes|JEOL JBX-6300FS EBL]]
#***[[Lithography Recipes#FIB Lithography Recipes .28Raith Velion.29|Raith Velion FIB]]
#**[[Lithography Recipes#Automated Coat.2FDevelop System Recipes .28S-Cubed Flexi.29|Automated Coater Recipes (S-Cubed Flexi)]]
#[[Lithography Recipes#General Photolithography Techniques|'''General Photolithography Techniques''']]
#*''Techniques for improving litho. or solving common photolith. problems.''
#'''[[Lithography Recipes#Lift-Off Recipes|Lift-Off Recipes]]'''
#*''Verified Recipes for lift-off using various photolith. tools''
#*''General educational description of this technique and it's limitations/considerations.''
#'''E-beam Lithography'''
#*[[#E-Beam_Lithography_Recipes |E-Beam Lithography Recipes]]
#**''Has links to starting recipes. Substrates and patterns play a large role in process parameters.''
#*[[#EBLPR |EBL Photoresist Datasheets]]
#**''Provided for reference, also showing starting recipes and usage info.''
#'''[[Lithography Recipes#Holography Recipes|Holography]]'''
#*''For 1-D and 2-D gratings with 220nm nominal period, available on substrates up to 1 inch square.''
#*''Recipes for silicon substrates are provided, and have been translated to other substrates by users.''
#*''Datasheets are provided with starting recipes and usage info.''
#'''[[Lithography Recipes#Edge-Bead Removal Techniques|Edge-Bead Removal]]'''
#*''Edge photoresist removal methods needed for clamp-based etchers''
#*''Improves resolution for contact lithography''
|-
|

==='''<big>Photolithography Chemicals/Materials</big>'''===

#'''[[#Underlayers |Underlayers]]'''
#*''These are used beneath resists for both adhesive purposes and to enable bi-layer lift-off profiles for use with photoresist.''
#*''Datasheets are provided.''
#'''[[#AntiReflectionCoatings |Anti-Reflection Coatings]]''':
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Bottom Anti-Reflection Coatings (BARC) are used in the stepper systems, underneath the resists to eliminate substrate reflections that can affect resolution and repeatability for small, near resolution limited, feature sizes.''
#*''Datasheets are provided for reference on use of the materials.''
#'''[[#ContrastEnhancement |Contrast Enhancement Materials (CEM)]]'''
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Used for resolution enhancement. Not for use in contact aligners, typically used on I-Line Steppers.''
#*''Datasheets provided with usage info.''
#'''[[#AdhesionPromoters |Adhesion Promoters]]'''
#*''These are used to improve wetting of photoresists to your substrate.''
#*''Datasheets are provided on use of these materials.''
#'''[[#SpinOnDielectrics |Low-K Spin-on Dielectrics]]'''
#*[[Lithography Recipes#SpinOnDielectrics|Spin-On Dielectrics]]
#**''Datasheets for BCB, Photo-BCB, and SOG (spin-on-glass) for reference on use.''
#*[[#Low-K_Spin-On_Dielectric_Recipes |Low-K Spin-On Dielectric Recipes]]
#**''Recipes for usage of some spin-on dielectrics.''
#'''[[#Developers |Developers and Removers]]'''
#*''Datasheets provided for reference.''
#*''Remover and Photoresist Strippers are used to dissolve PR during lift-off or after etching.''
|}

==General Photolithography Techniques==

====[[Photolithography - Improving Adhesion Photoresist Adhesion|'''HMDS Process for Improving Adhesion''']]====

*''Use these procedures if you are finding poor adhesion PR lifting-off), or for chemicals (like BHF) that attack the PR adhesion interface strongly.''

====[[Photolithography - Manual Edge-Bead Removal Techniques|'''Edge-Bead Removal Techniques''']]====

*''These techniques are required for loading full-wafers into etchers that use top-side clamps, to prevent photoresist from sticking to the clamp (and potentially destroying your wafer).''
*''For contact lithography, this improves the proximity of the mask plate and sample, improving resolution. For some projection systems, such as the [[Maskless Aligner (Heidelberg MLA150)|Maskless Aligner]], EBR can help with autofocus issues.''

====[https://www.microchemicals.com/technical_information/reflow_photoresist.pdf '''Photoresist reflow (MicroChem)''']====

*''To create slanted sidewalls or curved surfaces.''

==Photolithography Recipes==

*'''R''': ''Recipe is available. Clicking this link will take you to the recipe.''
*'''A''': ''Material is available for use, but no recipes are provided.''

''Click the tool title to go to recipes for that tool.''

''Click the photoresist title to get the datasheet, also found in [[Lithography Recipes#Chemicals Stocked .2B Datasheets|Stocked Chemicals + Datasheets]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|-
! colspan="7" height="45" |<div style="font-size: 150%;">Photolithography Recipes</div>

|-
| bgcolor="#EAECF0" |
! colspan="2" align="center" |'''[[Contact Alignment Recipes|<big>Contact Aligner Recipes</big>]]'''
! colspan="3" align="center" |'''[[Stepper Recipes|<big>Stepper Recipes</big>]]'''
! align="center" |[[Direct-Write Lithography Recipes|Direct-Write Litho. Recipes]]
|-
! width="150" bgcolor="#D0E7FF" align="center" |'''Positive Resists'''
{{LithRecipe Table}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[[:File:AXP4000pb-Datasheet.pdf|AZ4110]]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4210]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4330RS]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/a2/Az_p4620_photoresist_data_package.pdf AZ4620]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/8b/OCG825-Positive-Resist-Datasheet.pdf OCG 825-35CS]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-0.9]
|A
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-1.8]
|A
|A
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-3.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-7.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive_Resist_.28MLA150.29}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/be/3600_D%2C_D2v_Spin_Speed_Curve.pdf THMR-IP3600 HP D]
|
|
|A
|A
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/ff/UV210-Positive-Resist-Datasheet.pdf UV210-0.3]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/UV26-Positive-Resist-Datasheet.pdf UV26-2.5]
|
|
|
|
|A
|
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Negative Resists'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/b0/AZ5214-Negative-Resist-Datasheet.pdf AZ5214-EIR]
|{{rl|Contact_Alignment_Recipes|Negative Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2020]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2035]
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |
| bgcolor="EEFFFF" |A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2070]
|A
|A
|A
|A
|
|A
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/82/AZnLOF5510-Negative-Resist-Datasheet.pdf AZnLOF 5510]
|A
|A
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/c/c9/UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf UVN30-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Negative Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/7/78/SU-8-2015-revA.pdf SU-8 2005,2010,2015]
|A
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/2c/SU-8-2075-revA.pdf SU-8 2075]
|A
|A
|A
|A
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |NR9-[//wiki.nanotech.ucsb.edu/w/images/8/8f/NR9-1000PY-revA.pdf 1000],[//wiki.nanotech.ucsb.edu/w/images/7/71/NR9-3000PY-revA.pdf 3000],[//wiki.nanotech.ucsb.edu/w/images/f/f9/NR9-6000PY-revA.pdf 6000]PY
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Anti-Reflection Coatings'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/33/XHRiC-Anti-Reflective-Coating.pdf XHRiC-11]
|
|
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/DUV42P-Anti-Reflective-Coating.pdf DUV42-P]
|
|
|
|
|{{rl|Stepper Recipes|DUV-42P-6}}
|
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101-304]
|
|
|
|
|{{rl|Stepper Recipes|DS-K101-304}}
|
|-
! bgcolor="#D0E7FF" align="center" |
{{LithRecipe Table}}
|}


==Lift-Off Recipes==

*{{fl|Liftoff-Techniques.pdf|Lift-Off Description/Tutorial}}
**How it works, process limits and considerations for designing your process
*[[Lift-Off with I-Line Imaging Resist + LOL2000 Underlayer|I-Line Lift-Off: Bi-Layer Process with LOL2000 Underlayer]]
**''Single Expose/Develop process for simplicity''
**''Up to ~130nm metal thickness & ≥500nm-1000nm gap between metal.''
**''Can use any I-Line litho tool (GCA Stepper, Contact aligner, MLA)''
*{{fl|Bi-LayerContactprocesswithPMGI.pdf|I-Line Lift-Off: Bi-Layer Process with PMGI Underlayer and Contact Aligner}}
**''Multiple processes for Metal thicknesses ~800nm to ~2.5µm''
**''Uses multiple DUV Flood exposure/develop cycles to create undercut.''
**''Can be transferred to other I-Line litho tools (Stepper, MLA etc.)''
*[[Lift-Off with DUV Imaging + PMGI Underlayer|DUV Lift-Off: UV6 Imaging Resist + PMGI Underlayer]]
**''Single-expose/develop process''
**''Up to ~65nm metal thickness & ~350nm gap between metal''
**''Use thicker PMGI for thicker metals''

==[[E-Beam Lithography System (JEOL JBX-6300FS)|E-Beam Lithography Recipes (JEOL JBX-6300FS)]]==

*Under Development.

==[[Focused Ion-Beam Lithography (Raith Velion)|FIB Lithography Recipes (Raith Velion)]]==
''To Be Added''

==[[Automated Coat/Develop System (S-Cubed Flexi)|Automated Coat/Develop System Recipes (S-Cubed Flexi)]]==
Recipes pre-loaded on the S-Cubed Flexi automated coat/bake/develop system. Only staff may write new recipes, contact the tool supervisor for more info.

===Available Variations===

*We have different recipes with varyious UV6 spin speeds - the same spin speed optionss as found on our manual Headway spinners. This allows for PR thickness control. See the linked UV6 datasheets below for thickness vs. rpm spin curves.
*DSK is recommended to be spun at 1.5krpm (~40nm) for best anti-reflection properties. 5krpm (~20nm) recipes are also provided for historical/legacy processes.
*DSK can be baked at either 220C to act as a Dry-etchable BARC (similar to DUV-42P), or at lower temps as a developable BARC (no dry etch required).
*"Chain" recipes (with DSK+UV6 spin/cured in succession) are only available for DSK Baked at 185C & 220C, and all UV6 Spin-speed variations. For the other DSK temps you can use the single-PR "Routes".

===Recipes Table (S-Cubed Flexi)===
{| class="wikitable"
|+''Ask [[Tony Bosch|Staff]] if you need a new recipe.''
|'''''Coating Material'''''
|'''''Route/Chain'''''
|'''''Name''': (User: "UCSB Users")''
|'''''Spin Speed (krpm)'''''
|'''''Bake Temp'''''
|'''''Notes'''''
|-
! colspan="6" |
|-
! colspan="6" |BEFORE LITHOGRAPHY (PR Coat and Bake)
|-
! colspan="6" |
|-
|'''''Hotplate Set'''''
|Route
| colspan="4" |To pre-set the DSK Hotplate temp (HP4).
Note: Only HP4 can be changed. HP1-HP3 remains fixed. HP1=135°C, HP2=170°C & HP3=170°C
|-
|
|
|HP4-SET-220C
|
|220°C
|Will over shoot +-2°C when done.
|-
|
|
|HP4-SET-210C
|
|210°C
|
|-
|
|
|HP4-SET-200C
|
|200°C
|
|-
|
|
|HP4-SET-185C
|
|185°C
|
|-
! colspan="6" |
|-
|'''''[https://wiki.nanotech.ucsb.edu/wiki/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101]'''''
|Route
| colspan="4" |''DSK101 Develop Rate depends on Bake temp - you can use this to control undercut.'' ''See: [[DS-K101-304 Bake Temp. versus Develop Rate|DSK Bake vs. Dev rate]]''
DSK101 spun at 1.5K is equivalent to DUV-42P. See: [[Stepper Recipes#Anti-Reflective Coatings]]

'''Note: All PR coat recipes have EBR backside clean steps included in the recipe.'''
|-
|1.5krpm recipes
|
|COAT-DSK101-304[1.5K]-185C
|1.5krpm
|185°C
|Requires: HP4=185°C,
|-
|
|
|COAT-DSK101-304[1.5K]-200C
|1.5krpm
|200°C
|Requires: HP4=200°C
|-
|
|
|COAT-DSK101-304[1.5K]-210C
|1.5krpm
|210°C
|Requires: HP4=210°C
|-
|
|
|COAT-DSK101-304[1.5K]-220C
|1.5krpm
|220°C
|Requires: HP4=220°C,
|-
! colspan="6" |
|-
|5krpm recipes
|
|COAT-DSK101-304[5K]-185C
|5.0krpm
|185°C
|Requires: HP4=185°C,
|-
|
|
|COAT-DSK101-304[5K]-200C
|5.0krpm
|200°C
|Requires: HP4=200°C
|-
|
|
|COAT-DSK101-304[5K]-210C
|5.0krpm
|210°C
|Requires: HP4=210°C
|-
|
|
|COAT-DSK101-304[5K]-220C
|5.0krpm
|220°C
|Requires: HP4=220°C,
|-
! colspan="6" |
|-
|'''''[https://wiki.nanofab.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]'''''
|Route
|COAT-UV6[2K]-135C
|2.0krpm
|135°C
|Requires: HP1=135°C
|-
|varying spin speed
|
|COAT-UV6[2.5K]-135C
|2.5krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[3K]-135C
|3.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[3.5K]-135C
|3.5krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[4K]-135C
|4.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[5K]-135C
|5.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[6K]-135C
|6.0krpm
|135°C
|Requires: HP1=135°C
|-
| colspan="6" |'''''UV6 Coat with Developable BARC underlayer:'''''
|-
|'''''DS-K101 @ 185°C'''''
'''''+ UV6'''''
|Chain
|COAT-DSK101[1.5K]-185C-UV6[2K]-135C
|DSK: 1.5krpm
UV6: 2.0krpm
|DSK: 185°C
UV6: 135°C
|Requires:
– HP4=185°C

– HP1=135°C

Plan for ~10-15 min per wafer.
|-
|1.5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[1.5K]-185C-UV6[2.5K]-135C
|DSK: 1.5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3K]-135C
|DSK: 1.5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3.5K]-135C
|DSK: 1.5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[4K]-135C
|DSK: 1.5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[5K]-135C
|DSK: 1.5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[6K]-135C
|DSK: 1.5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
! colspan="6" |
|-
|5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[5K]-185C-UV6[2K]-135C
|DSK: 5krpm
UV6: 2.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[2.5K]-135C
|DSK: 5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3K]-135C
|DSK: 5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3.5K]-135C
|DSK: 5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[4K]-135C
|DSK: 5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[5K]-135C
|DSK: 5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[6K]-135C
|DSK: 5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |'''''UV6 Coat with Dry-Etchable BARC underlayer:'''''
|-
|'''''DS-K101 @ 220°C'''''
'''''+ UV6'''''
|Chain
|COAT-DSK101[1.5K]-220C-UV6[2K]-135C
|DSK: 1.5krpm
UV6: 2.0krpm
|DSK: 220°C
UV6: 135°C
|Requires:
– HP4=220°C

– HP1=135°C

Plan for ~10-15 min per wafer.
|-
|1.5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[1.5K]-220C-UV6[2.5K]-135C
|DSK: 1.5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3K]-135C
|DSK: 1.5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3.5K]-135C
|DSK: 1.5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[4K]-135C
|DSK: 1.5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[5K]-135C
|DSK: 1.5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[6K]-135C
|DSK: 1.5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
! colspan="6" |
|-
|5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[5K]-220C-UV6[2K]-135C
|DSK: 5krpm
UV6: 2.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[2.5K]-135C
|DSK: 5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3K]-135C
|DSK: 5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3.5K]-135C
|DSK: 5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[4K]-135C
|DSK: 5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[5K]-135C
|DSK: 5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[6K]-135C
|DSK: 5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
! colspan="6" |
|-
! colspan="6" |AFTER LITHOGRAPHY (PEB and Developing)
|-
! colspan="6" |
|-
|'''''PEB Wafer Bake'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) for 90sec and cool for 15sec
|-
|
|
|BAKE-135C-90S
|
|135°C
|Requires: HP1=135°C
|-
| colspan="6" |
|-
|'''''PEB and Developing'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) 90sec, cool 15sec, develop using AZ300MIF and water rinse 60sec

WARNING: DONOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE
|-
|Varying developer time
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-10S
|Developer chuck: 300rpm
|135°C
|Requires: HP1=135°C
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-15S
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-20S
|same as above
|same as above
|same as above
|-
| colspan="6" |
|-
|'''Developing'''
|Route
| colspan="4" |To only develop wafer using AZ300MIF and water rinse 60sec

WARNING: DONOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE
|-
|Varying developer time
|
|DEV[MIF300]-SPIN[300RPM]-10S
|Developer chuck: 300rpm
|135°C
|Requires: HP1=135°C
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-15S
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-20S
|same as above
|same as above
|same as above
|-
|
|
|
|
|
|
|}
==[[Holographic Lith/PL Setup (Custom)|Holography Recipes]]==
''The Holography recipes here use the BARC layer XHRiC-11 & the high-res. I-Line photoresist THMR-IP3600HP-D.''

*{{fl|Holography_Process_for_1D-lines_and_2D-dots_%28ARC-11_%26_THMR-IP3600HP-D%29-updated-4-8-2021.pdf|Standard Holography Process - on SiO2 on Si}}
*{{fl|Holography-Process-Variation-revA.pdf|Holography Process Variations - Set-up Angle - Etching into SiO2 and Si}}
*{{fl|05-SiO2_Nano-structure_Etch.pdf|Etch SiO2 Nano-structure - Changing Side-wall Angle - Etching into Si with a different line-width}}
*{{fl|30-Redicing_Nanowire_Diameter_by_Thermal_Oxidation_and_Vapored_HF_Etch.pdf|Reduce SiO2 Nanowire Diameter - Thermal Oxidation - Vapor HF Etching}}

==Low-K Spin-On Dielectric Recipes==

*{{fl|Lithography-BCB-photo-lowk-dielectric-spinon-4024-40-revA.docx|Photo BCB (4024-40)}}
*{{fl|BCB-cyclotene-3000-revA.pdf|Standard BCB (3022-46)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|SOG (T512B)}}

==Chemicals Stocked + Datasheets==
''The following is a list of the lithography chemicals we stock in the lab, with links to the datasheets for each. The datasheets will often have important processing info such as spin-speed vs. thickness curves, typical process parameters, bake temps/times etc.''
{|
|- valign="top"
| width="400" |
;<div id="PositivePR"><big>Positive Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AXP4000pb-Datasheet.pdf|AZP4000 (AZ4110, AZ4210, AZ4330)}}
*{{Fl|Az_p4620_photoresist_data_package.pdf|AZ P4620}}
*{{fl|OCG825-Positive-Resist-Datasheet.pdf|OCG825}}
*{{fl|SPR220-Positive-Resist-Datasheet.pdf|SPR220 (SPR220-3, SPR220-7)}}
*{{fl|SPR955-Positive-Resist-Datasheet.pdf|SPR955CM (SPR955CM-0.9, SPR955CM-1.8)}}
*THMR-3600HP (Thin I-Line & Holography)
**{{fl|THMR_iP_3500_iP3600.pdf|Evaluation Results: THMR-3600HP}}
**{{fl|3600_D,_D2v_Spin_Speed_Curve.pdf|Spin Curves for THMR-3600HP}}
**{{fl|THMR-iP3600_HP_D_20140801_(B)_GHS_US.pdf|Safety Datasheet for THMR-3600HP}}

'''''DUV-248nm'''''

*{{fl|UV210-Positive-Resist-Datasheet.pdf|UV210-0.3}}
*{{fl|UV6-Positive-Resist-Datasheet.pdf|UV6-0.8}}
*{{fl|UV26-Positive-Resist-Datasheet.pdf|UV26-2.5}}

;<div id="NegativePR"><big>Negative Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AZ5214-Negative-Resist-Datasheet.pdf|AZ5214}}
*{{fl|AZnLOF5510-Negative-Resist-Datasheet.pdf|AZnLOF5510}}
*{{fl|AZnLOF2020-Negative-Resist-Datasheet.pdf|AZnLOF2000 (AZnLOF2020, AZnLOF2035, AZnLOF2070)}}
*{{fl|NR9-1000PY-revA.pdf|Futurrex NR9-1000PY(use AZ300MIF dev)}}
*{{fl|NR9-3000PY-revA.pdf|Futurrex NR9-3000PY(use AZ300MIF dev)}}
*{{fl|NR9-6000PY-revA.pdf|Futurrex NR9-6000PY(use AZ300MIF dev)}}
*{{fl|SU-8-2015-revA.pdf|SU-8-2005,2010, 2015}}
*{{fl|SU-8-2075-revA.pdf|SU-8-2075}}

'''''DUV-248nm'''''

*{{fl|UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf|UVN-30-0.8}}

;<div id="Underlayers"><big>Underlayers</big></div>

*{{fl|PMGI-Underlayer-Datasheet.pdf|PMGI (PMGI SF3,5,8,11,15)}}
*{{fl|LOL2000-Underlayer-Datasheet.pdf|Shipley LOL2000}}

;<div id="EBLPR"><big>E-beam resists</big></div>

*{{fl|PMMA-E-Beam-Resist-Datasheet.pdf|PMMA (PMMA, P(MMA-MAA) copolymer)}}
*{{fl|maN2403-E-Beam-Resist-Datasheet.pdf|maN 2403}}

;<div id="NanoImprinting"><big>Nanoimprinting</big></div>

*{{fl|NX1020-Nanoimprinting-Datasheet.pdf|NX1020}}
*{{fl|MRI-7020-Nanoimprinting-Datasheet.pdf|MRI-7020}}
*{{fl|Mr-UVCur21.pdf|MR-UVCur21}}
*{{fl|OrmoStamp-NIL-Lithography-UV-Soft-RevA.pdf|Ormostamp}}

|
;<div id="ContrastEnhancement"><big>Contrast Enhancement Materials</big></div>

*{{fl|CEM365iS-Contrast-Enhancement-Datasheet.pdf|CEM365iS}}

;<div id="AntiReflectionCoatings"><big>Anti-Reflection Coatings</big></div>

*{{fl|XHRiC-Anti-Reflective-Coating.pdf|XHRiC-11 (i-line)}}
*{{fl|DUV42P-Anti-Reflective-Coating.pdf|DUV42P-6 (DUV) (For AR2 replacement)}}
*{{fl|DS-K101-304-Anti-Reflective-Coating.pdf|DS-K101-304 (DUV developable BARC)}}

;<div id="AdhesionPromoters"><big>Adhesion Promoters</big></div>

*HMDS
*AP3000 BCB Adhesion Promoter
*{{fl|OMNICOAT-revA.pdf|Omnicoat, SU-8 Adhesion Promoter}}
*{{fl|OrmoPrime-NIL-Adhesion-RevA.pdf|Ormoprime08-Ormostsmp Adhesion Promoter}}

;<div id="SpinOnDielectrics"><big>Spin-On Dielectrics</big></div>

''Low-K Spin-On Dielectrics such as Benzocyclobutane and Spin-on Glass''

*{{fl|BCB-cyclotene-3000-revA.pdf|BCB, Cyclotene 3022-46(Not Photosensitive)}}
*{{fl|BCB-cyclotene-4000-revA.pdf|PhotoBCB, Cyclotene 4022-40(Negative Polarity)}}
*{{fl|BCB-adhesion.pdf|BCB Adhesion Notes from Vendor}}
*{{fl|BCB-rework.pdf|BCB rework Notes from Vendor}}
*{{fl|512B-Datasheet-revA.pdf|Spin-on-Glass, Honeywell 512B (Not Photosensitive)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|Honeywell 512B Apps Data}}

;<div id="Developers"><big>Developers</big></div>

*{{fl|AZ400K-Developer-Datasheet.pdf|AZ400K (AZ400K, AZ400K1:4)}}
*{{fl|AZ300MIF-Developer-Datasheet.pdf|AZ300MIF}}
*DS2100 BCB Developer
*SU-8 Developer
*101A Developer (for DUV Flood Exposed PMGI)

;<div id="PRRemovers"><big>Photoresist Removers</big></div>

*[http://www.microchemicals.com/products/remover_stripper/nmp.html AZ NMP]
**''This replaces {{fl|1165-Resist-Remover.pdf|1165}}''
*{{fl|AZ300T-Resist-Remover.pdf|AZ300T}}
*{{fl|RemoverPG-revA.pdf|Remover PG, SU-8 stripper}}
*AZ EBR ("Edge Bead Remover", PGMEA)

|}

[[Category: Processing]]
[[category: Lithography]]
[[category: Recipes]]

Lithography Recipes

2024-07-11T16:14:30Z

Gopimeena: /* Recipes Table (S-Cubed Flexi) */

__NOTOC__
{| class="wikitable"
|+
!Table of Contents
|-
|
==='''<big>Photolithography Processes</big>'''===

#'''UV Optical Lithography'''
#*[[#PositivePR |'''Stocked Lithography Chemical + Datasheets''']]
#**''Lists all stocked photolith. chemicals, PRs, strippers, developers, and links to the chemical's application notes/datasheet, which detail the spin curves and nominal processes.''
#*[[#Photolithography_Recipes |'''Photo Lithography Recipe section''']]
#**''Starting recipes (spin, bake, exposure, develop etc.) for all photolith. tools.''
#**''Substrate/surface materials/pattern size can affect process parameters. Users may need to run Focus/Exposure Arrays/Matrix (FEA's/FEM's) with these processes to achieve high-resolution.''
#**[[Contact Alignment Recipes|Contact Aligner Recipes]]
#***[[Contact Alignment Recipes#Suss Aligners .28SUSS MJB-3.29|Suss MJB Aligners]]
#***[[Contact Alignment Recipes#Contact Aligner .28SUSS MA-6.29|Suss MA6]]
#**[[Stepper Recipes|Stepper Recipes]]
#***[[Stepper Recipes#Stepper 1 .28GCA 6300.29|Stepper #1: GCA 6300]] (I-Line)
#***[[Stepper Recipes#Stepper 2 .28AutoStep 200.29|Stepper #2: GCA Autostep 200]] (I-Line)
#***[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Stepper #3: ASML PAS 5500/300]] (DUV)
#**[[Direct-Write Lithography Recipes|Direct-Write Recipes]]
#***[[Direct-Write Lithography Recipes#Maskless Aligner .28Heidelberg MLA150.29|Heidelberg MLA150]]
#***[[Lithography Recipes#E-Beam Lithography Recipes|JEOL JBX-6300FS EBL]]
#***[[Lithography Recipes#FIB Lithography Recipes .28Raith Velion.29|Raith Velion FIB]]
#**[[Lithography Recipes#Automated Coat.2FDevelop System Recipes .28S-Cubed Flexi.29|Automated Coater Recipes (S-Cubed Flexi)]]
#[[Lithography Recipes#General Photolithography Techniques|'''General Photolithography Techniques''']]
#*''Techniques for improving litho. or solving common photolith. problems.''
#'''[[Lithography Recipes#Lift-Off Recipes|Lift-Off Recipes]]'''
#*''Verified Recipes for lift-off using various photolith. tools''
#*''General educational description of this technique and it's limitations/considerations.''
#'''E-beam Lithography'''
#*[[#E-Beam_Lithography_Recipes |E-Beam Lithography Recipes]]
#**''Has links to starting recipes. Substrates and patterns play a large role in process parameters.''
#*[[#EBLPR |EBL Photoresist Datasheets]]
#**''Provided for reference, also showing starting recipes and usage info.''
#'''[[Lithography Recipes#Holography Recipes|Holography]]'''
#*''For 1-D and 2-D gratings with 220nm nominal period, available on substrates up to 1 inch square.''
#*''Recipes for silicon substrates are provided, and have been translated to other substrates by users.''
#*''Datasheets are provided with starting recipes and usage info.''
#'''[[Lithography Recipes#Edge-Bead Removal Techniques|Edge-Bead Removal]]'''
#*''Edge photoresist removal methods needed for clamp-based etchers''
#*''Improves resolution for contact lithography''
|-
|

==='''<big>Photolithography Chemicals/Materials</big>'''===

#'''[[#Underlayers |Underlayers]]'''
#*''These are used beneath resists for both adhesive purposes and to enable bi-layer lift-off profiles for use with photoresist.''
#*''Datasheets are provided.''
#'''[[#AntiReflectionCoatings |Anti-Reflection Coatings]]''':
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Bottom Anti-Reflection Coatings (BARC) are used in the stepper systems, underneath the resists to eliminate substrate reflections that can affect resolution and repeatability for small, near resolution limited, feature sizes.''
#*''Datasheets are provided for reference on use of the materials.''
#'''[[#ContrastEnhancement |Contrast Enhancement Materials (CEM)]]'''
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Used for resolution enhancement. Not for use in contact aligners, typically used on I-Line Steppers.''
#*''Datasheets provided with usage info.''
#'''[[#AdhesionPromoters |Adhesion Promoters]]'''
#*''These are used to improve wetting of photoresists to your substrate.''
#*''Datasheets are provided on use of these materials.''
#'''[[#SpinOnDielectrics |Low-K Spin-on Dielectrics]]'''
#*[[Lithography Recipes#SpinOnDielectrics|Spin-On Dielectrics]]
#**''Datasheets for BCB, Photo-BCB, and SOG (spin-on-glass) for reference on use.''
#*[[#Low-K_Spin-On_Dielectric_Recipes |Low-K Spin-On Dielectric Recipes]]
#**''Recipes for usage of some spin-on dielectrics.''
#'''[[#Developers |Developers and Removers]]'''
#*''Datasheets provided for reference.''
#*''Remover and Photoresist Strippers are used to dissolve PR during lift-off or after etching.''
|}

==General Photolithography Techniques==

====[[Photolithography - Improving Adhesion Photoresist Adhesion|'''HMDS Process for Improving Adhesion''']]====

*''Use these procedures if you are finding poor adhesion PR lifting-off), or for chemicals (like BHF) that attack the PR adhesion interface strongly.''

====[[Photolithography - Manual Edge-Bead Removal Techniques|'''Edge-Bead Removal Techniques''']]====

*''These techniques are required for loading full-wafers into etchers that use top-side clamps, to prevent photoresist from sticking to the clamp (and potentially destroying your wafer).''
*''For contact lithography, this improves the proximity of the mask plate and sample, improving resolution. For some projection systems, such as the [[Maskless Aligner (Heidelberg MLA150)|Maskless Aligner]], EBR can help with autofocus issues.''

====[https://www.microchemicals.com/technical_information/reflow_photoresist.pdf '''Photoresist reflow (MicroChem)''']====

*''To create slanted sidewalls or curved surfaces.''

==Photolithography Recipes==

*'''R''': ''Recipe is available. Clicking this link will take you to the recipe.''
*'''A''': ''Material is available for use, but no recipes are provided.''

''Click the tool title to go to recipes for that tool.''

''Click the photoresist title to get the datasheet, also found in [[Lithography Recipes#Chemicals Stocked .2B Datasheets|Stocked Chemicals + Datasheets]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|-
! colspan="7" height="45" |<div style="font-size: 150%;">Photolithography Recipes</div>

|-
| bgcolor="#EAECF0" |
! colspan="2" align="center" |'''[[Contact Alignment Recipes|<big>Contact Aligner Recipes</big>]]'''
! colspan="3" align="center" |'''[[Stepper Recipes|<big>Stepper Recipes</big>]]'''
! align="center" |[[Direct-Write Lithography Recipes|Direct-Write Litho. Recipes]]
|-
! width="150" bgcolor="#D0E7FF" align="center" |'''Positive Resists'''
{{LithRecipe Table}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[[:File:AXP4000pb-Datasheet.pdf|AZ4110]]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4210]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4330RS]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/a2/Az_p4620_photoresist_data_package.pdf AZ4620]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/8b/OCG825-Positive-Resist-Datasheet.pdf OCG 825-35CS]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-0.9]
|A
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-1.8]
|A
|A
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-3.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-7.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive_Resist_.28MLA150.29}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/be/3600_D%2C_D2v_Spin_Speed_Curve.pdf THMR-IP3600 HP D]
|
|
|A
|A
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/ff/UV210-Positive-Resist-Datasheet.pdf UV210-0.3]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/UV26-Positive-Resist-Datasheet.pdf UV26-2.5]
|
|
|
|
|A
|
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Negative Resists'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/b0/AZ5214-Negative-Resist-Datasheet.pdf AZ5214-EIR]
|{{rl|Contact_Alignment_Recipes|Negative Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2020]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2035]
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |
| bgcolor="EEFFFF" |A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2070]
|A
|A
|A
|A
|
|A
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/82/AZnLOF5510-Negative-Resist-Datasheet.pdf AZnLOF 5510]
|A
|A
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/c/c9/UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf UVN30-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Negative Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/7/78/SU-8-2015-revA.pdf SU-8 2005,2010,2015]
|A
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/2c/SU-8-2075-revA.pdf SU-8 2075]
|A
|A
|A
|A
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |NR9-[//wiki.nanotech.ucsb.edu/w/images/8/8f/NR9-1000PY-revA.pdf 1000],[//wiki.nanotech.ucsb.edu/w/images/7/71/NR9-3000PY-revA.pdf 3000],[//wiki.nanotech.ucsb.edu/w/images/f/f9/NR9-6000PY-revA.pdf 6000]PY
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Anti-Reflection Coatings'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/33/XHRiC-Anti-Reflective-Coating.pdf XHRiC-11]
|
|
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/DUV42P-Anti-Reflective-Coating.pdf DUV42-P]
|
|
|
|
|{{rl|Stepper Recipes|DUV-42P-6}}
|
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101-304]
|
|
|
|
|{{rl|Stepper Recipes|DS-K101-304}}
|
|-
! bgcolor="#D0E7FF" align="center" |
{{LithRecipe Table}}
|}


==Lift-Off Recipes==

*{{fl|Liftoff-Techniques.pdf|Lift-Off Description/Tutorial}}
**How it works, process limits and considerations for designing your process
*[[Lift-Off with I-Line Imaging Resist + LOL2000 Underlayer|I-Line Lift-Off: Bi-Layer Process with LOL2000 Underlayer]]
**''Single Expose/Develop process for simplicity''
**''Up to ~130nm metal thickness & ≥500nm-1000nm gap between metal.''
**''Can use any I-Line litho tool (GCA Stepper, Contact aligner, MLA)''
*{{fl|Bi-LayerContactprocesswithPMGI.pdf|I-Line Lift-Off: Bi-Layer Process with PMGI Underlayer and Contact Aligner}}
**''Multiple processes for Metal thicknesses ~800nm to ~2.5µm''
**''Uses multiple DUV Flood exposure/develop cycles to create undercut.''
**''Can be transferred to other I-Line litho tools (Stepper, MLA etc.)''
*[[Lift-Off with DUV Imaging + PMGI Underlayer|DUV Lift-Off: UV6 Imaging Resist + PMGI Underlayer]]
**''Single-expose/develop process''
**''Up to ~65nm metal thickness & ~350nm gap between metal''
**''Use thicker PMGI for thicker metals''

==[[E-Beam Lithography System (JEOL JBX-6300FS)|E-Beam Lithography Recipes (JEOL JBX-6300FS)]]==

*Under Development.

==[[Focused Ion-Beam Lithography (Raith Velion)|FIB Lithography Recipes (Raith Velion)]]==
''To Be Added''

==[[Automated Coat/Develop System (S-Cubed Flexi)|Automated Coat/Develop System Recipes (S-Cubed Flexi)]]==
Recipes pre-loaded on the S-Cubed Flexi automated coat/bake/develop system. Only staff may write new recipes, contact the tool supervisor for more info.

===Available Variations===

*We have different recipes with varyious UV6 spin speeds - the same spin speed optionss as found on our manual Headway spinners. This allows for PR thickness control. See the linked UV6 datasheets below for thickness vs. rpm spin curves.
*DSK is recommended to be spun at 1.5krpm (~40nm) for best anti-reflection properties. 5krpm (~20nm) recipes are also provided for historical/legacy processes.
*DSK can be baked at either 220C to act as a Dry-etchable BARC (similar to DUV-42P), or at lower temps as a developable BARC (no dry etch required).
*"Chain" recipes (with DSK+UV6 spin/cured in succession) are only available for DSK Baked at 185C & 220C, and all UV6 Spin-speed variations. For the other DSK temps you can use the single-PR "Routes".

===Recipes Table (S-Cubed Flexi)===
{| class="wikitable"
|+''Ask [[Tony Bosch|Staff]] if you need a new recipe.''
|'''''Coating Material'''''
|'''''Route/Chain'''''
|'''''Name''': (User: "UCSB Users")''
|'''''Spin Speed (krpm)'''''
|'''''Bake Temp'''''
|'''''Notes'''''
|-
! colspan="6" |
|-
! colspan="6" |BEFORE LITHOGRAPHY (PR Coat and Bake)
|-
! colspan="6" |
|-
|'''''Hotplate Set'''''
|Route
| colspan="4" |To pre-set the DSK Hotplate temp (HP4).
Note: Only HP4 can be changed. HP1-HP3 remains fixed. HP1=135°C, HP2=170°C & HP3=170°C
|-
|
|
|HP4-SET-220C
|
|220°C
|''Will over shoot +-2°C when done.''
|-
|
|
|HP4-SET-210C
|
|210°C
|
|-
|
|
|HP4-SET-200C
|
|200°C
|
|-
|
|
|HP4-SET-185C
|
|185°C
|
|-
| colspan="6" |
|-
|'''''[https://wiki.nanotech.ucsb.edu/wiki/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101]'''''
|Route
| colspan="4" |''DSK101 Develop Rate depends on Bake temp - you can use this to control undercut.'' ''See: [[DS-K101-304 Bake Temp. versus Develop Rate|DSK Bake vs. Dev rate]]''
DSK101 spun at 1.5K is equivalent to DUV-42P. See: [[Stepper Recipes#Anti-Reflective Coatings]]

'''Note: All PR coat recipes have EBR backside clean steps included in the recipe.'''
|-
|1.5krpm recipes
|
|COAT-DSK101-304[1.5K]-185C
|1.5krpm
|185°C
|Requires: HP4=185°C,
|-
|
|
|COAT-DSK101-304[1.5K]-200C
|1.5krpm
|200°C
|Requires: HP4=200°C
|-
|
|
|COAT-DSK101-304[1.5K]-210C
|1.5krpm
|210°C
|Requires: HP4=210°C
|-
|
|
|COAT-DSK101-304[1.5K]-220C
|1.5krpm
|220°C
|Requires: HP4=220°C,
|-
| colspan="6" |
|-
|5krpm recipes
|
|COAT-DSK101-304[5K]-185C
|5.0krpm
|185°C
|Requires: HP4=185°C,
|-
|
|
|COAT-DSK101-304[5K]-200C
|5.0krpm
|200°C
|Requires: HP4=200°C
|-
|
|
|COAT-DSK101-304[5K]-210C
|5.0krpm
|210°C
|Requires: HP4=210°C
|-
|
|
|COAT-DSK101-304[5K]-220C
|5.0krpm
|220°C
|Requires: HP4=220°C,
|-
| colspan="6" |
|-
|'''''[https://wiki.nanofab.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]'''''
|Route
|COAT-UV6[2K]-135C
|2.0krpm
|135°C
|Requires: HP1=135°C
|-
|varying spin speed
|
|COAT-UV6[2.5K]-135C
|2.5krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[3K]-135C
|3.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[3.5K]-135C
|3.5krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[4K]-135C
|4.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[5K]-135C
|5.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[6K]-135C
|6.0krpm
|135°C
|Requires: HP1=135°C
|-
| colspan="6" |'''''UV6 Coat with Developable BARC underlayer:'''''
|-
|'''''DS-K101 @ 185°C'''''
'''''+ UV6'''''
|Chain
|COAT-DSK101[1.5K]-185C-UV6[2K]-135C
|DSK: 1.5krpm
UV6: 2.0krpm
|DSK: 185°C
UV6: 135°C
|Requires:
– HP4=185°C

– HP1=135°C

Plan for ~10-15 min per wafer.
|-
|1.5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[1.5K]-185C-UV6[2.5K]-135C
|DSK: 1.5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3K]-135C
|DSK: 1.5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3.5K]-135C
|DSK: 1.5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[4K]-135C
|DSK: 1.5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[5K]-135C
|DSK: 1.5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[6K]-135C
|DSK: 1.5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |
|-
|5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[5K]-185C-UV6[2K]-135C
|DSK: 5krpm
UV6: 2.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[2.5K]-135C
|DSK: 5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3K]-135C
|DSK: 5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3.5K]-135C
|DSK: 5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[4K]-135C
|DSK: 5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[5K]-135C
|DSK: 5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[6K]-135C
|DSK: 5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |'''''UV6 Coat with Dry-Etchable BARC underlayer:'''''
|-
|'''''DS-K101 @ 220°C'''''
'''''+ UV6'''''
|Chain
|COAT-DSK101[1.5K]-220C-UV6[2K]-135C
|DSK: 1.5krpm
UV6: 2.0krpm
|DSK: 220°C
UV6: 135°C
|Requires:
– HP4=220°C

– HP1=135°C

Plan for ~10-15 min per wafer.
|-
|1.5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[1.5K]-220C-UV6[2.5K]-135C
|DSK: 1.5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3K]-135C
|DSK: 1.5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3.5K]-135C
|DSK: 1.5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[4K]-135C
|DSK: 1.5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[5K]-135C
|DSK: 1.5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[6K]-135C
|DSK: 1.5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |
|-
|5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[5K]-220C-UV6[2K]-135C
|DSK: 5krpm
UV6: 2.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[2.5K]-135C
|DSK: 5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3K]-135C
|DSK: 5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3.5K]-135C
|DSK: 5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[4K]-135C
|DSK: 5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[5K]-135C
|DSK: 5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[6K]-135C
|DSK: 5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
! colspan="6" |
|-
! colspan="6" |AFTER LITHOGRAPHY (PEB and Developing)
|-
! colspan="6" |
|-
|'''''PEB Wafer Bake'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) for 90sec and cool for 15sec
|-
|
|
|BAKE-135C-90S
|
|135°C
|Requires: HP1=135°C
|-
| colspan="6" |
|-
|'''''PEB and Developing'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) 90sec, cool 15sec, develop using AZ300MIF and water rinse 60sec

WARNING: DONOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE
|-
|Varying developer time
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-10S
|Developer chuck: 300rpm
|135°C
|Requires: HP1=135°C
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-15S
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-20S
|same as above
|same as above
|same as above
|-
| colspan="6" |
|-
|'''Developing'''
|Route
| colspan="4" |To only develop wafer using AZ300MIF and water rinse 60sec

WARNING: DONOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE
|-
|Varying developer time
|
|DEV[MIF300]-SPIN[300RPM]-10S
|Developer chuck: 300rpm
|135°C
|Requires: HP1=135°C
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-15S
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-20S
|same as above
|same as above
|same as above
|-
|
|
|
|
|
|
|}
==[[Holographic Lith/PL Setup (Custom)|Holography Recipes]]==
''The Holography recipes here use the BARC layer XHRiC-11 & the high-res. I-Line photoresist THMR-IP3600HP-D.''

*{{fl|Holography_Process_for_1D-lines_and_2D-dots_%28ARC-11_%26_THMR-IP3600HP-D%29-updated-4-8-2021.pdf|Standard Holography Process - on SiO2 on Si}}
*{{fl|Holography-Process-Variation-revA.pdf|Holography Process Variations - Set-up Angle - Etching into SiO2 and Si}}
*{{fl|05-SiO2_Nano-structure_Etch.pdf|Etch SiO2 Nano-structure - Changing Side-wall Angle - Etching into Si with a different line-width}}
*{{fl|30-Redicing_Nanowire_Diameter_by_Thermal_Oxidation_and_Vapored_HF_Etch.pdf|Reduce SiO2 Nanowire Diameter - Thermal Oxidation - Vapor HF Etching}}

==Low-K Spin-On Dielectric Recipes==

*{{fl|Lithography-BCB-photo-lowk-dielectric-spinon-4024-40-revA.docx|Photo BCB (4024-40)}}
*{{fl|BCB-cyclotene-3000-revA.pdf|Standard BCB (3022-46)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|SOG (T512B)}}

==Chemicals Stocked + Datasheets==
''The following is a list of the lithography chemicals we stock in the lab, with links to the datasheets for each. The datasheets will often have important processing info such as spin-speed vs. thickness curves, typical process parameters, bake temps/times etc.''
{|
|- valign="top"
| width="400" |
;<div id="PositivePR"><big>Positive Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AXP4000pb-Datasheet.pdf|AZP4000 (AZ4110, AZ4210, AZ4330)}}
*{{Fl|Az_p4620_photoresist_data_package.pdf|AZ P4620}}
*{{fl|OCG825-Positive-Resist-Datasheet.pdf|OCG825}}
*{{fl|SPR220-Positive-Resist-Datasheet.pdf|SPR220 (SPR220-3, SPR220-7)}}
*{{fl|SPR955-Positive-Resist-Datasheet.pdf|SPR955CM (SPR955CM-0.9, SPR955CM-1.8)}}
*THMR-3600HP (Thin I-Line & Holography)
**{{fl|THMR_iP_3500_iP3600.pdf|Evaluation Results: THMR-3600HP}}
**{{fl|3600_D,_D2v_Spin_Speed_Curve.pdf|Spin Curves for THMR-3600HP}}
**{{fl|THMR-iP3600_HP_D_20140801_(B)_GHS_US.pdf|Safety Datasheet for THMR-3600HP}}

'''''DUV-248nm'''''

*{{fl|UV210-Positive-Resist-Datasheet.pdf|UV210-0.3}}
*{{fl|UV6-Positive-Resist-Datasheet.pdf|UV6-0.8}}
*{{fl|UV26-Positive-Resist-Datasheet.pdf|UV26-2.5}}

;<div id="NegativePR"><big>Negative Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AZ5214-Negative-Resist-Datasheet.pdf|AZ5214}}
*{{fl|AZnLOF5510-Negative-Resist-Datasheet.pdf|AZnLOF5510}}
*{{fl|AZnLOF2020-Negative-Resist-Datasheet.pdf|AZnLOF2000 (AZnLOF2020, AZnLOF2035, AZnLOF2070)}}
*{{fl|NR9-1000PY-revA.pdf|Futurrex NR9-1000PY(use AZ300MIF dev)}}
*{{fl|NR9-3000PY-revA.pdf|Futurrex NR9-3000PY(use AZ300MIF dev)}}
*{{fl|NR9-6000PY-revA.pdf|Futurrex NR9-6000PY(use AZ300MIF dev)}}
*{{fl|SU-8-2015-revA.pdf|SU-8-2005,2010, 2015}}
*{{fl|SU-8-2075-revA.pdf|SU-8-2075}}

'''''DUV-248nm'''''

*{{fl|UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf|UVN-30-0.8}}

;<div id="Underlayers"><big>Underlayers</big></div>

*{{fl|PMGI-Underlayer-Datasheet.pdf|PMGI (PMGI SF3,5,8,11,15)}}
*{{fl|LOL2000-Underlayer-Datasheet.pdf|Shipley LOL2000}}

;<div id="EBLPR"><big>E-beam resists</big></div>

*{{fl|PMMA-E-Beam-Resist-Datasheet.pdf|PMMA (PMMA, P(MMA-MAA) copolymer)}}
*{{fl|maN2403-E-Beam-Resist-Datasheet.pdf|maN 2403}}

;<div id="NanoImprinting"><big>Nanoimprinting</big></div>

*{{fl|NX1020-Nanoimprinting-Datasheet.pdf|NX1020}}
*{{fl|MRI-7020-Nanoimprinting-Datasheet.pdf|MRI-7020}}
*{{fl|Mr-UVCur21.pdf|MR-UVCur21}}
*{{fl|OrmoStamp-NIL-Lithography-UV-Soft-RevA.pdf|Ormostamp}}

|
;<div id="ContrastEnhancement"><big>Contrast Enhancement Materials</big></div>

*{{fl|CEM365iS-Contrast-Enhancement-Datasheet.pdf|CEM365iS}}

;<div id="AntiReflectionCoatings"><big>Anti-Reflection Coatings</big></div>

*{{fl|XHRiC-Anti-Reflective-Coating.pdf|XHRiC-11 (i-line)}}
*{{fl|DUV42P-Anti-Reflective-Coating.pdf|DUV42P-6 (DUV) (For AR2 replacement)}}
*{{fl|DS-K101-304-Anti-Reflective-Coating.pdf|DS-K101-304 (DUV developable BARC)}}

;<div id="AdhesionPromoters"><big>Adhesion Promoters</big></div>

*HMDS
*AP3000 BCB Adhesion Promoter
*{{fl|OMNICOAT-revA.pdf|Omnicoat, SU-8 Adhesion Promoter}}
*{{fl|OrmoPrime-NIL-Adhesion-RevA.pdf|Ormoprime08-Ormostsmp Adhesion Promoter}}

;<div id="SpinOnDielectrics"><big>Spin-On Dielectrics</big></div>

''Low-K Spin-On Dielectrics such as Benzocyclobutane and Spin-on Glass''

*{{fl|BCB-cyclotene-3000-revA.pdf|BCB, Cyclotene 3022-46(Not Photosensitive)}}
*{{fl|BCB-cyclotene-4000-revA.pdf|PhotoBCB, Cyclotene 4022-40(Negative Polarity)}}
*{{fl|BCB-adhesion.pdf|BCB Adhesion Notes from Vendor}}
*{{fl|BCB-rework.pdf|BCB rework Notes from Vendor}}
*{{fl|512B-Datasheet-revA.pdf|Spin-on-Glass, Honeywell 512B (Not Photosensitive)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|Honeywell 512B Apps Data}}

;<div id="Developers"><big>Developers</big></div>

*{{fl|AZ400K-Developer-Datasheet.pdf|AZ400K (AZ400K, AZ400K1:4)}}
*{{fl|AZ300MIF-Developer-Datasheet.pdf|AZ300MIF}}
*DS2100 BCB Developer
*SU-8 Developer
*101A Developer (for DUV Flood Exposed PMGI)

;<div id="PRRemovers"><big>Photoresist Removers</big></div>

*[http://www.microchemicals.com/products/remover_stripper/nmp.html AZ NMP]
**''This replaces {{fl|1165-Resist-Remover.pdf|1165}}''
*{{fl|AZ300T-Resist-Remover.pdf|AZ300T}}
*{{fl|RemoverPG-revA.pdf|Remover PG, SU-8 stripper}}
*AZ EBR ("Edge Bead Remover", PGMEA)

|}

[[Category: Processing]]
[[category: Lithography]]
[[category: Recipes]]

Lithography Recipes

2024-07-11T16:13:57Z

Gopimeena: /* Recipes Table (S-Cubed Flexi) */

__NOTOC__
{| class="wikitable"
|+
!Table of Contents
|-
|
==='''<big>Photolithography Processes</big>'''===

#'''UV Optical Lithography'''
#*[[#PositivePR |'''Stocked Lithography Chemical + Datasheets''']]
#**''Lists all stocked photolith. chemicals, PRs, strippers, developers, and links to the chemical's application notes/datasheet, which detail the spin curves and nominal processes.''
#*[[#Photolithography_Recipes |'''Photo Lithography Recipe section''']]
#**''Starting recipes (spin, bake, exposure, develop etc.) for all photolith. tools.''
#**''Substrate/surface materials/pattern size can affect process parameters. Users may need to run Focus/Exposure Arrays/Matrix (FEA's/FEM's) with these processes to achieve high-resolution.''
#**[[Contact Alignment Recipes|Contact Aligner Recipes]]
#***[[Contact Alignment Recipes#Suss Aligners .28SUSS MJB-3.29|Suss MJB Aligners]]
#***[[Contact Alignment Recipes#Contact Aligner .28SUSS MA-6.29|Suss MA6]]
#**[[Stepper Recipes|Stepper Recipes]]
#***[[Stepper Recipes#Stepper 1 .28GCA 6300.29|Stepper #1: GCA 6300]] (I-Line)
#***[[Stepper Recipes#Stepper 2 .28AutoStep 200.29|Stepper #2: GCA Autostep 200]] (I-Line)
#***[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Stepper #3: ASML PAS 5500/300]] (DUV)
#**[[Direct-Write Lithography Recipes|Direct-Write Recipes]]
#***[[Direct-Write Lithography Recipes#Maskless Aligner .28Heidelberg MLA150.29|Heidelberg MLA150]]
#***[[Lithography Recipes#E-Beam Lithography Recipes|JEOL JBX-6300FS EBL]]
#***[[Lithography Recipes#FIB Lithography Recipes .28Raith Velion.29|Raith Velion FIB]]
#**[[Lithography Recipes#Automated Coat.2FDevelop System Recipes .28S-Cubed Flexi.29|Automated Coater Recipes (S-Cubed Flexi)]]
#[[Lithography Recipes#General Photolithography Techniques|'''General Photolithography Techniques''']]
#*''Techniques for improving litho. or solving common photolith. problems.''
#'''[[Lithography Recipes#Lift-Off Recipes|Lift-Off Recipes]]'''
#*''Verified Recipes for lift-off using various photolith. tools''
#*''General educational description of this technique and it's limitations/considerations.''
#'''E-beam Lithography'''
#*[[#E-Beam_Lithography_Recipes |E-Beam Lithography Recipes]]
#**''Has links to starting recipes. Substrates and patterns play a large role in process parameters.''
#*[[#EBLPR |EBL Photoresist Datasheets]]
#**''Provided for reference, also showing starting recipes and usage info.''
#'''[[Lithography Recipes#Holography Recipes|Holography]]'''
#*''For 1-D and 2-D gratings with 220nm nominal period, available on substrates up to 1 inch square.''
#*''Recipes for silicon substrates are provided, and have been translated to other substrates by users.''
#*''Datasheets are provided with starting recipes and usage info.''
#'''[[Lithography Recipes#Edge-Bead Removal Techniques|Edge-Bead Removal]]'''
#*''Edge photoresist removal methods needed for clamp-based etchers''
#*''Improves resolution for contact lithography''
|-
|

==='''<big>Photolithography Chemicals/Materials</big>'''===

#'''[[#Underlayers |Underlayers]]'''
#*''These are used beneath resists for both adhesive purposes and to enable bi-layer lift-off profiles for use with photoresist.''
#*''Datasheets are provided.''
#'''[[#AntiReflectionCoatings |Anti-Reflection Coatings]]''':
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Bottom Anti-Reflection Coatings (BARC) are used in the stepper systems, underneath the resists to eliminate substrate reflections that can affect resolution and repeatability for small, near resolution limited, feature sizes.''
#*''Datasheets are provided for reference on use of the materials.''
#'''[[#ContrastEnhancement |Contrast Enhancement Materials (CEM)]]'''
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Used for resolution enhancement. Not for use in contact aligners, typically used on I-Line Steppers.''
#*''Datasheets provided with usage info.''
#'''[[#AdhesionPromoters |Adhesion Promoters]]'''
#*''These are used to improve wetting of photoresists to your substrate.''
#*''Datasheets are provided on use of these materials.''
#'''[[#SpinOnDielectrics |Low-K Spin-on Dielectrics]]'''
#*[[Lithography Recipes#SpinOnDielectrics|Spin-On Dielectrics]]
#**''Datasheets for BCB, Photo-BCB, and SOG (spin-on-glass) for reference on use.''
#*[[#Low-K_Spin-On_Dielectric_Recipes |Low-K Spin-On Dielectric Recipes]]
#**''Recipes for usage of some spin-on dielectrics.''
#'''[[#Developers |Developers and Removers]]'''
#*''Datasheets provided for reference.''
#*''Remover and Photoresist Strippers are used to dissolve PR during lift-off or after etching.''
|}

==General Photolithography Techniques==

====[[Photolithography - Improving Adhesion Photoresist Adhesion|'''HMDS Process for Improving Adhesion''']]====

*''Use these procedures if you are finding poor adhesion PR lifting-off), or for chemicals (like BHF) that attack the PR adhesion interface strongly.''

====[[Photolithography - Manual Edge-Bead Removal Techniques|'''Edge-Bead Removal Techniques''']]====

*''These techniques are required for loading full-wafers into etchers that use top-side clamps, to prevent photoresist from sticking to the clamp (and potentially destroying your wafer).''
*''For contact lithography, this improves the proximity of the mask plate and sample, improving resolution. For some projection systems, such as the [[Maskless Aligner (Heidelberg MLA150)|Maskless Aligner]], EBR can help with autofocus issues.''

====[https://www.microchemicals.com/technical_information/reflow_photoresist.pdf '''Photoresist reflow (MicroChem)''']====

*''To create slanted sidewalls or curved surfaces.''

==Photolithography Recipes==

*'''R''': ''Recipe is available. Clicking this link will take you to the recipe.''
*'''A''': ''Material is available for use, but no recipes are provided.''

''Click the tool title to go to recipes for that tool.''

''Click the photoresist title to get the datasheet, also found in [[Lithography Recipes#Chemicals Stocked .2B Datasheets|Stocked Chemicals + Datasheets]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|-
! colspan="7" height="45" |<div style="font-size: 150%;">Photolithography Recipes</div>

|-
| bgcolor="#EAECF0" |
! colspan="2" align="center" |'''[[Contact Alignment Recipes|<big>Contact Aligner Recipes</big>]]'''
! colspan="3" align="center" |'''[[Stepper Recipes|<big>Stepper Recipes</big>]]'''
! align="center" |[[Direct-Write Lithography Recipes|Direct-Write Litho. Recipes]]
|-
! width="150" bgcolor="#D0E7FF" align="center" |'''Positive Resists'''
{{LithRecipe Table}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[[:File:AXP4000pb-Datasheet.pdf|AZ4110]]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4210]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4330RS]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/a2/Az_p4620_photoresist_data_package.pdf AZ4620]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/8b/OCG825-Positive-Resist-Datasheet.pdf OCG 825-35CS]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-0.9]
|A
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-1.8]
|A
|A
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-3.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-7.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive_Resist_.28MLA150.29}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/be/3600_D%2C_D2v_Spin_Speed_Curve.pdf THMR-IP3600 HP D]
|
|
|A
|A
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/ff/UV210-Positive-Resist-Datasheet.pdf UV210-0.3]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/UV26-Positive-Resist-Datasheet.pdf UV26-2.5]
|
|
|
|
|A
|
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Negative Resists'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/b0/AZ5214-Negative-Resist-Datasheet.pdf AZ5214-EIR]
|{{rl|Contact_Alignment_Recipes|Negative Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2020]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2035]
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |
| bgcolor="EEFFFF" |A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2070]
|A
|A
|A
|A
|
|A
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/82/AZnLOF5510-Negative-Resist-Datasheet.pdf AZnLOF 5510]
|A
|A
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/c/c9/UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf UVN30-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Negative Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/7/78/SU-8-2015-revA.pdf SU-8 2005,2010,2015]
|A
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/2c/SU-8-2075-revA.pdf SU-8 2075]
|A
|A
|A
|A
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |NR9-[//wiki.nanotech.ucsb.edu/w/images/8/8f/NR9-1000PY-revA.pdf 1000],[//wiki.nanotech.ucsb.edu/w/images/7/71/NR9-3000PY-revA.pdf 3000],[//wiki.nanotech.ucsb.edu/w/images/f/f9/NR9-6000PY-revA.pdf 6000]PY
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Anti-Reflection Coatings'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/33/XHRiC-Anti-Reflective-Coating.pdf XHRiC-11]
|
|
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/DUV42P-Anti-Reflective-Coating.pdf DUV42-P]
|
|
|
|
|{{rl|Stepper Recipes|DUV-42P-6}}
|
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101-304]
|
|
|
|
|{{rl|Stepper Recipes|DS-K101-304}}
|
|-
! bgcolor="#D0E7FF" align="center" |
{{LithRecipe Table}}
|}


==Lift-Off Recipes==

*{{fl|Liftoff-Techniques.pdf|Lift-Off Description/Tutorial}}
**How it works, process limits and considerations for designing your process
*[[Lift-Off with I-Line Imaging Resist + LOL2000 Underlayer|I-Line Lift-Off: Bi-Layer Process with LOL2000 Underlayer]]
**''Single Expose/Develop process for simplicity''
**''Up to ~130nm metal thickness & ≥500nm-1000nm gap between metal.''
**''Can use any I-Line litho tool (GCA Stepper, Contact aligner, MLA)''
*{{fl|Bi-LayerContactprocesswithPMGI.pdf|I-Line Lift-Off: Bi-Layer Process with PMGI Underlayer and Contact Aligner}}
**''Multiple processes for Metal thicknesses ~800nm to ~2.5µm''
**''Uses multiple DUV Flood exposure/develop cycles to create undercut.''
**''Can be transferred to other I-Line litho tools (Stepper, MLA etc.)''
*[[Lift-Off with DUV Imaging + PMGI Underlayer|DUV Lift-Off: UV6 Imaging Resist + PMGI Underlayer]]
**''Single-expose/develop process''
**''Up to ~65nm metal thickness & ~350nm gap between metal''
**''Use thicker PMGI for thicker metals''

==[[E-Beam Lithography System (JEOL JBX-6300FS)|E-Beam Lithography Recipes (JEOL JBX-6300FS)]]==

*Under Development.

==[[Focused Ion-Beam Lithography (Raith Velion)|FIB Lithography Recipes (Raith Velion)]]==
''To Be Added''

==[[Automated Coat/Develop System (S-Cubed Flexi)|Automated Coat/Develop System Recipes (S-Cubed Flexi)]]==
Recipes pre-loaded on the S-Cubed Flexi automated coat/bake/develop system. Only staff may write new recipes, contact the tool supervisor for more info.

===Available Variations===

*We have different recipes with varyious UV6 spin speeds - the same spin speed optionss as found on our manual Headway spinners. This allows for PR thickness control. See the linked UV6 datasheets below for thickness vs. rpm spin curves.
*DSK is recommended to be spun at 1.5krpm (~40nm) for best anti-reflection properties. 5krpm (~20nm) recipes are also provided for historical/legacy processes.
*DSK can be baked at either 220C to act as a Dry-etchable BARC (similar to DUV-42P), or at lower temps as a developable BARC (no dry etch required).
*"Chain" recipes (with DSK+UV6 spin/cured in succession) are only available for DSK Baked at 185C & 220C, and all UV6 Spin-speed variations. For the other DSK temps you can use the single-PR "Routes".

===Recipes Table (S-Cubed Flexi)===
{| class="wikitable"
|+''Ask [[Tony Bosch|Staff]] if you need a new recipe.''
|'''''Coating Material'''''
|'''''Route/Chain'''''
|'''''Name''': (User: "UCSB Users")''
|'''''Spin Speed (krpm)'''''
|'''''Bake Temp'''''
|'''''Notes'''''
|-
! colspan="6" |
|-
! colspan="6" |BEFORE LITHOGRAPHY (PR Coat and Bake)
|-
! colspan="6" |
|-
|'''''Hotplate Set'''''
|Route
| colspan="4" |To pre-set the DSK Hotplate temp (HP4).
Note: Only HP4 can be changed. HP1-HP3 remains fixed. HP1=135°C, HP2=170°C & HP3=170°C
|-
|
|
|HP4-SET-220C
|
|220°C
|''Will over shoot +-2°C when done.''
|-
|
|
|HP4-SET-210C
|
|210°C
|
|-
|
|
|HP4-SET-200C
|
|200°C
|
|-
|
|
|HP4-SET-185C
|
|185*C
|
|-
| colspan="6" |
|-
|'''''[https://wiki.nanotech.ucsb.edu/wiki/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101]'''''
|Route
| colspan="4" |''DSK101 Develop Rate depends on Bake temp - you can use this to control undercut.'' ''See: [[DS-K101-304 Bake Temp. versus Develop Rate|DSK Bake vs. Dev rate]]''
DSK101 spun at 1.5K is equivalent to DUV-42P. See: [[Stepper Recipes#Anti-Reflective Coatings]]

'''Note: All PR coat recipes have EBR backside clean steps included in the recipe.'''
|-
|1.5krpm recipes
|
|COAT-DSK101-304[1.5K]-185C
|1.5krpm
|185°C
|Requires: HP4=185°C,
|-
|
|
|COAT-DSK101-304[1.5K]-200C
|1.5krpm
|200°C
|Requires: HP4=200°C
|-
|
|
|COAT-DSK101-304[1.5K]-210C
|1.5krpm
|210°C
|Requires: HP4=210°C
|-
|
|
|COAT-DSK101-304[1.5K]-220C
|1.5krpm
|220°C
|Requires: HP4=220°C,
|-
| colspan="6" |
|-
|5krpm recipes
|
|COAT-DSK101-304[5K]-185C
|5.0krpm
|185°C
|Requires: HP4=185°C,
|-
|
|
|COAT-DSK101-304[5K]-200C
|5.0krpm
|200°C
|Requires: HP4=200°C
|-
|
|
|COAT-DSK101-304[5K]-210C
|5.0krpm
|210°C
|Requires: HP4=210°C
|-
|
|
|COAT-DSK101-304[5K]-220C
|5.0krpm
|220°C
|Requires: HP4=220°C,
|-
| colspan="6" |
|-
|'''''[https://wiki.nanofab.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]'''''
|Route
|COAT-UV6[2K]-135C
|2.0krpm
|135°C
|Requires: HP1=135°C
|-
|varying spin speed
|
|COAT-UV6[2.5K]-135C
|2.5krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[3K]-135C
|3.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[3.5K]-135C
|3.5krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[4K]-135C
|4.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[5K]-135C
|5.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6[6K]-135C
|6.0krpm
|135°C
|Requires: HP1=135°C
|-
| colspan="6" |'''''UV6 Coat with Developable BARC underlayer:'''''
|-
|'''''DS-K101 @ 185°C'''''
'''''+ UV6'''''
|Chain
|COAT-DSK101[1.5K]-185C-UV6[2K]-135C
|DSK: 1.5krpm
UV6: 2.0krpm
|DSK: 185°C
UV6: 135°C
|Requires:
– HP4=185°C

– HP1=135°C

Plan for ~10-15 min per wafer.
|-
|1.5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[1.5K]-185C-UV6[2.5K]-135C
|DSK: 1.5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3K]-135C
|DSK: 1.5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3.5K]-135C
|DSK: 1.5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[4K]-135C
|DSK: 1.5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[5K]-135C
|DSK: 1.5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[6K]-135C
|DSK: 1.5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |
|-
|5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[5K]-185C-UV6[2K]-135C
|DSK: 5krpm
UV6: 2.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[2.5K]-135C
|DSK: 5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3K]-135C
|DSK: 5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3.5K]-135C
|DSK: 5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[4K]-135C
|DSK: 5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[5K]-135C
|DSK: 5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-185C-UV6[6K]-135C
|DSK: 5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |'''''UV6 Coat with Dry-Etchable BARC underlayer:'''''
|-
|'''''DS-K101 @ 220°C'''''
'''''+ UV6'''''
|Chain
|COAT-DSK101[1.5K]-220C-UV6[2K]-135C
|DSK: 1.5krpm
UV6: 2.0krpm
|DSK: 220°C
UV6: 135°C
|Requires:
– HP4=220°C

– HP1=135°C

Plan for ~10-15 min per wafer.
|-
|1.5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[1.5K]-220C-UV6[2.5K]-135C
|DSK: 1.5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3K]-135C
|DSK: 1.5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3.5K]-135C
|DSK: 1.5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[4K]-135C
|DSK: 1.5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[5K]-135C
|DSK: 1.5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[6K]-135C
|DSK: 1.5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |
|-
|5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[5K]-220C-UV6[2K]-135C
|DSK: 5krpm
UV6: 2.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[2.5K]-135C
|DSK: 5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3K]-135C
|DSK: 5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3.5K]-135C
|DSK: 5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[4K]-135C
|DSK: 5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[5K]-135C
|DSK: 5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101[5K]-220C-UV6[6K]-135C
|DSK: 5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
! colspan="6" |
|-
! colspan="6" |AFTER LITHOGRAPHY (PEB and Developing)
|-
! colspan="6" |
|-
|'''''PEB Wafer Bake'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) for 90sec and cool for 15sec
|-
|
|
|BAKE-135C-90S
|
|135°C
|Requires: HP1=135°C
|-
| colspan="6" |
|-
|'''''PEB and Developing'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) 90sec, cool 15sec, develop using AZ300MIF and water rinse 60sec

WARNING: DONOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE
|-
|Varying developer time
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-10S
|Developer chuck: 300rpm
|135°C
|Requires: HP1=135°C
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-15S
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-20S
|same as above
|same as above
|same as above
|-
| colspan="6" |
|-
|'''Developing'''
|Route
| colspan="4" |To only develop wafer using AZ300MIF and water rinse 60sec

WARNING: DONOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE
|-
|Varying developer time
|
|DEV[MIF300]-SPIN[300RPM]-10S
|Developer chuck: 300rpm
|135°C
|Requires: HP1=135°C
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-15S
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-20S
|same as above
|same as above
|same as above
|-
|
|
|
|
|
|
|}
==[[Holographic Lith/PL Setup (Custom)|Holography Recipes]]==
''The Holography recipes here use the BARC layer XHRiC-11 & the high-res. I-Line photoresist THMR-IP3600HP-D.''

*{{fl|Holography_Process_for_1D-lines_and_2D-dots_%28ARC-11_%26_THMR-IP3600HP-D%29-updated-4-8-2021.pdf|Standard Holography Process - on SiO2 on Si}}
*{{fl|Holography-Process-Variation-revA.pdf|Holography Process Variations - Set-up Angle - Etching into SiO2 and Si}}
*{{fl|05-SiO2_Nano-structure_Etch.pdf|Etch SiO2 Nano-structure - Changing Side-wall Angle - Etching into Si with a different line-width}}
*{{fl|30-Redicing_Nanowire_Diameter_by_Thermal_Oxidation_and_Vapored_HF_Etch.pdf|Reduce SiO2 Nanowire Diameter - Thermal Oxidation - Vapor HF Etching}}

==Low-K Spin-On Dielectric Recipes==

*{{fl|Lithography-BCB-photo-lowk-dielectric-spinon-4024-40-revA.docx|Photo BCB (4024-40)}}
*{{fl|BCB-cyclotene-3000-revA.pdf|Standard BCB (3022-46)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|SOG (T512B)}}

==Chemicals Stocked + Datasheets==
''The following is a list of the lithography chemicals we stock in the lab, with links to the datasheets for each. The datasheets will often have important processing info such as spin-speed vs. thickness curves, typical process parameters, bake temps/times etc.''
{|
|- valign="top"
| width="400" |
;<div id="PositivePR"><big>Positive Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AXP4000pb-Datasheet.pdf|AZP4000 (AZ4110, AZ4210, AZ4330)}}
*{{Fl|Az_p4620_photoresist_data_package.pdf|AZ P4620}}
*{{fl|OCG825-Positive-Resist-Datasheet.pdf|OCG825}}
*{{fl|SPR220-Positive-Resist-Datasheet.pdf|SPR220 (SPR220-3, SPR220-7)}}
*{{fl|SPR955-Positive-Resist-Datasheet.pdf|SPR955CM (SPR955CM-0.9, SPR955CM-1.8)}}
*THMR-3600HP (Thin I-Line & Holography)
**{{fl|THMR_iP_3500_iP3600.pdf|Evaluation Results: THMR-3600HP}}
**{{fl|3600_D,_D2v_Spin_Speed_Curve.pdf|Spin Curves for THMR-3600HP}}
**{{fl|THMR-iP3600_HP_D_20140801_(B)_GHS_US.pdf|Safety Datasheet for THMR-3600HP}}

'''''DUV-248nm'''''

*{{fl|UV210-Positive-Resist-Datasheet.pdf|UV210-0.3}}
*{{fl|UV6-Positive-Resist-Datasheet.pdf|UV6-0.8}}
*{{fl|UV26-Positive-Resist-Datasheet.pdf|UV26-2.5}}

;<div id="NegativePR"><big>Negative Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AZ5214-Negative-Resist-Datasheet.pdf|AZ5214}}
*{{fl|AZnLOF5510-Negative-Resist-Datasheet.pdf|AZnLOF5510}}
*{{fl|AZnLOF2020-Negative-Resist-Datasheet.pdf|AZnLOF2000 (AZnLOF2020, AZnLOF2035, AZnLOF2070)}}
*{{fl|NR9-1000PY-revA.pdf|Futurrex NR9-1000PY(use AZ300MIF dev)}}
*{{fl|NR9-3000PY-revA.pdf|Futurrex NR9-3000PY(use AZ300MIF dev)}}
*{{fl|NR9-6000PY-revA.pdf|Futurrex NR9-6000PY(use AZ300MIF dev)}}
*{{fl|SU-8-2015-revA.pdf|SU-8-2005,2010, 2015}}
*{{fl|SU-8-2075-revA.pdf|SU-8-2075}}

'''''DUV-248nm'''''

*{{fl|UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf|UVN-30-0.8}}

;<div id="Underlayers"><big>Underlayers</big></div>

*{{fl|PMGI-Underlayer-Datasheet.pdf|PMGI (PMGI SF3,5,8,11,15)}}
*{{fl|LOL2000-Underlayer-Datasheet.pdf|Shipley LOL2000}}

;<div id="EBLPR"><big>E-beam resists</big></div>

*{{fl|PMMA-E-Beam-Resist-Datasheet.pdf|PMMA (PMMA, P(MMA-MAA) copolymer)}}
*{{fl|maN2403-E-Beam-Resist-Datasheet.pdf|maN 2403}}

;<div id="NanoImprinting"><big>Nanoimprinting</big></div>

*{{fl|NX1020-Nanoimprinting-Datasheet.pdf|NX1020}}
*{{fl|MRI-7020-Nanoimprinting-Datasheet.pdf|MRI-7020}}
*{{fl|Mr-UVCur21.pdf|MR-UVCur21}}
*{{fl|OrmoStamp-NIL-Lithography-UV-Soft-RevA.pdf|Ormostamp}}

|
;<div id="ContrastEnhancement"><big>Contrast Enhancement Materials</big></div>

*{{fl|CEM365iS-Contrast-Enhancement-Datasheet.pdf|CEM365iS}}

;<div id="AntiReflectionCoatings"><big>Anti-Reflection Coatings</big></div>

*{{fl|XHRiC-Anti-Reflective-Coating.pdf|XHRiC-11 (i-line)}}
*{{fl|DUV42P-Anti-Reflective-Coating.pdf|DUV42P-6 (DUV) (For AR2 replacement)}}
*{{fl|DS-K101-304-Anti-Reflective-Coating.pdf|DS-K101-304 (DUV developable BARC)}}

;<div id="AdhesionPromoters"><big>Adhesion Promoters</big></div>

*HMDS
*AP3000 BCB Adhesion Promoter
*{{fl|OMNICOAT-revA.pdf|Omnicoat, SU-8 Adhesion Promoter}}
*{{fl|OrmoPrime-NIL-Adhesion-RevA.pdf|Ormoprime08-Ormostsmp Adhesion Promoter}}

;<div id="SpinOnDielectrics"><big>Spin-On Dielectrics</big></div>

''Low-K Spin-On Dielectrics such as Benzocyclobutane and Spin-on Glass''

*{{fl|BCB-cyclotene-3000-revA.pdf|BCB, Cyclotene 3022-46(Not Photosensitive)}}
*{{fl|BCB-cyclotene-4000-revA.pdf|PhotoBCB, Cyclotene 4022-40(Negative Polarity)}}
*{{fl|BCB-adhesion.pdf|BCB Adhesion Notes from Vendor}}
*{{fl|BCB-rework.pdf|BCB rework Notes from Vendor}}
*{{fl|512B-Datasheet-revA.pdf|Spin-on-Glass, Honeywell 512B (Not Photosensitive)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|Honeywell 512B Apps Data}}

;<div id="Developers"><big>Developers</big></div>

*{{fl|AZ400K-Developer-Datasheet.pdf|AZ400K (AZ400K, AZ400K1:4)}}
*{{fl|AZ300MIF-Developer-Datasheet.pdf|AZ300MIF}}
*DS2100 BCB Developer
*SU-8 Developer
*101A Developer (for DUV Flood Exposed PMGI)

;<div id="PRRemovers"><big>Photoresist Removers</big></div>

*[http://www.microchemicals.com/products/remover_stripper/nmp.html AZ NMP]
**''This replaces {{fl|1165-Resist-Remover.pdf|1165}}''
*{{fl|AZ300T-Resist-Remover.pdf|AZ300T}}
*{{fl|RemoverPG-revA.pdf|Remover PG, SU-8 stripper}}
*AZ EBR ("Edge Bead Remover", PGMEA)

|}

[[Category: Processing]]
[[category: Lithography]]
[[category: Recipes]]

Lithography Recipes

2024-07-11T16:10:22Z

Gopimeena: Fixed some mistakes

__NOTOC__
{| class="wikitable"
|+
!Table of Contents
|-
|
==='''<big>Photolithography Processes</big>'''===

#'''UV Optical Lithography'''
#*[[#PositivePR |'''Stocked Lithography Chemical + Datasheets''']]
#**''Lists all stocked photolith. chemicals, PRs, strippers, developers, and links to the chemical's application notes/datasheet, which detail the spin curves and nominal processes.''
#*[[#Photolithography_Recipes |'''Photo Lithography Recipe section''']]
#**''Starting recipes (spin, bake, exposure, develop etc.) for all photolith. tools.''
#**''Substrate/surface materials/pattern size can affect process parameters. Users may need to run Focus/Exposure Arrays/Matrix (FEA's/FEM's) with these processes to achieve high-resolution.''
#**[[Contact Alignment Recipes|Contact Aligner Recipes]]
#***[[Contact Alignment Recipes#Suss Aligners .28SUSS MJB-3.29|Suss MJB Aligners]]
#***[[Contact Alignment Recipes#Contact Aligner .28SUSS MA-6.29|Suss MA6]]
#**[[Stepper Recipes|Stepper Recipes]]
#***[[Stepper Recipes#Stepper 1 .28GCA 6300.29|Stepper #1: GCA 6300]] (I-Line)
#***[[Stepper Recipes#Stepper 2 .28AutoStep 200.29|Stepper #2: GCA Autostep 200]] (I-Line)
#***[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Stepper #3: ASML PAS 5500/300]] (DUV)
#**[[Direct-Write Lithography Recipes|Direct-Write Recipes]]
#***[[Direct-Write Lithography Recipes#Maskless Aligner .28Heidelberg MLA150.29|Heidelberg MLA150]]
#***[[Lithography Recipes#E-Beam Lithography Recipes|JEOL JBX-6300FS EBL]]
#***[[Lithography Recipes#FIB Lithography Recipes .28Raith Velion.29|Raith Velion FIB]]
#**[[Lithography Recipes#Automated Coat.2FDevelop System Recipes .28S-Cubed Flexi.29|Automated Coater Recipes (S-Cubed Flexi)]]
#[[Lithography Recipes#General Photolithography Techniques|'''General Photolithography Techniques''']]
#*''Techniques for improving litho. or solving common photolith. problems.''
#'''[[Lithography Recipes#Lift-Off Recipes|Lift-Off Recipes]]'''
#*''Verified Recipes for lift-off using various photolith. tools''
#*''General educational description of this technique and it's limitations/considerations.''
#'''E-beam Lithography'''
#*[[#E-Beam_Lithography_Recipes |E-Beam Lithography Recipes]]
#**''Has links to starting recipes. Substrates and patterns play a large role in process parameters.''
#*[[#EBLPR |EBL Photoresist Datasheets]]
#**''Provided for reference, also showing starting recipes and usage info.''
#'''[[Lithography Recipes#Holography Recipes|Holography]]'''
#*''For 1-D and 2-D gratings with 220nm nominal period, available on substrates up to 1 inch square.''
#*''Recipes for silicon substrates are provided, and have been translated to other substrates by users.''
#*''Datasheets are provided with starting recipes and usage info.''
#'''[[Lithography Recipes#Edge-Bead Removal Techniques|Edge-Bead Removal]]'''
#*''Edge photoresist removal methods needed for clamp-based etchers''
#*''Improves resolution for contact lithography''
|-
|

==='''<big>Photolithography Chemicals/Materials</big>'''===

#'''[[#Underlayers |Underlayers]]'''
#*''These are used beneath resists for both adhesive purposes and to enable bi-layer lift-off profiles for use with photoresist.''
#*''Datasheets are provided.''
#'''[[#AntiReflectionCoatings |Anti-Reflection Coatings]]''':
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Bottom Anti-Reflection Coatings (BARC) are used in the stepper systems, underneath the resists to eliminate substrate reflections that can affect resolution and repeatability for small, near resolution limited, feature sizes.''
#*''Datasheets are provided for reference on use of the materials.''
#'''[[#ContrastEnhancement |Contrast Enhancement Materials (CEM)]]'''
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Used for resolution enhancement. Not for use in contact aligners, typically used on I-Line Steppers.''
#*''Datasheets provided with usage info.''
#'''[[#AdhesionPromoters |Adhesion Promoters]]'''
#*''These are used to improve wetting of photoresists to your substrate.''
#*''Datasheets are provided on use of these materials.''
#'''[[#SpinOnDielectrics |Low-K Spin-on Dielectrics]]'''
#*[[Lithography Recipes#SpinOnDielectrics|Spin-On Dielectrics]]
#**''Datasheets for BCB, Photo-BCB, and SOG (spin-on-glass) for reference on use.''
#*[[#Low-K_Spin-On_Dielectric_Recipes |Low-K Spin-On Dielectric Recipes]]
#**''Recipes for usage of some spin-on dielectrics.''
#'''[[#Developers |Developers and Removers]]'''
#*''Datasheets provided for reference.''
#*''Remover and Photoresist Strippers are used to dissolve PR during lift-off or after etching.''
|}

==General Photolithography Techniques==

====[[Photolithography - Improving Adhesion Photoresist Adhesion|'''HMDS Process for Improving Adhesion''']]====

*''Use these procedures if you are finding poor adhesion PR lifting-off), or for chemicals (like BHF) that attack the PR adhesion interface strongly.''

====[[Photolithography - Manual Edge-Bead Removal Techniques|'''Edge-Bead Removal Techniques''']]====

*''These techniques are required for loading full-wafers into etchers that use top-side clamps, to prevent photoresist from sticking to the clamp (and potentially destroying your wafer).''
*''For contact lithography, this improves the proximity of the mask plate and sample, improving resolution. For some projection systems, such as the [[Maskless Aligner (Heidelberg MLA150)|Maskless Aligner]], EBR can help with autofocus issues.''

====[https://www.microchemicals.com/technical_information/reflow_photoresist.pdf '''Photoresist reflow (MicroChem)''']====

*''To create slanted sidewalls or curved surfaces.''

==Photolithography Recipes==

*'''R''': ''Recipe is available. Clicking this link will take you to the recipe.''
*'''A''': ''Material is available for use, but no recipes are provided.''

''Click the tool title to go to recipes for that tool.''

''Click the photoresist title to get the datasheet, also found in [[Lithography Recipes#Chemicals Stocked .2B Datasheets|Stocked Chemicals + Datasheets]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|-
! colspan="7" height="45" |<div style="font-size: 150%;">Photolithography Recipes</div>

|-
| bgcolor="#EAECF0" |
! colspan="2" align="center" |'''[[Contact Alignment Recipes|<big>Contact Aligner Recipes</big>]]'''
! colspan="3" align="center" |'''[[Stepper Recipes|<big>Stepper Recipes</big>]]'''
! align="center" |[[Direct-Write Lithography Recipes|Direct-Write Litho. Recipes]]
|-
! width="150" bgcolor="#D0E7FF" align="center" |'''Positive Resists'''
{{LithRecipe Table}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[[:File:AXP4000pb-Datasheet.pdf|AZ4110]]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4210]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4330RS]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/a2/Az_p4620_photoresist_data_package.pdf AZ4620]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/8b/OCG825-Positive-Resist-Datasheet.pdf OCG 825-35CS]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-0.9]
|A
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-1.8]
|A
|A
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-3.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-7.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive_Resist_.28MLA150.29}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/be/3600_D%2C_D2v_Spin_Speed_Curve.pdf THMR-IP3600 HP D]
|
|
|A
|A
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/ff/UV210-Positive-Resist-Datasheet.pdf UV210-0.3]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/UV26-Positive-Resist-Datasheet.pdf UV26-2.5]
|
|
|
|
|A
|
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Negative Resists'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/b0/AZ5214-Negative-Resist-Datasheet.pdf AZ5214-EIR]
|{{rl|Contact_Alignment_Recipes|Negative Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2020]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2035]
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |
| bgcolor="EEFFFF" |A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2070]
|A
|A
|A
|A
|
|A
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/82/AZnLOF5510-Negative-Resist-Datasheet.pdf AZnLOF 5510]
|A
|A
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/c/c9/UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf UVN30-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Negative Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/7/78/SU-8-2015-revA.pdf SU-8 2005,2010,2015]
|A
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/2c/SU-8-2075-revA.pdf SU-8 2075]
|A
|A
|A
|A
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |NR9-[//wiki.nanotech.ucsb.edu/w/images/8/8f/NR9-1000PY-revA.pdf 1000],[//wiki.nanotech.ucsb.edu/w/images/7/71/NR9-3000PY-revA.pdf 3000],[//wiki.nanotech.ucsb.edu/w/images/f/f9/NR9-6000PY-revA.pdf 6000]PY
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Anti-Reflection Coatings'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/33/XHRiC-Anti-Reflective-Coating.pdf XHRiC-11]
|
|
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/DUV42P-Anti-Reflective-Coating.pdf DUV42-P]
|
|
|
|
|{{rl|Stepper Recipes|DUV-42P-6}}
|
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101-304]
|
|
|
|
|{{rl|Stepper Recipes|DS-K101-304}}
|
|-
! bgcolor="#D0E7FF" align="center" |
{{LithRecipe Table}}
|}


==Lift-Off Recipes==

*{{fl|Liftoff-Techniques.pdf|Lift-Off Description/Tutorial}}
**How it works, process limits and considerations for designing your process
*[[Lift-Off with I-Line Imaging Resist + LOL2000 Underlayer|I-Line Lift-Off: Bi-Layer Process with LOL2000 Underlayer]]
**''Single Expose/Develop process for simplicity''
**''Up to ~130nm metal thickness & ≥500nm-1000nm gap between metal.''
**''Can use any I-Line litho tool (GCA Stepper, Contact aligner, MLA)''
*{{fl|Bi-LayerContactprocesswithPMGI.pdf|I-Line Lift-Off: Bi-Layer Process with PMGI Underlayer and Contact Aligner}}
**''Multiple processes for Metal thicknesses ~800nm to ~2.5µm''
**''Uses multiple DUV Flood exposure/develop cycles to create undercut.''
**''Can be transferred to other I-Line litho tools (Stepper, MLA etc.)''
*[[Lift-Off with DUV Imaging + PMGI Underlayer|DUV Lift-Off: UV6 Imaging Resist + PMGI Underlayer]]
**''Single-expose/develop process''
**''Up to ~65nm metal thickness & ~350nm gap between metal''
**''Use thicker PMGI for thicker metals''

==[[E-Beam Lithography System (JEOL JBX-6300FS)|E-Beam Lithography Recipes (JEOL JBX-6300FS)]]==

*Under Development.

==[[Focused Ion-Beam Lithography (Raith Velion)|FIB Lithography Recipes (Raith Velion)]]==
''To Be Added''

==[[Automated Coat/Develop System (S-Cubed Flexi)|Automated Coat/Develop System Recipes (S-Cubed Flexi)]]==
Recipes pre-loaded on the S-Cubed Flexi automated coat/bake/develop system. Only staff may write new recipes, contact the tool supervisor for more info.

===Available Variations===

*We have different recipes with varyious UV6 spin speeds - the same spin speed optionss as found on our manual Headway spinners. This allows for PR thickness control. See the linked UV6 datasheets below for thickness vs. rpm spin curves.
*DSK is recommended to be spun at 1.5krpm (~40nm) for best anti-reflection properties. 5krpm (~20nm) recipes are also provided for historical/legacy processes.
*DSK can be baked at either 220C to act as a Dry-etchable BARC (similar to DUV-42P), or at lower temps as a developable BARC (no dry etch required).
*"Chain" recipes (with DSK+UV6 spin/cured in succession) are only available for DSK Baked at 185C & 220C, and all UV6 Spin-speed variations. For the other DSK temps you can use the single-PR "Routes".

===Recipes Table (S-Cubed Flexi)===
{| class="wikitable"
|+''Ask [[Tony Bosch|Staff]] if you need a new recipe.''
|'''''Coating Material'''''
|'''''Route/Chain'''''
|'''''Name''': (User: "UCSB Users")''
|'''''Spin Speed (krpm)'''''
|'''''Bake Temp'''''
|'''''Notes'''''
|-
! colspan="6" |
|-
! colspan="6" |BEFORE LITHOGRAPHY (PR Coat and Bake)
|-
! colspan="6" |
|-
|'''''Hotplate Set'''''
|Route
| colspan="4" |To pre-set the DSK Hotplate temp (HP4).
Note: Only HP4 can be changed. HP1-HP3 remains fixed. HP1=135°C, HP2=170°C & HP3=170°C
|-
|
|
|HP4-SET-220C
|
|220°C
|''Will over shoot +-2°C when done.''
|-
|
|
|HP4-SET-210C
|
|210°C
|
|-
|
|
|HP4-SET-200C
|
|200°C
|
|-
|
|
|HP4-SET-185C
|
|185*C
|
|-
| colspan="6" |
|-
|'''''[https://wiki.nanotech.ucsb.edu/wiki/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101]'''''
|Route
| colspan="4" |''DSK101 Develop Rate depends on Bake temp - you can use this to control undercut.'' ''See: [[DS-K101-304 Bake Temp. versus Develop Rate|DSK Bake vs. Dev rate]]''
DSK101 spun at 1.5K is equivalent to DUV-42P. See: [[Stepper Recipes#Anti-Reflective Coatings]]

'''Note: All PR coat recipes have EBR backside clean steps included in the recipe.'''
|-
|1.5krpm recipes
|
|COAT-DSK101-304[1.5K]-185C
|1.5
|185°C
|''Requires: HP4=185°C,''
|-
|
|
|COAT-DSK101-304[1.5K]-200C
|1.5
|200°C
|''Requires: HP4=200°C''
|-
|
|
|COAT-DSK101-304[1.5K]-210C
|1.5
|210°C
|''Requires: HP4=210°C''
|-
|
|
|COAT-DSK101-304[1.5K]-220C
|1.5
|220°C
|''Requires: HP4=220°C,''
|-
| colspan="6" |
|-
|5krpm recipes
|
|COAT-DSK101-304[5K]-185C
|5.0
|185°C
|''Requires: HP4=185°C,''
|-
|
|
|COAT-DSK101-304[5K]-200C
|5.0
|200°C
|''Requires: HP4=200°C''
|-
|
|
|COAT-DSK101-304[5K]-210C
|5.0
|210°C
|''Requires: HP4=210°C''
|-
|
|
|COAT-DSK101-304[5K]-220C
|5.0
|220°C
|''Requires: HP4=220°C,''
|-
| colspan="6" |
|-
|'''''[https://wiki.nanofab.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]'''''
|Route
|COAT-UV6[2K]-135C
|2.0
|135°C
|''Requires: HP1=135°C''
|-
|varying spin speed
|
|COAT-UV6[2.5K]-135C
|2.5
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[3K]-135C
|3.0
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[3.5K]-135C
|3.5
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[4K]-135C
|4.0
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[5K]-135C
|5.0
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[6K]-135C
|6.0
|135°C
|''Requires: HP1=135°C''
|-
| colspan="6" |'''''UV6 Coat with Developable BARC underlayer:'''''
|-
|'''''DS-K101 @ 185°C'''''
'''''+ UV6'''''
|Chain
|COAT-DSK101[1.5K]-185C-UV6[2K]-135C
|''DSK: 1.5krpm''
''UV6: 2.0krpm''
|DSK: 185°C
UV6: 135°C
|''Requires:''
''– HP4=185°C''

''– HP1=135°C''

''Plan for ~10-15 min per wafer.''
|-
|1.5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[1.5K]-185C-UV6[2.5K]-135C
|''DSK: 1.5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3K]-135C
|''DSK: 1.5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3.5K]-135C
|''DSK: 1.5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[4K]-135C
|''DSK: 1.5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[5K]-135C
|''DSK: 1.5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[6K]-135C
|''DSK: 1.5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
| colspan="6" |
|-
|5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[5K]-185C-UV6[2K]-135C
|''DSK: 5krpm''
''UV6: 2.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[2.5K]-135C
|''DSK: 5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3K]-135C
|''DSK: 5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3.5K]-135C
|''DSK: 5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[4K]-135C
|''DSK: 5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[5K]-135C
|''DSK: 5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[6K]-135C
|''DSK: 5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
| colspan="6" |'''''UV6 Coat with Dry-Etchable BARC underlayer:'''''
|-
|'''''DS-K101 @ 220°C'''''
'''''+ UV6'''''
|Chain
|COAT-DSK101[1.5K]-220C-UV6[2K]-135C
|''DSK: 1.5krpm''
''UV6: 2.0krpm''
|DSK: 220°C
UV6: 135°C
|''Requires:''
''– HP4=220°C''

''– HP1=135°C''

''Plan for ~10-15 min per wafer.''
|-
|1.5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[1.5K]-220C-UV6[2.5K]-135C
|''DSK: 1.5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3K]-135C
|''DSK: 1.5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3.5K]-135C
|''DSK: 1.5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[4K]-135C
|''DSK: 1.5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[5K]-135C
|''DSK: 1.5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[6K]-135C
|''DSK: 1.5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
| colspan="6" |
|-
|5krpm DSK recipes with
UV6- various spin speeds
|
|COAT-DSK101[5K]-220C-UV6[2K]-135C
|''DSK: 5krpm''
''UV6: 2.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[2.5K]-135C
|''DSK: 5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3K]-135C
|''DSK: 5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3.5K]-135C
|''DSK: 5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[4K]-135C
|''DSK: 5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[5K]-135C
|''DSK: 5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[6K]-135C
|''DSK: 5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
! colspan="6" |
|-
! colspan="6" |AFTER LITHOGRAPHY (PEB and Developing)
|-
! colspan="6" |
|-
|'''''PEB Wafer Bake'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) for 90sec and cool for 15sec
|-
|
|
|BAKE-135C-90S
|
|135°C
|''Requires: HP1=135°C''
|-
| colspan="6" |
|-
|'''''PEB and Developing'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) 90sec, cool 15sec, develop using AZ300MIF and water rinse 60sec

WARNING: DONOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE
|-
|Varying developer time
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-10S
|Developer chuck: 300rpm
|135°C
|''Requires: HP1=135°C''
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-15S
|''same as above''
|''same as above''
|''same as above''
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-20S
|''same as above''
|''same as above''
|''same as above''
|-
| colspan="6" |
|-
|'''Developing'''
|Route
| colspan="4" |To only develop wafer using AZ300MIF and water rinse 60sec

WARNING: DONOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE
|-
|Varying developer time
|
|DEV[MIF300]-SPIN[300RPM]-10S
|Developer chuck: 300rpm
|135°C
|''Requires: HP1=135°C''
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-15S
|''same as above''
|''same as above''
|''same as above''
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-20S
|''same as above''
|''same as above''
|''same as above''
|-
|
|
|
|
|
|
|}
==[[Holographic Lith/PL Setup (Custom)|Holography Recipes]]==
''The Holography recipes here use the BARC layer XHRiC-11 & the high-res. I-Line photoresist THMR-IP3600HP-D.''

*{{fl|Holography_Process_for_1D-lines_and_2D-dots_%28ARC-11_%26_THMR-IP3600HP-D%29-updated-4-8-2021.pdf|Standard Holography Process - on SiO2 on Si}}
*{{fl|Holography-Process-Variation-revA.pdf|Holography Process Variations - Set-up Angle - Etching into SiO2 and Si}}
*{{fl|05-SiO2_Nano-structure_Etch.pdf|Etch SiO2 Nano-structure - Changing Side-wall Angle - Etching into Si with a different line-width}}
*{{fl|30-Redicing_Nanowire_Diameter_by_Thermal_Oxidation_and_Vapored_HF_Etch.pdf|Reduce SiO2 Nanowire Diameter - Thermal Oxidation - Vapor HF Etching}}

==Low-K Spin-On Dielectric Recipes==

*{{fl|Lithography-BCB-photo-lowk-dielectric-spinon-4024-40-revA.docx|Photo BCB (4024-40)}}
*{{fl|BCB-cyclotene-3000-revA.pdf|Standard BCB (3022-46)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|SOG (T512B)}}

==Chemicals Stocked + Datasheets==
''The following is a list of the lithography chemicals we stock in the lab, with links to the datasheets for each. The datasheets will often have important processing info such as spin-speed vs. thickness curves, typical process parameters, bake temps/times etc.''
{|
|- valign="top"
| width="400" |
;<div id="PositivePR"><big>Positive Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AXP4000pb-Datasheet.pdf|AZP4000 (AZ4110, AZ4210, AZ4330)}}
*{{Fl|Az_p4620_photoresist_data_package.pdf|AZ P4620}}
*{{fl|OCG825-Positive-Resist-Datasheet.pdf|OCG825}}
*{{fl|SPR220-Positive-Resist-Datasheet.pdf|SPR220 (SPR220-3, SPR220-7)}}
*{{fl|SPR955-Positive-Resist-Datasheet.pdf|SPR955CM (SPR955CM-0.9, SPR955CM-1.8)}}
*THMR-3600HP (Thin I-Line & Holography)
**{{fl|THMR_iP_3500_iP3600.pdf|Evaluation Results: THMR-3600HP}}
**{{fl|3600_D,_D2v_Spin_Speed_Curve.pdf|Spin Curves for THMR-3600HP}}
**{{fl|THMR-iP3600_HP_D_20140801_(B)_GHS_US.pdf|Safety Datasheet for THMR-3600HP}}

'''''DUV-248nm'''''

*{{fl|UV210-Positive-Resist-Datasheet.pdf|UV210-0.3}}
*{{fl|UV6-Positive-Resist-Datasheet.pdf|UV6-0.8}}
*{{fl|UV26-Positive-Resist-Datasheet.pdf|UV26-2.5}}

;<div id="NegativePR"><big>Negative Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AZ5214-Negative-Resist-Datasheet.pdf|AZ5214}}
*{{fl|AZnLOF5510-Negative-Resist-Datasheet.pdf|AZnLOF5510}}
*{{fl|AZnLOF2020-Negative-Resist-Datasheet.pdf|AZnLOF2000 (AZnLOF2020, AZnLOF2035, AZnLOF2070)}}
*{{fl|NR9-1000PY-revA.pdf|Futurrex NR9-1000PY(use AZ300MIF dev)}}
*{{fl|NR9-3000PY-revA.pdf|Futurrex NR9-3000PY(use AZ300MIF dev)}}
*{{fl|NR9-6000PY-revA.pdf|Futurrex NR9-6000PY(use AZ300MIF dev)}}
*{{fl|SU-8-2015-revA.pdf|SU-8-2005,2010, 2015}}
*{{fl|SU-8-2075-revA.pdf|SU-8-2075}}

'''''DUV-248nm'''''

*{{fl|UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf|UVN-30-0.8}}

;<div id="Underlayers"><big>Underlayers</big></div>

*{{fl|PMGI-Underlayer-Datasheet.pdf|PMGI (PMGI SF3,5,8,11,15)}}
*{{fl|LOL2000-Underlayer-Datasheet.pdf|Shipley LOL2000}}

;<div id="EBLPR"><big>E-beam resists</big></div>

*{{fl|PMMA-E-Beam-Resist-Datasheet.pdf|PMMA (PMMA, P(MMA-MAA) copolymer)}}
*{{fl|maN2403-E-Beam-Resist-Datasheet.pdf|maN 2403}}

;<div id="NanoImprinting"><big>Nanoimprinting</big></div>

*{{fl|NX1020-Nanoimprinting-Datasheet.pdf|NX1020}}
*{{fl|MRI-7020-Nanoimprinting-Datasheet.pdf|MRI-7020}}
*{{fl|Mr-UVCur21.pdf|MR-UVCur21}}
*{{fl|OrmoStamp-NIL-Lithography-UV-Soft-RevA.pdf|Ormostamp}}

|
;<div id="ContrastEnhancement"><big>Contrast Enhancement Materials</big></div>

*{{fl|CEM365iS-Contrast-Enhancement-Datasheet.pdf|CEM365iS}}

;<div id="AntiReflectionCoatings"><big>Anti-Reflection Coatings</big></div>

*{{fl|XHRiC-Anti-Reflective-Coating.pdf|XHRiC-11 (i-line)}}
*{{fl|DUV42P-Anti-Reflective-Coating.pdf|DUV42P-6 (DUV) (For AR2 replacement)}}
*{{fl|DS-K101-304-Anti-Reflective-Coating.pdf|DS-K101-304 (DUV developable BARC)}}

;<div id="AdhesionPromoters"><big>Adhesion Promoters</big></div>

*HMDS
*AP3000 BCB Adhesion Promoter
*{{fl|OMNICOAT-revA.pdf|Omnicoat, SU-8 Adhesion Promoter}}
*{{fl|OrmoPrime-NIL-Adhesion-RevA.pdf|Ormoprime08-Ormostsmp Adhesion Promoter}}

;<div id="SpinOnDielectrics"><big>Spin-On Dielectrics</big></div>

''Low-K Spin-On Dielectrics such as Benzocyclobutane and Spin-on Glass''

*{{fl|BCB-cyclotene-3000-revA.pdf|BCB, Cyclotene 3022-46(Not Photosensitive)}}
*{{fl|BCB-cyclotene-4000-revA.pdf|PhotoBCB, Cyclotene 4022-40(Negative Polarity)}}
*{{fl|BCB-adhesion.pdf|BCB Adhesion Notes from Vendor}}
*{{fl|BCB-rework.pdf|BCB rework Notes from Vendor}}
*{{fl|512B-Datasheet-revA.pdf|Spin-on-Glass, Honeywell 512B (Not Photosensitive)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|Honeywell 512B Apps Data}}

;<div id="Developers"><big>Developers</big></div>

*{{fl|AZ400K-Developer-Datasheet.pdf|AZ400K (AZ400K, AZ400K1:4)}}
*{{fl|AZ300MIF-Developer-Datasheet.pdf|AZ300MIF}}
*DS2100 BCB Developer
*SU-8 Developer
*101A Developer (for DUV Flood Exposed PMGI)

;<div id="PRRemovers"><big>Photoresist Removers</big></div>

*[http://www.microchemicals.com/products/remover_stripper/nmp.html AZ NMP]
**''This replaces {{fl|1165-Resist-Remover.pdf|1165}}''
*{{fl|AZ300T-Resist-Remover.pdf|AZ300T}}
*{{fl|RemoverPG-revA.pdf|Remover PG, SU-8 stripper}}
*AZ EBR ("Edge Bead Remover", PGMEA)

|}

[[Category: Processing]]
[[category: Lithography]]
[[category: Recipes]]

Lithography Recipes

2024-07-11T15:59:30Z

Gopimeena: Added all S-Cube recipes open for UCSB USER

__NOTOC__
{| class="wikitable"
|+
!Table of Contents
|-
|
==='''<big>Photolithography Processes</big>'''===

#'''UV Optical Lithography'''
#*[[#PositivePR |'''Stocked Lithography Chemical + Datasheets''']]
#**''Lists all stocked photolith. chemicals, PRs, strippers, developers, and links to the chemical's application notes/datasheet, which detail the spin curves and nominal processes.''
#*[[#Photolithography_Recipes |'''Photo Lithography Recipe section''']]
#**''Starting recipes (spin, bake, exposure, develop etc.) for all photolith. tools.''
#**''Substrate/surface materials/pattern size can affect process parameters. Users may need to run Focus/Exposure Arrays/Matrix (FEA's/FEM's) with these processes to achieve high-resolution.''
#**[[Contact Alignment Recipes|Contact Aligner Recipes]]
#***[[Contact Alignment Recipes#Suss Aligners .28SUSS MJB-3.29|Suss MJB Aligners]]
#***[[Contact Alignment Recipes#Contact Aligner .28SUSS MA-6.29|Suss MA6]]
#**[[Stepper Recipes|Stepper Recipes]]
#***[[Stepper Recipes#Stepper 1 .28GCA 6300.29|Stepper #1: GCA 6300]] (I-Line)
#***[[Stepper Recipes#Stepper 2 .28AutoStep 200.29|Stepper #2: GCA Autostep 200]] (I-Line)
#***[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Stepper #3: ASML PAS 5500/300]] (DUV)
#**[[Direct-Write Lithography Recipes|Direct-Write Recipes]]
#***[[Direct-Write Lithography Recipes#Maskless Aligner .28Heidelberg MLA150.29|Heidelberg MLA150]]
#***[[Lithography Recipes#E-Beam Lithography Recipes|JEOL JBX-6300FS EBL]]
#***[[Lithography Recipes#FIB Lithography Recipes .28Raith Velion.29|Raith Velion FIB]]
#**[[Lithography Recipes#Automated Coat.2FDevelop System Recipes .28S-Cubed Flexi.29|Automated Coater Recipes (S-Cubed Flexi)]]
#[[Lithography Recipes#General Photolithography Techniques|'''General Photolithography Techniques''']]
#*''Techniques for improving litho. or solving common photolith. problems.''
#'''[[Lithography Recipes#Lift-Off Recipes|Lift-Off Recipes]]'''
#*''Verified Recipes for lift-off using various photolith. tools''
#*''General educational description of this technique and it's limitations/considerations.''
#'''E-beam Lithography'''
#*[[#E-Beam_Lithography_Recipes |E-Beam Lithography Recipes]]
#**''Has links to starting recipes. Substrates and patterns play a large role in process parameters.''
#*[[#EBLPR |EBL Photoresist Datasheets]]
#**''Provided for reference, also showing starting recipes and usage info.''
#'''[[Lithography Recipes#Holography Recipes|Holography]]'''
#*''For 1-D and 2-D gratings with 220nm nominal period, available on substrates up to 1 inch square.''
#*''Recipes for silicon substrates are provided, and have been translated to other substrates by users.''
#*''Datasheets are provided with starting recipes and usage info.''
#'''[[Lithography Recipes#Edge-Bead Removal Techniques|Edge-Bead Removal]]'''
#*''Edge photoresist removal methods needed for clamp-based etchers''
#*''Improves resolution for contact lithography''
|-
|

==='''<big>Photolithography Chemicals/Materials</big>'''===

#'''[[#Underlayers |Underlayers]]'''
#*''These are used beneath resists for both adhesive purposes and to enable bi-layer lift-off profiles for use with photoresist.''
#*''Datasheets are provided.''
#'''[[#AntiReflectionCoatings |Anti-Reflection Coatings]]''':
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Bottom Anti-Reflection Coatings (BARC) are used in the stepper systems, underneath the resists to eliminate substrate reflections that can affect resolution and repeatability for small, near resolution limited, feature sizes.''
#*''Datasheets are provided for reference on use of the materials.''
#'''[[#ContrastEnhancement |Contrast Enhancement Materials (CEM)]]'''
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Used for resolution enhancement. Not for use in contact aligners, typically used on I-Line Steppers.''
#*''Datasheets provided with usage info.''
#'''[[#AdhesionPromoters |Adhesion Promoters]]'''
#*''These are used to improve wetting of photoresists to your substrate.''
#*''Datasheets are provided on use of these materials.''
#'''[[#SpinOnDielectrics |Low-K Spin-on Dielectrics]]'''
#*[[Lithography Recipes#SpinOnDielectrics|Spin-On Dielectrics]]
#**''Datasheets for BCB, Photo-BCB, and SOG (spin-on-glass) for reference on use.''
#*[[#Low-K_Spin-On_Dielectric_Recipes |Low-K Spin-On Dielectric Recipes]]
#**''Recipes for usage of some spin-on dielectrics.''
#'''[[#Developers |Developers and Removers]]'''
#*''Datasheets provided for reference.''
#*''Remover and Photoresist Strippers are used to dissolve PR during lift-off or after etching.''
|}

==General Photolithography Techniques==

====[[Photolithography - Improving Adhesion Photoresist Adhesion|'''HMDS Process for Improving Adhesion''']]====

*''Use these procedures if you are finding poor adhesion PR lifting-off), or for chemicals (like BHF) that attack the PR adhesion interface strongly.''

====[[Photolithography - Manual Edge-Bead Removal Techniques|'''Edge-Bead Removal Techniques''']]====

*''These techniques are required for loading full-wafers into etchers that use top-side clamps, to prevent photoresist from sticking to the clamp (and potentially destroying your wafer).''
*''For contact lithography, this improves the proximity of the mask plate and sample, improving resolution. For some projection systems, such as the [[Maskless Aligner (Heidelberg MLA150)|Maskless Aligner]], EBR can help with autofocus issues.''

====[https://www.microchemicals.com/technical_information/reflow_photoresist.pdf '''Photoresist reflow (MicroChem)''']====

*''To create slanted sidewalls or curved surfaces.''

==Photolithography Recipes==

*'''R''': ''Recipe is available. Clicking this link will take you to the recipe.''
*'''A''': ''Material is available for use, but no recipes are provided.''

''Click the tool title to go to recipes for that tool.''

''Click the photoresist title to get the datasheet, also found in [[Lithography Recipes#Chemicals Stocked .2B Datasheets|Stocked Chemicals + Datasheets]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|-
! colspan="7" height="45" |<div style="font-size: 150%;">Photolithography Recipes</div>

|-
| bgcolor="#EAECF0" |
! colspan="2" align="center" |'''[[Contact Alignment Recipes|<big>Contact Aligner Recipes</big>]]'''
! colspan="3" align="center" |'''[[Stepper Recipes|<big>Stepper Recipes</big>]]'''
! align="center" |[[Direct-Write Lithography Recipes|Direct-Write Litho. Recipes]]
|-
! width="150" bgcolor="#D0E7FF" align="center" |'''Positive Resists'''
{{LithRecipe Table}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[[:File:AXP4000pb-Datasheet.pdf|AZ4110]]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4210]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4330RS]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/a2/Az_p4620_photoresist_data_package.pdf AZ4620]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/8b/OCG825-Positive-Resist-Datasheet.pdf OCG 825-35CS]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-0.9]
|A
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-1.8]
|A
|A
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-3.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-7.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive_Resist_.28MLA150.29}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/be/3600_D%2C_D2v_Spin_Speed_Curve.pdf THMR-IP3600 HP D]
|
|
|A
|A
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/ff/UV210-Positive-Resist-Datasheet.pdf UV210-0.3]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/UV26-Positive-Resist-Datasheet.pdf UV26-2.5]
|
|
|
|
|A
|
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Negative Resists'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/b0/AZ5214-Negative-Resist-Datasheet.pdf AZ5214-EIR]
|{{rl|Contact_Alignment_Recipes|Negative Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2020]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2035]
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |
| bgcolor="EEFFFF" |A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2070]
|A
|A
|A
|A
|
|A
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/82/AZnLOF5510-Negative-Resist-Datasheet.pdf AZnLOF 5510]
|A
|A
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/c/c9/UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf UVN30-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Negative Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/7/78/SU-8-2015-revA.pdf SU-8 2005,2010,2015]
|A
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/2c/SU-8-2075-revA.pdf SU-8 2075]
|A
|A
|A
|A
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |NR9-[//wiki.nanotech.ucsb.edu/w/images/8/8f/NR9-1000PY-revA.pdf 1000],[//wiki.nanotech.ucsb.edu/w/images/7/71/NR9-3000PY-revA.pdf 3000],[//wiki.nanotech.ucsb.edu/w/images/f/f9/NR9-6000PY-revA.pdf 6000]PY
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Anti-Reflection Coatings'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/33/XHRiC-Anti-Reflective-Coating.pdf XHRiC-11]
|
|
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/DUV42P-Anti-Reflective-Coating.pdf DUV42-P]
|
|
|
|
|{{rl|Stepper Recipes|DUV-42P-6}}
|
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101-304]
|
|
|
|
|{{rl|Stepper Recipes|DS-K101-304}}
|
|-
! bgcolor="#D0E7FF" align="center" |
{{LithRecipe Table}}
|}


==Lift-Off Recipes==

*{{fl|Liftoff-Techniques.pdf|Lift-Off Description/Tutorial}}
**How it works, process limits and considerations for designing your process
*[[Lift-Off with I-Line Imaging Resist + LOL2000 Underlayer|I-Line Lift-Off: Bi-Layer Process with LOL2000 Underlayer]]
**''Single Expose/Develop process for simplicity''
**''Up to ~130nm metal thickness & ≥500nm-1000nm gap between metal.''
**''Can use any I-Line litho tool (GCA Stepper, Contact aligner, MLA)''
*{{fl|Bi-LayerContactprocesswithPMGI.pdf|I-Line Lift-Off: Bi-Layer Process with PMGI Underlayer and Contact Aligner}}
**''Multiple processes for Metal thicknesses ~800nm to ~2.5µm''
**''Uses multiple DUV Flood exposure/develop cycles to create undercut.''
**''Can be transferred to other I-Line litho tools (Stepper, MLA etc.)''
*[[Lift-Off with DUV Imaging + PMGI Underlayer|DUV Lift-Off: UV6 Imaging Resist + PMGI Underlayer]]
**''Single-expose/develop process''
**''Up to ~65nm metal thickness & ~350nm gap between metal''
**''Use thicker PMGI for thicker metals''

==[[E-Beam Lithography System (JEOL JBX-6300FS)|E-Beam Lithography Recipes (JEOL JBX-6300FS)]]==

*Under Development.

==[[Focused Ion-Beam Lithography (Raith Velion)|FIB Lithography Recipes (Raith Velion)]]==
''To Be Added''

==[[Automated Coat/Develop System (S-Cubed Flexi)|Automated Coat/Develop System Recipes (S-Cubed Flexi)]]==
Recipes pre-loaded on the S-Cubed Flexi automated coat/bake/develop system. Only staff may write new recipes, contact the tool supervisor for more info.

===Available Variations===

*We have different recipes with varyious UV6 spin speeds - the same spin speed optionss as found on our manual Headway spinners. This allows for PR thickness control. See the linked UV6 datasheets below for thickness vs. rpm spin curves.
*DSK is recommended to be spun at 1.5krpm (~40nm) for best anti-reflection properties. 5krpm (~20nm) recipes are also provided for historical/legacy processes.
*DSK can be baked at either 220C to act as a Dry-etchable BARC (similar to DUV-42P), or at lower temps as a developable BARC (no dry etch required).
*"Chain" recipes (with DSK+UV6 spin/cured in succession) are only available for DSK Baked at 185C & 220C, and all UV6 Spin-speed variations. For the other DSK temps you can use the single-PR "Routes".

===Recipes Table (S-Cubed Flexi)===
{| class="wikitable"
|+''Ask [[Tony Bosch|Staff]] if you need a new recipe.''
|'''''Coating Material'''''
|'''''Route/Chain'''''
|'''''Name''': (User: "UCSB Users")''
|'''''Spin Speed (krpm)'''''
|'''''Bake Temp'''''
|'''''Notes'''''
|-
! colspan="6" |BEFORE LITHOGRAPHY (PR Coat and Bake)
|-
| colspan="6" |
|-
|'''''Hotplate Set'''''
|''Route''
| colspan="4" |To pre-set the DSK Hotplate temp (HP4).
Note: Only HP4 can be changed. HP1-HP3 remains fixed. HP1=135°C, HP2=170°C & HP3=170°C
|-
|
|
|HP4-SET-220C
|
|220°C
|''Will over shoot +-2°C when done.''
|-
|
|
|HP4-SET-210C
|
|210°C
|
|-
|
|
|HP4-SET-200C
|
|200°C
|
|-
|
|
|HP4-SET-185C
|
|185*C
|
|-
| colspan="6" |
|-
|'''''[https://wiki.nanotech.ucsb.edu/wiki/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101]'''''
|''Route''
| colspan="4" |''DSK101 Develop Rate depends on Bake temp - you can use this to control undercut.'' ''See: [[DS-K101-304 Bake Temp. versus Develop Rate|DSK Bake vs. Dev rate]]''
DSK101 spun at 1.5K is equivalent to DUV-42P. See: [[Stepper Recipes#Anti-Reflective Coatings]]

'''Note: All PR coat recipes have EBR backside clean steps included in the recipe.'''
|-
|1.5krpm recipes
|
|COAT-DSK101-304[1.5K]-185C
|1.5
|185°C
|''Requires: HP4=185°C,''
|-
|
|
|COAT-DSK101-304[1.5K]-200C
|1.5
|200°C
|''Requires: HP4=200°C''
|-
|
|
|COAT-DSK101-304[1.5K]-210C
|1.5
|210°C
|''Requires: HP4=210°C''
|-
|
|
|COAT-DSK101-304[1.5K]-220C
|1.5
|220°C
|''Requires: HP4=220°C,''
|-
| colspan="6" |
|-
|5krpm recipes
|
|COAT-DSK101-304[5K]-185C
|5.0
|185°C
|''Requires: HP4=185°C,''
|-
|
|
|COAT-DSK101-304[5K]-200C
|5.0
|200°C
|''Requires: HP4=200°C''
|-
|
|
|COAT-DSK101-304[5K]-210C
|5.0
|210°C
|''Requires: HP4=210°C''
|-
|
|
|COAT-DSK101-304[5K]-220C
|5.0
|220°C
|''Requires: HP4=220°C,''
|-
| colspan="6" |
|-
|'''''[https://wiki.nanofab.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]'''''
|''Route''
|COAT-UV6[2K]-135C
|2.0
|135°C
|''Requires: HP1=135°C''
|-
|varying spin speed
|
|COAT-UV6[2.5K]-135C
|2.5
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[3K]-135C
|3.0
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[3.5K]-135C
|3.5
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[4K]-135C
|4.0
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[5K]-135C
|5.0
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[6K]-135C
|6.0
|135°C
|''Requires: HP1=135°C''
|-
| colspan="6" |'''''Developable BARC underlayer:'''''
|-
|'''''DS-K101 @ 185°C'''''
'''''+ UV6'''''
|''Chain''
|COAT-DSK101[1.5K]-185C-UV6[2K]-135C
|''DSK: 1.5krpm''
''UV6: 2.0krpm''
|DSK: 185°C
UV6: 135°C
|''Requires:''
''– HP4=185°C''

''– HP1=135°C''

''Plan for ~10-15 min per wafer.''
|-
|''1.5krpm DSK recipes with''
''UV6- varyious spin speeds''
|
|COAT-DSK101[1.5K]-185C-UV6[2.5K]-135C
|''DSK: 1.5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3K]-135C
|''DSK: 1.5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3.5K]-135C
|''DSK: 1.5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[4K]-135C
|''DSK: 1.5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[5K]-135C
|''DSK: 1.5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[6K]-135C
|''DSK: 1.5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
| colspan="6" |
|-
|''5krpm DSK recipes with''
''UV6- various spin speeds''
|
|COAT-DSK101[5K]-185C-UV6[2K]-135C
|''DSK: 5krpm''
''UV6: 2.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[2.5K]-135C
|''DSK: 5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3K]-135C
|''DSK: 5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3.5K]-135C
|''DSK: 5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[4K]-135C
|''DSK: 5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[5K]-135C
|''DSK: 5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[6K]-135C
|''DSK: 5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
| colspan="6" |'''Dry-Etchable BARC underlayer:'''
|-
|'''''DS-K101 @ 220°C'''''
'''''+ UV6'''''
|''Chain''
|COAT-DSK101[1.5K]-220C-UV6[2K]-135C
|''DSK: 1.5krpm''
''UV6: 2.0krpm''
|DSK: 220°C
UV6: 135°C
|''Requires:''
''– HP4=220°C''

''– HP1=135°C''

''Plan for ~10-15 min per wafer.''
|-
|''1.5krpm DSK recipes with''
''UV6- varyious spin speeds''
|
|COAT-DSK101[1.5K]-220C-UV6[2.5K]-135C
|''DSK: 1.5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3K]-135C
|''DSK: 1.5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3.5K]-135C
|''DSK: 1.5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[4K]-135C
|''DSK: 1.5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[5K]-135C
|''DSK: 1.5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[6K]-135C
|''DSK: 1.5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
|
|
|
|
|
|
|-
|''5krpm DSK recipes with''
''UV6- varyious spin speeds''
|
|COAT-DSK101[5K]-220C-UV6[2K]-135C
|''DSK: 5krpm''
''UV6: 2.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[2.5K]-135C
|''DSK: 5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3K]-135C
|''DSK: 5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3.5K]-135C
|''DSK: 5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[4K]-135C
|''DSK: 5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[5K]-135C
|''DSK: 5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[6K]-135C
|''DSK: 5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
| colspan="6" |
|-
! colspan="6" |AFTER LITHOGRAPHY (PEB and Developing)
|-
| colspan="6" |
|-
|'''''PEB Wafer Bake'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) for 90sec and cool for 15sec
|-
|
|
|BAKE-135C-90S
|
|135°C
|''Requires: HP1=135°C''
|-
| colspan="6" |
|-
|'''''PEB and Developing'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) 90sec, cool 15sec, develop using AZ300MIF and water rinse 60sec

WARNING: DONOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE
|-
|Varying developer time
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-10S
|Developer chuck: 300rpm
|135°C
|''Requires: HP1=135°C''
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-15S
|''same as above''
|''same as above''
|''same as above''
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-20S
|''same as above''
|''same as above''
|''same as above''
|-
| colspan="6" |
|-
|'''Developing'''
|Route
| colspan="4" |To only develop wafer using AZ300MIF and water rinse 60sec

WARNING: DONOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE
|-
|Varying developer time
|
|DEV[MIF300[-SPIN[300RPM]-10S
|Developer chuck: 300rpm
|135°C
|''Requires: HP1=135°C''
|-
|
|
|DEV[MIF300[-SPIN[300RPM]-15S
|''same as above''
|''same as above''
|''same as above''
|-
|
|
|DEV[MIF300[-SPIN[300RPM]-20S
|''same as above''
|''same as above''
|''same as above''
|-
|
|
|
|
|
|
|}
==[[Holographic Lith/PL Setup (Custom)|Holography Recipes]]==
''The Holography recipes here use the BARC layer XHRiC-11 & the high-res. I-Line photoresist THMR-IP3600HP-D.''

*{{fl|Holography_Process_for_1D-lines_and_2D-dots_%28ARC-11_%26_THMR-IP3600HP-D%29-updated-4-8-2021.pdf|Standard Holography Process - on SiO2 on Si}}
*{{fl|Holography-Process-Variation-revA.pdf|Holography Process Variations - Set-up Angle - Etching into SiO2 and Si}}
*{{fl|05-SiO2_Nano-structure_Etch.pdf|Etch SiO2 Nano-structure - Changing Side-wall Angle - Etching into Si with a different line-width}}
*{{fl|30-Redicing_Nanowire_Diameter_by_Thermal_Oxidation_and_Vapored_HF_Etch.pdf|Reduce SiO2 Nanowire Diameter - Thermal Oxidation - Vapor HF Etching}}

==Low-K Spin-On Dielectric Recipes==

*{{fl|Lithography-BCB-photo-lowk-dielectric-spinon-4024-40-revA.docx|Photo BCB (4024-40)}}
*{{fl|BCB-cyclotene-3000-revA.pdf|Standard BCB (3022-46)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|SOG (T512B)}}

==Chemicals Stocked + Datasheets==
''The following is a list of the lithography chemicals we stock in the lab, with links to the datasheets for each. The datasheets will often have important processing info such as spin-speed vs. thickness curves, typical process parameters, bake temps/times etc.''
{|
|- valign="top"
| width="400" |
;<div id="PositivePR"><big>Positive Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AXP4000pb-Datasheet.pdf|AZP4000 (AZ4110, AZ4210, AZ4330)}}
*{{Fl|Az_p4620_photoresist_data_package.pdf|AZ P4620}}
*{{fl|OCG825-Positive-Resist-Datasheet.pdf|OCG825}}
*{{fl|SPR220-Positive-Resist-Datasheet.pdf|SPR220 (SPR220-3, SPR220-7)}}
*{{fl|SPR955-Positive-Resist-Datasheet.pdf|SPR955CM (SPR955CM-0.9, SPR955CM-1.8)}}
*THMR-3600HP (Thin I-Line & Holography)
**{{fl|THMR_iP_3500_iP3600.pdf|Evaluation Results: THMR-3600HP}}
**{{fl|3600_D,_D2v_Spin_Speed_Curve.pdf|Spin Curves for THMR-3600HP}}
**{{fl|THMR-iP3600_HP_D_20140801_(B)_GHS_US.pdf|Safety Datasheet for THMR-3600HP}}

'''''DUV-248nm'''''

*{{fl|UV210-Positive-Resist-Datasheet.pdf|UV210-0.3}}
*{{fl|UV6-Positive-Resist-Datasheet.pdf|UV6-0.8}}
*{{fl|UV26-Positive-Resist-Datasheet.pdf|UV26-2.5}}

;<div id="NegativePR"><big>Negative Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AZ5214-Negative-Resist-Datasheet.pdf|AZ5214}}
*{{fl|AZnLOF5510-Negative-Resist-Datasheet.pdf|AZnLOF5510}}
*{{fl|AZnLOF2020-Negative-Resist-Datasheet.pdf|AZnLOF2000 (AZnLOF2020, AZnLOF2035, AZnLOF2070)}}
*{{fl|NR9-1000PY-revA.pdf|Futurrex NR9-1000PY(use AZ300MIF dev)}}
*{{fl|NR9-3000PY-revA.pdf|Futurrex NR9-3000PY(use AZ300MIF dev)}}
*{{fl|NR9-6000PY-revA.pdf|Futurrex NR9-6000PY(use AZ300MIF dev)}}
*{{fl|SU-8-2015-revA.pdf|SU-8-2005,2010, 2015}}
*{{fl|SU-8-2075-revA.pdf|SU-8-2075}}

'''''DUV-248nm'''''

*{{fl|UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf|UVN-30-0.8}}

;<div id="Underlayers"><big>Underlayers</big></div>

*{{fl|PMGI-Underlayer-Datasheet.pdf|PMGI (PMGI SF3,5,8,11,15)}}
*{{fl|LOL2000-Underlayer-Datasheet.pdf|Shipley LOL2000}}

;<div id="EBLPR"><big>E-beam resists</big></div>

*{{fl|PMMA-E-Beam-Resist-Datasheet.pdf|PMMA (PMMA, P(MMA-MAA) copolymer)}}
*{{fl|maN2403-E-Beam-Resist-Datasheet.pdf|maN 2403}}

;<div id="NanoImprinting"><big>Nanoimprinting</big></div>

*{{fl|NX1020-Nanoimprinting-Datasheet.pdf|NX1020}}
*{{fl|MRI-7020-Nanoimprinting-Datasheet.pdf|MRI-7020}}
*{{fl|Mr-UVCur21.pdf|MR-UVCur21}}
*{{fl|OrmoStamp-NIL-Lithography-UV-Soft-RevA.pdf|Ormostamp}}

|
;<div id="ContrastEnhancement"><big>Contrast Enhancement Materials</big></div>

*{{fl|CEM365iS-Contrast-Enhancement-Datasheet.pdf|CEM365iS}}

;<div id="AntiReflectionCoatings"><big>Anti-Reflection Coatings</big></div>

*{{fl|XHRiC-Anti-Reflective-Coating.pdf|XHRiC-11 (i-line)}}
*{{fl|DUV42P-Anti-Reflective-Coating.pdf|DUV42P-6 (DUV) (For AR2 replacement)}}
*{{fl|DS-K101-304-Anti-Reflective-Coating.pdf|DS-K101-304 (DUV developable BARC)}}

;<div id="AdhesionPromoters"><big>Adhesion Promoters</big></div>

*HMDS
*AP3000 BCB Adhesion Promoter
*{{fl|OMNICOAT-revA.pdf|Omnicoat, SU-8 Adhesion Promoter}}
*{{fl|OrmoPrime-NIL-Adhesion-RevA.pdf|Ormoprime08-Ormostsmp Adhesion Promoter}}

;<div id="SpinOnDielectrics"><big>Spin-On Dielectrics</big></div>

''Low-K Spin-On Dielectrics such as Benzocyclobutane and Spin-on Glass''

*{{fl|BCB-cyclotene-3000-revA.pdf|BCB, Cyclotene 3022-46(Not Photosensitive)}}
*{{fl|BCB-cyclotene-4000-revA.pdf|PhotoBCB, Cyclotene 4022-40(Negative Polarity)}}
*{{fl|BCB-adhesion.pdf|BCB Adhesion Notes from Vendor}}
*{{fl|BCB-rework.pdf|BCB rework Notes from Vendor}}
*{{fl|512B-Datasheet-revA.pdf|Spin-on-Glass, Honeywell 512B (Not Photosensitive)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|Honeywell 512B Apps Data}}

;<div id="Developers"><big>Developers</big></div>

*{{fl|AZ400K-Developer-Datasheet.pdf|AZ400K (AZ400K, AZ400K1:4)}}
*{{fl|AZ300MIF-Developer-Datasheet.pdf|AZ300MIF}}
*DS2100 BCB Developer
*SU-8 Developer
*101A Developer (for DUV Flood Exposed PMGI)

;<div id="PRRemovers"><big>Photoresist Removers</big></div>

*[http://www.microchemicals.com/products/remover_stripper/nmp.html AZ NMP]
**''This replaces {{fl|1165-Resist-Remover.pdf|1165}}''
*{{fl|AZ300T-Resist-Remover.pdf|AZ300T}}
*{{fl|RemoverPG-revA.pdf|Remover PG, SU-8 stripper}}
*AZ EBR ("Edge Bead Remover", PGMEA)

|}

[[Category: Processing]]
[[category: Lithography]]
[[category: Recipes]]

Lithography Recipes

2024-07-11T15:33:36Z

Gopimeena: /* Recipes Table (S-Cubed Flexi) */

__NOTOC__
{| class="wikitable"
|+
!Table of Contents
|-
|
==='''<big>Photolithography Processes</big>'''===

#'''UV Optical Lithography'''
#*[[#PositivePR |'''Stocked Lithography Chemical + Datasheets''']]
#**''Lists all stocked photolith. chemicals, PRs, strippers, developers, and links to the chemical's application notes/datasheet, which detail the spin curves and nominal processes.''
#*[[#Photolithography_Recipes |'''Photo Lithography Recipe section''']]
#**''Starting recipes (spin, bake, exposure, develop etc.) for all photolith. tools.''
#**''Substrate/surface materials/pattern size can affect process parameters. Users may need to run Focus/Exposure Arrays/Matrix (FEA's/FEM's) with these processes to achieve high-resolution.''
#**[[Contact Alignment Recipes|Contact Aligner Recipes]]
#***[[Contact Alignment Recipes#Suss Aligners .28SUSS MJB-3.29|Suss MJB Aligners]]
#***[[Contact Alignment Recipes#Contact Aligner .28SUSS MA-6.29|Suss MA6]]
#**[[Stepper Recipes|Stepper Recipes]]
#***[[Stepper Recipes#Stepper 1 .28GCA 6300.29|Stepper #1: GCA 6300]] (I-Line)
#***[[Stepper Recipes#Stepper 2 .28AutoStep 200.29|Stepper #2: GCA Autostep 200]] (I-Line)
#***[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Stepper #3: ASML PAS 5500/300]] (DUV)
#**[[Direct-Write Lithography Recipes|Direct-Write Recipes]]
#***[[Direct-Write Lithography Recipes#Maskless Aligner .28Heidelberg MLA150.29|Heidelberg MLA150]]
#***[[Lithography Recipes#E-Beam Lithography Recipes|JEOL JBX-6300FS EBL]]
#***[[Lithography Recipes#FIB Lithography Recipes .28Raith Velion.29|Raith Velion FIB]]
#**[[Lithography Recipes#Automated Coat.2FDevelop System Recipes .28S-Cubed Flexi.29|Automated Coater Recipes (S-Cubed Flexi)]]
#[[Lithography Recipes#General Photolithography Techniques|'''General Photolithography Techniques''']]
#*''Techniques for improving litho. or solving common photolith. problems.''
#'''[[Lithography Recipes#Lift-Off Recipes|Lift-Off Recipes]]'''
#*''Verified Recipes for lift-off using various photolith. tools''
#*''General educational description of this technique and it's limitations/considerations.''
#'''E-beam Lithography'''
#*[[#E-Beam_Lithography_Recipes |E-Beam Lithography Recipes]]
#**''Has links to starting recipes. Substrates and patterns play a large role in process parameters.''
#*[[#EBLPR |EBL Photoresist Datasheets]]
#**''Provided for reference, also showing starting recipes and usage info.''
#'''[[Lithography Recipes#Holography Recipes|Holography]]'''
#*''For 1-D and 2-D gratings with 220nm nominal period, available on substrates up to 1 inch square.''
#*''Recipes for silicon substrates are provided, and have been translated to other substrates by users.''
#*''Datasheets are provided with starting recipes and usage info.''
#'''[[Lithography Recipes#Edge-Bead Removal Techniques|Edge-Bead Removal]]'''
#*''Edge photoresist removal methods needed for clamp-based etchers''
#*''Improves resolution for contact lithography''
|-
|

==='''<big>Photolithography Chemicals/Materials</big>'''===

#'''[[#Underlayers |Underlayers]]'''
#*''These are used beneath resists for both adhesive purposes and to enable bi-layer lift-off profiles for use with photoresist.''
#*''Datasheets are provided.''
#'''[[#AntiReflectionCoatings |Anti-Reflection Coatings]]''':
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Bottom Anti-Reflection Coatings (BARC) are used in the stepper systems, underneath the resists to eliminate substrate reflections that can affect resolution and repeatability for small, near resolution limited, feature sizes.''
#*''Datasheets are provided for reference on use of the materials.''
#'''[[#ContrastEnhancement |Contrast Enhancement Materials (CEM)]]'''
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Used for resolution enhancement. Not for use in contact aligners, typically used on I-Line Steppers.''
#*''Datasheets provided with usage info.''
#'''[[#AdhesionPromoters |Adhesion Promoters]]'''
#*''These are used to improve wetting of photoresists to your substrate.''
#*''Datasheets are provided on use of these materials.''
#'''[[#SpinOnDielectrics |Low-K Spin-on Dielectrics]]'''
#*[[Lithography Recipes#SpinOnDielectrics|Spin-On Dielectrics]]
#**''Datasheets for BCB, Photo-BCB, and SOG (spin-on-glass) for reference on use.''
#*[[#Low-K_Spin-On_Dielectric_Recipes |Low-K Spin-On Dielectric Recipes]]
#**''Recipes for usage of some spin-on dielectrics.''
#'''[[#Developers |Developers and Removers]]'''
#*''Datasheets provided for reference.''
#*''Remover and Photoresist Strippers are used to dissolve PR during lift-off or after etching.''
|}

==General Photolithography Techniques==

====[[Photolithography - Improving Adhesion Photoresist Adhesion|'''HMDS Process for Improving Adhesion''']]====

*''Use these procedures if you are finding poor adhesion PR lifting-off), or for chemicals (like BHF) that attack the PR adhesion interface strongly.''

====[[Photolithography - Manual Edge-Bead Removal Techniques|'''Edge-Bead Removal Techniques''']]====

*''These techniques are required for loading full-wafers into etchers that use top-side clamps, to prevent photoresist from sticking to the clamp (and potentially destroying your wafer).''
*''For contact lithography, this improves the proximity of the mask plate and sample, improving resolution. For some projection systems, such as the [[Maskless Aligner (Heidelberg MLA150)|Maskless Aligner]], EBR can help with autofocus issues.''

====[https://www.microchemicals.com/technical_information/reflow_photoresist.pdf '''Photoresist reflow (MicroChem)''']====

*''To create slanted sidewalls or curved surfaces.''

==Photolithography Recipes==

*'''R''': ''Recipe is available. Clicking this link will take you to the recipe.''
*'''A''': ''Material is available for use, but no recipes are provided.''

''Click the tool title to go to recipes for that tool.''

''Click the photoresist title to get the datasheet, also found in [[Lithography Recipes#Chemicals Stocked .2B Datasheets|Stocked Chemicals + Datasheets]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|-
! colspan="7" height="45" |<div style="font-size: 150%;">Photolithography Recipes</div>

|-
| bgcolor="#EAECF0" |
! colspan="2" align="center" |'''[[Contact Alignment Recipes|<big>Contact Aligner Recipes</big>]]'''
! colspan="3" align="center" |'''[[Stepper Recipes|<big>Stepper Recipes</big>]]'''
! align="center" |[[Direct-Write Lithography Recipes|Direct-Write Litho. Recipes]]
|-
! width="150" bgcolor="#D0E7FF" align="center" |'''Positive Resists'''
{{LithRecipe Table}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[[:File:AXP4000pb-Datasheet.pdf|AZ4110]]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4210]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4330RS]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/a2/Az_p4620_photoresist_data_package.pdf AZ4620]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/8b/OCG825-Positive-Resist-Datasheet.pdf OCG 825-35CS]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-0.9]
|A
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-1.8]
|A
|A
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-3.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-7.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive_Resist_.28MLA150.29}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/be/3600_D%2C_D2v_Spin_Speed_Curve.pdf THMR-IP3600 HP D]
|
|
|A
|A
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/ff/UV210-Positive-Resist-Datasheet.pdf UV210-0.3]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/UV26-Positive-Resist-Datasheet.pdf UV26-2.5]
|
|
|
|
|A
|
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Negative Resists'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/b0/AZ5214-Negative-Resist-Datasheet.pdf AZ5214-EIR]
|{{rl|Contact_Alignment_Recipes|Negative Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2020]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2035]
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |
| bgcolor="EEFFFF" |A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2070]
|A
|A
|A
|A
|
|A
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/82/AZnLOF5510-Negative-Resist-Datasheet.pdf AZnLOF 5510]
|A
|A
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/c/c9/UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf UVN30-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Negative Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/7/78/SU-8-2015-revA.pdf SU-8 2005,2010,2015]
|A
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/2c/SU-8-2075-revA.pdf SU-8 2075]
|A
|A
|A
|A
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |NR9-[//wiki.nanotech.ucsb.edu/w/images/8/8f/NR9-1000PY-revA.pdf 1000],[//wiki.nanotech.ucsb.edu/w/images/7/71/NR9-3000PY-revA.pdf 3000],[//wiki.nanotech.ucsb.edu/w/images/f/f9/NR9-6000PY-revA.pdf 6000]PY
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Anti-Reflection Coatings'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/33/XHRiC-Anti-Reflective-Coating.pdf XHRiC-11]
|
|
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/DUV42P-Anti-Reflective-Coating.pdf DUV42-P]
|
|
|
|
|{{rl|Stepper Recipes|DUV-42P-6}}
|
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101-304]
|
|
|
|
|{{rl|Stepper Recipes|DS-K101-304}}
|
|-
! bgcolor="#D0E7FF" align="center" |
{{LithRecipe Table}}
|}


==Lift-Off Recipes==

*{{fl|Liftoff-Techniques.pdf|Lift-Off Description/Tutorial}}
**How it works, process limits and considerations for designing your process
*[[Lift-Off with I-Line Imaging Resist + LOL2000 Underlayer|I-Line Lift-Off: Bi-Layer Process with LOL2000 Underlayer]]
**''Single Expose/Develop process for simplicity''
**''Up to ~130nm metal thickness & ≥500nm-1000nm gap between metal.''
**''Can use any I-Line litho tool (GCA Stepper, Contact aligner, MLA)''
*{{fl|Bi-LayerContactprocesswithPMGI.pdf|I-Line Lift-Off: Bi-Layer Process with PMGI Underlayer and Contact Aligner}}
**''Multiple processes for Metal thicknesses ~800nm to ~2.5µm''
**''Uses multiple DUV Flood exposure/develop cycles to create undercut.''
**''Can be transferred to other I-Line litho tools (Stepper, MLA etc.)''
*[[Lift-Off with DUV Imaging + PMGI Underlayer|DUV Lift-Off: UV6 Imaging Resist + PMGI Underlayer]]
**''Single-expose/develop process''
**''Up to ~65nm metal thickness & ~350nm gap between metal''
**''Use thicker PMGI for thicker metals''

==[[E-Beam Lithography System (JEOL JBX-6300FS)|E-Beam Lithography Recipes (JEOL JBX-6300FS)]]==

*Under Development.

==[[Focused Ion-Beam Lithography (Raith Velion)|FIB Lithography Recipes (Raith Velion)]]==
''To Be Added''

==[[Automated Coat/Develop System (S-Cubed Flexi)|Automated Coat/Develop System Recipes (S-Cubed Flexi)]]==
Recipes pre-loaded on the S-Cubed Flexi automated coat/bake/develop system. Only staff may write new recipes, contact the tool supervisor for more info.

===Available Variations===

*We have different recipes with varyious UV6 spin speeds - the same spin speed optionss as found on our manual Headway spinners. This allows for PR thickness control. See the linked UV6 datasheets below for thickness vs. rpm spin curves.
*DSK is recommended to be spun at 1.5krpm (~40nm) for best anti-reflection properties. 5krpm (~20nm) recipes are also provided for historical/legacy processes.
*DSK can be baked at either 220C to act as a Dry-etchable BARC (similar to DUV-42P), or at lower temps as a developable BARC (no dry etch required).
*"Chain" recipes (with DSK+UV6 spin/cured in succession) are only available for DSK Baked at 185C & 220C, and all UV6 Spin-speed variations. For the other DSK temps you can use the single-PR "Routes".

===Recipes Table (S-Cubed Flexi)===
{| class="wikitable"
|+''Ask [[Tony Bosch|Staff]] if you need a new recipe.''
|'''''Coating Material'''''
|'''''Route/Chain'''''
|'''''Name''': (User: "UCSB Users")''
|'''''Spin Speed (krpm)'''''
|'''''Bake Temp'''''
|'''''Notes'''''
|-
|'''''Hotplate Set'''''
|''Route''
| colspan="4" |To pre-set the DSK Hotplate temp (HP4).
Note: Only HP4 can be changed. HP1-HP3 remains fixed. HP1=135°C, HP2=170°C & HP3=170°C
|-
|
|
|HP4-SET-220C
|
|220°C
|''Will over shoot +-2°C when done.''
|-
|
|
|HP4-SET-210C
|
|210°C
|
|-
|
|
|HP4-SET-200C
|
|200°C
|
|-
|
|
|HP4-SET-185C
|
|185*C
|
|-
| colspan="6" |
|-
|'''''[https://wiki.nanotech.ucsb.edu/wiki/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101]'''''
|''Route''
| colspan="4" |''DSK101 Develop Rate depends on Bake temp - you can use this to control undercut.'' ''See: [[DS-K101-304 Bake Temp. versus Develop Rate|DSK Bake vs. Dev rate]]''
DSK101 spun at 1.5K is equivalent to DUV-42P. See: [[Stepper Recipes#Anti-Reflective Coatings]]
|-
|1.5krpm recipes
|
|COAT-DSK101-304[1.5K]-185C
|1.5
|185°C
|''Requires: HP4=185°C,''
|-
|
|
|COAT-DSK101-304[1.5K]-200C
|1.5
|200°C
|''Requires: HP4=200°C''
|-
|
|
|COAT-DSK101-304[1.5K]-210C
|1.5
|210°C
|''Requires: HP4=210°C''
|-
|
|
|COAT-DSK101-304[1.5K]-220C
|1.5
|220°C
|''Requires: HP4=220°C,''
|-
| colspan="6" |
|-
|5krpm recipes
|
|COAT-DSK101-304[5K]-185C
|5.0
|185°C
|''Requires: HP4=185°C,''
|-
|
|
|COAT-DSK101-304[5K]-200C
|5.0
|200°C
|''Requires: HP4=200°C''
|-
|
|
|COAT-DSK101-304[5K]-210C
|5.0
|210°C
|''Requires: HP4=210°C''
|-
|
|
|COAT-DSK101-304[5K]-220C
|5.0
|220°C
|''Requires: HP4=220°C,''
|-
| colspan="6" |
|-
|'''''[https://wiki.nanofab.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]'''''
|''Route''
|COAT-UV6[2K]-135C
|2.0
|135°C
|''Requires: HP1=135°C''
|-
|varying spin speed
|
|COAT-UV6[2.5K]-135C
|2.5
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[3K]-135C
|3.0
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[3.5K]-135C
|3.5
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[4K]-135C
|4.0
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[5K]-135C
|5.0
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[6K]-135C
|6.0
|135°C
|''Requires: HP1=135°C''
|-
| colspan="6" |
|-
|'''''DS-K101 @ 185°C'''''
'''''+ UV6'''''
|''Chain''
|COAT-DSK101[1.5K]-185C-UV6[2K]-135C
|''DSK: 1.5krpm''
''UV6: 2.0krpm''
|DSK: 185°C
UV6: 135°C
|''Requires:''
''– HP4=185°C''

''– HP1=135°C''

''Plan for ~10-15 min per wafer.''
|-
|1.5krpm DSK recipes with
UV6- varying spin speed
|
|COAT-DSK101[1.5K]-185C-UV6[2.5K]-135C
|''DSK: 1.5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3K]-135C
|''DSK: 1.5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3.5K]-135C
|''DSK: 1.5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[4K]-135C
|''DSK: 1.5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[5K]-135C
|''DSK: 1.5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[6K]-135C
|''DSK: 1.5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
| colspan="6" |
|-
|5krpm DSK recipes with
UV6- varying spin speed
|
|COAT-DSK101[5K]-185C-UV6[2K]-135C
|''DSK: 5krpm''
''UV6: 2.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[2.5K]-135C
|''DSK: 5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3K]-135C
|''DSK: 5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[3.5K]-135C
|''DSK: 5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[4K]-135C
|''DSK: 5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[5K]-135C
|''DSK: 5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-185C-UV6[6K]-135C
|''DSK: 5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
| colspan="6" |
|-
|'''''DS-K101 @ 220°C'''''
'''''+ UV6'''''
|''Chain''
|COAT-DSK101[1.5K]-220C-UV6[2K]-135C
|''DSK: 1.5krpm''
''UV6: 2.0krpm''
|DSK: 220°C
UV6: 135°C
|''Requires:''
''– HP4=220°C''

''– HP1=135°C''

''Plan for ~10-15 min per wafer.''
|-
|1.5krpm DSK recipes with
UV6- varying spin speed
|
|COAT-DSK101[1.5K]-220C-UV6[2.5K]-135C
|''DSK: 1.5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3K]-135C
|''DSK: 1.5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3.5K]-135C
|''DSK: 1.5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[4K]-135C
|''DSK: 1.5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[5K]-135C
|''DSK: 1.5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[6K]-135C
|''DSK: 1.5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
|
|
|
|
|
|
|-
|5krpm DSK recipes with
UV6- varying spin speed
|
|COAT-DSK101[5K]-220C-UV6[2K]-135C
|''DSK: 5krpm''
''UV6: 2.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[2.5K]-135C
|''DSK: 5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3K]-135C
|''DSK: 5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[3.5K]-135C
|''DSK: 5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[4K]-135C
|''DSK: 5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[5K]-135C
|''DSK: 5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[5K]-220C-UV6[6K]-135C
|''DSK: 5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
|
|
|
|
|
|
|-
|
|
|
|
|
|
|-
|
|
|
|
|
|
|-
|
|
|
|
|
|
|-
|
|
|
|
|
|
|-
|'''''Hotplate Set'''''
|''Route''
|''SET-HP4-220C''
|
|220°C
|''Hotplate 4 (top) between 218-222°C when done.''
|-
|To pre-set the DSK Hotplate temp.
|
|''SET-HP4-210C''
|
|210°C
|
|-
|
|
|''SET-HP4-200C''
|
|200°C
|
|-
|
|
|''SET-HP4-185C''
|
|185*C
|
|}
==[[Holographic Lith/PL Setup (Custom)|Holography Recipes]]==
''The Holography recipes here use the BARC layer XHRiC-11 & the high-res. I-Line photoresist THMR-IP3600HP-D.''

*{{fl|Holography_Process_for_1D-lines_and_2D-dots_%28ARC-11_%26_THMR-IP3600HP-D%29-updated-4-8-2021.pdf|Standard Holography Process - on SiO2 on Si}}
*{{fl|Holography-Process-Variation-revA.pdf|Holography Process Variations - Set-up Angle - Etching into SiO2 and Si}}
*{{fl|05-SiO2_Nano-structure_Etch.pdf|Etch SiO2 Nano-structure - Changing Side-wall Angle - Etching into Si with a different line-width}}
*{{fl|30-Redicing_Nanowire_Diameter_by_Thermal_Oxidation_and_Vapored_HF_Etch.pdf|Reduce SiO2 Nanowire Diameter - Thermal Oxidation - Vapor HF Etching}}

==Low-K Spin-On Dielectric Recipes==

*{{fl|Lithography-BCB-photo-lowk-dielectric-spinon-4024-40-revA.docx|Photo BCB (4024-40)}}
*{{fl|BCB-cyclotene-3000-revA.pdf|Standard BCB (3022-46)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|SOG (T512B)}}

==Chemicals Stocked + Datasheets==
''The following is a list of the lithography chemicals we stock in the lab, with links to the datasheets for each. The datasheets will often have important processing info such as spin-speed vs. thickness curves, typical process parameters, bake temps/times etc.''
{|
|- valign="top"
| width="400" |
;<div id="PositivePR"><big>Positive Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AXP4000pb-Datasheet.pdf|AZP4000 (AZ4110, AZ4210, AZ4330)}}
*{{Fl|Az_p4620_photoresist_data_package.pdf|AZ P4620}}
*{{fl|OCG825-Positive-Resist-Datasheet.pdf|OCG825}}
*{{fl|SPR220-Positive-Resist-Datasheet.pdf|SPR220 (SPR220-3, SPR220-7)}}
*{{fl|SPR955-Positive-Resist-Datasheet.pdf|SPR955CM (SPR955CM-0.9, SPR955CM-1.8)}}
*THMR-3600HP (Thin I-Line & Holography)
**{{fl|THMR_iP_3500_iP3600.pdf|Evaluation Results: THMR-3600HP}}
**{{fl|3600_D,_D2v_Spin_Speed_Curve.pdf|Spin Curves for THMR-3600HP}}
**{{fl|THMR-iP3600_HP_D_20140801_(B)_GHS_US.pdf|Safety Datasheet for THMR-3600HP}}

'''''DUV-248nm'''''

*{{fl|UV210-Positive-Resist-Datasheet.pdf|UV210-0.3}}
*{{fl|UV6-Positive-Resist-Datasheet.pdf|UV6-0.8}}
*{{fl|UV26-Positive-Resist-Datasheet.pdf|UV26-2.5}}

;<div id="NegativePR"><big>Negative Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AZ5214-Negative-Resist-Datasheet.pdf|AZ5214}}
*{{fl|AZnLOF5510-Negative-Resist-Datasheet.pdf|AZnLOF5510}}
*{{fl|AZnLOF2020-Negative-Resist-Datasheet.pdf|AZnLOF2000 (AZnLOF2020, AZnLOF2035, AZnLOF2070)}}
*{{fl|NR9-1000PY-revA.pdf|Futurrex NR9-1000PY(use AZ300MIF dev)}}
*{{fl|NR9-3000PY-revA.pdf|Futurrex NR9-3000PY(use AZ300MIF dev)}}
*{{fl|NR9-6000PY-revA.pdf|Futurrex NR9-6000PY(use AZ300MIF dev)}}
*{{fl|SU-8-2015-revA.pdf|SU-8-2005,2010, 2015}}
*{{fl|SU-8-2075-revA.pdf|SU-8-2075}}

'''''DUV-248nm'''''

*{{fl|UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf|UVN-30-0.8}}

;<div id="Underlayers"><big>Underlayers</big></div>

*{{fl|PMGI-Underlayer-Datasheet.pdf|PMGI (PMGI SF3,5,8,11,15)}}
*{{fl|LOL2000-Underlayer-Datasheet.pdf|Shipley LOL2000}}

;<div id="EBLPR"><big>E-beam resists</big></div>

*{{fl|PMMA-E-Beam-Resist-Datasheet.pdf|PMMA (PMMA, P(MMA-MAA) copolymer)}}
*{{fl|maN2403-E-Beam-Resist-Datasheet.pdf|maN 2403}}

;<div id="NanoImprinting"><big>Nanoimprinting</big></div>

*{{fl|NX1020-Nanoimprinting-Datasheet.pdf|NX1020}}
*{{fl|MRI-7020-Nanoimprinting-Datasheet.pdf|MRI-7020}}
*{{fl|Mr-UVCur21.pdf|MR-UVCur21}}
*{{fl|OrmoStamp-NIL-Lithography-UV-Soft-RevA.pdf|Ormostamp}}

|
;<div id="ContrastEnhancement"><big>Contrast Enhancement Materials</big></div>

*{{fl|CEM365iS-Contrast-Enhancement-Datasheet.pdf|CEM365iS}}

;<div id="AntiReflectionCoatings"><big>Anti-Reflection Coatings</big></div>

*{{fl|XHRiC-Anti-Reflective-Coating.pdf|XHRiC-11 (i-line)}}
*{{fl|DUV42P-Anti-Reflective-Coating.pdf|DUV42P-6 (DUV) (For AR2 replacement)}}
*{{fl|DS-K101-304-Anti-Reflective-Coating.pdf|DS-K101-304 (DUV developable BARC)}}

;<div id="AdhesionPromoters"><big>Adhesion Promoters</big></div>

*HMDS
*AP3000 BCB Adhesion Promoter
*{{fl|OMNICOAT-revA.pdf|Omnicoat, SU-8 Adhesion Promoter}}
*{{fl|OrmoPrime-NIL-Adhesion-RevA.pdf|Ormoprime08-Ormostsmp Adhesion Promoter}}

;<div id="SpinOnDielectrics"><big>Spin-On Dielectrics</big></div>

''Low-K Spin-On Dielectrics such as Benzocyclobutane and Spin-on Glass''

*{{fl|BCB-cyclotene-3000-revA.pdf|BCB, Cyclotene 3022-46(Not Photosensitive)}}
*{{fl|BCB-cyclotene-4000-revA.pdf|PhotoBCB, Cyclotene 4022-40(Negative Polarity)}}
*{{fl|BCB-adhesion.pdf|BCB Adhesion Notes from Vendor}}
*{{fl|BCB-rework.pdf|BCB rework Notes from Vendor}}
*{{fl|512B-Datasheet-revA.pdf|Spin-on-Glass, Honeywell 512B (Not Photosensitive)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|Honeywell 512B Apps Data}}

;<div id="Developers"><big>Developers</big></div>

*{{fl|AZ400K-Developer-Datasheet.pdf|AZ400K (AZ400K, AZ400K1:4)}}
*{{fl|AZ300MIF-Developer-Datasheet.pdf|AZ300MIF}}
*DS2100 BCB Developer
*SU-8 Developer
*101A Developer (for DUV Flood Exposed PMGI)

;<div id="PRRemovers"><big>Photoresist Removers</big></div>

*[http://www.microchemicals.com/products/remover_stripper/nmp.html AZ NMP]
**''This replaces {{fl|1165-Resist-Remover.pdf|1165}}''
*{{fl|AZ300T-Resist-Remover.pdf|AZ300T}}
*{{fl|RemoverPG-revA.pdf|Remover PG, SU-8 stripper}}
*AZ EBR ("Edge Bead Remover", PGMEA)

|}

[[Category: Processing]]
[[category: Lithography]]
[[category: Recipes]]

Lithography Recipes

2024-07-11T00:24:24Z

Gopimeena: /* Automated Coat/Develop System Recipes (S-Cubed Flexi) */

__NOTOC__
{| class="wikitable"
|+
!Table of Contents
|-
|
==='''<big>Photolithography Processes</big>'''===

#'''UV Optical Lithography'''
#*[[#PositivePR |'''Stocked Lithography Chemical + Datasheets''']]
#**''Lists all stocked photolith. chemicals, PRs, strippers, developers, and links to the chemical's application notes/datasheet, which detail the spin curves and nominal processes.''
#*[[#Photolithography_Recipes |'''Photo Lithography Recipe section''']]
#**''Starting recipes (spin, bake, exposure, develop etc.) for all photolith. tools.''
#**''Substrate/surface materials/pattern size can affect process parameters. Users may need to run Focus/Exposure Arrays/Matrix (FEA's/FEM's) with these processes to achieve high-resolution.''
#**[[Contact Alignment Recipes|Contact Aligner Recipes]]
#***[[Contact Alignment Recipes#Suss Aligners .28SUSS MJB-3.29|Suss MJB Aligners]]
#***[[Contact Alignment Recipes#Contact Aligner .28SUSS MA-6.29|Suss MA6]]
#**[[Stepper Recipes|Stepper Recipes]]
#***[[Stepper Recipes#Stepper 1 .28GCA 6300.29|Stepper #1: GCA 6300]] (I-Line)
#***[[Stepper Recipes#Stepper 2 .28AutoStep 200.29|Stepper #2: GCA Autostep 200]] (I-Line)
#***[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Stepper #3: ASML PAS 5500/300]] (DUV)
#**[[Direct-Write Lithography Recipes|Direct-Write Recipes]]
#***[[Direct-Write Lithography Recipes#Maskless Aligner .28Heidelberg MLA150.29|Heidelberg MLA150]]
#***[[Lithography Recipes#E-Beam Lithography Recipes|JEOL JBX-6300FS EBL]]
#***[[Lithography Recipes#FIB Lithography Recipes .28Raith Velion.29|Raith Velion FIB]]
#**[[Lithography Recipes#Automated Coat.2FDevelop System Recipes .28S-Cubed Flexi.29|Automated Coater Recipes (S-Cubed Flexi)]]
#[[Lithography Recipes#General Photolithography Techniques|'''General Photolithography Techniques''']]
#*''Techniques for improving litho. or solving common photolith. problems.''
#'''[[Lithography Recipes#Lift-Off Recipes|Lift-Off Recipes]]'''
#*''Verified Recipes for lift-off using various photolith. tools''
#*''General educational description of this technique and it's limitations/considerations.''
#'''E-beam Lithography'''
#*[[#E-Beam_Lithography_Recipes |E-Beam Lithography Recipes]]
#**''Has links to starting recipes. Substrates and patterns play a large role in process parameters.''
#*[[#EBLPR |EBL Photoresist Datasheets]]
#**''Provided for reference, also showing starting recipes and usage info.''
#'''[[Lithography Recipes#Holography Recipes|Holography]]'''
#*''For 1-D and 2-D gratings with 220nm nominal period, available on substrates up to 1 inch square.''
#*''Recipes for silicon substrates are provided, and have been translated to other substrates by users.''
#*''Datasheets are provided with starting recipes and usage info.''
#'''[[Lithography Recipes#Edge-Bead Removal Techniques|Edge-Bead Removal]]'''
#*''Edge photoresist removal methods needed for clamp-based etchers''
#*''Improves resolution for contact lithography''
|-
|

==='''<big>Photolithography Chemicals/Materials</big>'''===

#'''[[#Underlayers |Underlayers]]'''
#*''These are used beneath resists for both adhesive purposes and to enable bi-layer lift-off profiles for use with photoresist.''
#*''Datasheets are provided.''
#'''[[#AntiReflectionCoatings |Anti-Reflection Coatings]]''':
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Bottom Anti-Reflection Coatings (BARC) are used in the stepper systems, underneath the resists to eliminate substrate reflections that can affect resolution and repeatability for small, near resolution limited, feature sizes.''
#*''Datasheets are provided for reference on use of the materials.''
#'''[[#ContrastEnhancement |Contrast Enhancement Materials (CEM)]]'''
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Used for resolution enhancement. Not for use in contact aligners, typically used on I-Line Steppers.''
#*''Datasheets provided with usage info.''
#'''[[#AdhesionPromoters |Adhesion Promoters]]'''
#*''These are used to improve wetting of photoresists to your substrate.''
#*''Datasheets are provided on use of these materials.''
#'''[[#SpinOnDielectrics |Low-K Spin-on Dielectrics]]'''
#*[[Lithography Recipes#SpinOnDielectrics|Spin-On Dielectrics]]
#**''Datasheets for BCB, Photo-BCB, and SOG (spin-on-glass) for reference on use.''
#*[[#Low-K_Spin-On_Dielectric_Recipes |Low-K Spin-On Dielectric Recipes]]
#**''Recipes for usage of some spin-on dielectrics.''
#'''[[#Developers |Developers and Removers]]'''
#*''Datasheets provided for reference.''
#*''Remover and Photoresist Strippers are used to dissolve PR during lift-off or after etching.''
|}

==General Photolithography Techniques==

====[[Photolithography - Improving Adhesion Photoresist Adhesion|'''HMDS Process for Improving Adhesion''']]====

*''Use these procedures if you are finding poor adhesion PR lifting-off), or for chemicals (like BHF) that attack the PR adhesion interface strongly.''

====[[Photolithography - Manual Edge-Bead Removal Techniques|'''Edge-Bead Removal Techniques''']]====

*''These techniques are required for loading full-wafers into etchers that use top-side clamps, to prevent photoresist from sticking to the clamp (and potentially destroying your wafer).''
*''For contact lithography, this improves the proximity of the mask plate and sample, improving resolution. For some projection systems, such as the [[Maskless Aligner (Heidelberg MLA150)|Maskless Aligner]], EBR can help with autofocus issues.''

====[https://www.microchemicals.com/technical_information/reflow_photoresist.pdf '''Photoresist reflow (MicroChem)''']====

*''To create slanted sidewalls or curved surfaces.''

==Photolithography Recipes==

*'''R''': ''Recipe is available. Clicking this link will take you to the recipe.''
*'''A''': ''Material is available for use, but no recipes are provided.''

''Click the tool title to go to recipes for that tool.''

''Click the photoresist title to get the datasheet, also found in [[Lithography Recipes#Chemicals Stocked .2B Datasheets|Stocked Chemicals + Datasheets]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|-
! colspan="7" height="45" |<div style="font-size: 150%;">Photolithography Recipes</div>

|-
| bgcolor="#EAECF0" |
! colspan="2" align="center" |'''[[Contact Alignment Recipes|<big>Contact Aligner Recipes</big>]]'''
! colspan="3" align="center" |'''[[Stepper Recipes|<big>Stepper Recipes</big>]]'''
! align="center" |[[Direct-Write Lithography Recipes|Direct-Write Litho. Recipes]]
|-
! width="150" bgcolor="#D0E7FF" align="center" |'''Positive Resists'''
{{LithRecipe Table}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[[:File:AXP4000pb-Datasheet.pdf|AZ4110]]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4210]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4330RS]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/a2/Az_p4620_photoresist_data_package.pdf AZ4620]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/8b/OCG825-Positive-Resist-Datasheet.pdf OCG 825-35CS]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-0.9]
|A
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-1.8]
|A
|A
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-3.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-7.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Positive_Resist_.28MLA150.29}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/be/3600_D%2C_D2v_Spin_Speed_Curve.pdf THMR-IP3600 HP D]
|
|
|A
|A
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/ff/UV210-Positive-Resist-Datasheet.pdf UV210-0.3]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/UV26-Positive-Resist-Datasheet.pdf UV26-2.5]
|
|
|
|
|A
|
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Negative Resists'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/b0/AZ5214-Negative-Resist-Datasheet.pdf AZ5214-EIR]
|{{rl|Contact_Alignment_Recipes|Negative Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2020]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2035]
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |
| bgcolor="EEFFFF" |A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2070]
|A
|A
|A
|A
|
|A
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/82/AZnLOF5510-Negative-Resist-Datasheet.pdf AZnLOF 5510]
|A
|A
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/c/c9/UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf UVN30-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Negative Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/7/78/SU-8-2015-revA.pdf SU-8 2005,2010,2015]
|A
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/2c/SU-8-2075-revA.pdf SU-8 2075]
|A
|A
|A
|A
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |NR9-[//wiki.nanotech.ucsb.edu/w/images/8/8f/NR9-1000PY-revA.pdf 1000],[//wiki.nanotech.ucsb.edu/w/images/7/71/NR9-3000PY-revA.pdf 3000],[//wiki.nanotech.ucsb.edu/w/images/f/f9/NR9-6000PY-revA.pdf 6000]PY
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Anti-Reflection Coatings'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/33/XHRiC-Anti-Reflective-Coating.pdf XHRiC-11]
|
|
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/DUV42P-Anti-Reflective-Coating.pdf DUV42-P]
|
|
|
|
|{{rl|Stepper Recipes|DUV-42P-6}}
|
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101-304]
|
|
|
|
|{{rl|Stepper Recipes|DS-K101-304}}
|
|-
! bgcolor="#D0E7FF" align="center" |
{{LithRecipe Table}}
|}


==Lift-Off Recipes==

*{{fl|Liftoff-Techniques.pdf|Lift-Off Description/Tutorial}}
**How it works, process limits and considerations for designing your process
*[[Lift-Off with I-Line Imaging Resist + LOL2000 Underlayer|I-Line Lift-Off: Bi-Layer Process with LOL2000 Underlayer]]
**''Single Expose/Develop process for simplicity''
**''Up to ~130nm metal thickness & ≥500nm-1000nm gap between metal.''
**''Can use any I-Line litho tool (GCA Stepper, Contact aligner, MLA)''
*{{fl|Bi-LayerContactprocesswithPMGI.pdf|I-Line Lift-Off: Bi-Layer Process with PMGI Underlayer and Contact Aligner}}
**''Multiple processes for Metal thicknesses ~800nm to ~2.5µm''
**''Uses multiple DUV Flood exposure/develop cycles to create undercut.''
**''Can be transferred to other I-Line litho tools (Stepper, MLA etc.)''
*[[Lift-Off with DUV Imaging + PMGI Underlayer|DUV Lift-Off: UV6 Imaging Resist + PMGI Underlayer]]
**''Single-expose/develop process''
**''Up to ~65nm metal thickness & ~350nm gap between metal''
**''Use thicker PMGI for thicker metals''

==[[E-Beam Lithography System (JEOL JBX-6300FS)|E-Beam Lithography Recipes (JEOL JBX-6300FS)]]==

*Under Development.

==[[Focused Ion-Beam Lithography (Raith Velion)|FIB Lithography Recipes (Raith Velion)]]==
''To Be Added''

==[[Automated Coat/Develop System (S-Cubed Flexi)|Automated Coat/Develop System Recipes (S-Cubed Flexi)]]==
Recipes pre-loaded on the S-Cubed Flexi automated coat/bake/develop system. Only staff may write new recipes, contact the tool supervisor for more info.
{| class="wikitable"
|+''Ask [[Tony Bosch|Staff]] if you need a new recipe.''
|'''''Coating Material'''''
|'''''Route/Chain'''''
|'''''Name''': User: "UCSB Users"''
|'''''Spin Speed (krpm)'''''
|'''''Bake Temp'''''
|'''''Notes'''''
|-
|'''''[https://wiki.nanotech.ucsb.edu/wiki/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101]'''''
|''Route''
| colspan="4" |''DSK101 Develop Rate depends on Bake temp - you can use this to control undercut.'' ''See: [[DS-K101-304 Bake Temp. versus Develop Rate|DSK Bake vs. Dev rate]]''
DSK101 spun at 1.5K is equivalent to DUV-42P. See: [[Stepper Recipes#Anti-Reflective Coatings]]
|-
|
|
|COAT-DSK101-304[1.5K]-185C
|1.5
|185°C
|''Requires: HP4=185°C,''
|-
|
|
|COAT-DSK101-304[1.5K]-200C
|1.5
|200°C
|''Requires: HP4=200°C''
|-
|
|
|COAT-DSK101-304[1.5K]-210C
|1.5
|210°C
|''Requires: HP4=210°C''
|-
|
|
|COAT-DSK101-304[1.5K]-220C
|1.5
|220°C
|''Requires: HP4=220°C,''
|-
|
|
|COAT-DSK101-304[5K]-185C
|5.0
|185°C
|''Requires: HP4=185°C,''
|-
|
|
|COAT-DSK101-304[5K]-200C
|5.0
|200°C
|''Requires: HP4=200°C''
|-
|
|
|COAT-DSK101-304[5K]-210C
|5.0
|210°C
|''Requires: HP4=210°C''
|-
|
|
|COAT-DSK101-304[5K]-220C
|5.0
|220°C
|''Requires: HP4=220°C,''
|-
|'''''[https://wiki.nanofab.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]'''''
|''Route''
|COAT-UV6[2K]-135C
|2.0
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[2.5K]-135C
|2.5
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[3K]-135C
|3.0
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[3.5K]-135C
|3.5
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[4K]-135C
|4.0
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[5K]-135C
|5.0
|135°C
|''Requires: HP1=135°C''
|-
|
|
|COAT-UV6[6K]-135C
|6.0
|135°C
|''Requires: HP1=135°C''
|-
|'''''DS-K101 @ 185°C'''''
'''''+ UV6'''''
|''Chain''
|COAT-DSK101[1.5K]-185C-UV6[2K]-135C
|''DSK: 1.5krpm''
''UV6: 2.0krpm''
|DSK: 185°C
UV6: 135°C
|''Requires:''
''– HP4=185°C''

''– HP1=135°C''

''Plan for ~10-15 min per wafer.''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[2.5K]-135C
|''DSK: 1.5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3K]-135C
|''DSK: 1.5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[3.5K]-135C
|''DSK: 1.5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[4K]-135C
|''DSK: 1.5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[5K]-135C
|''DSK: 1.5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-185C-UV6[6K]-135C
|''DSK: 1.5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[2K]-135C
|''DSK: 5krpm''
''UV6: 2.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[2.5K]-135C
|''DSK: 5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3K]-135C
|''DSK: 5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[3.5K]-135C
|''DSK: 5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[4K]-135C
|''DSK: 5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[5K]-135C
|''DSK: 5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|COAT-DSK101[1.5K]-220C-UV6[6K]-135C
|''DSK: 5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
|'''''DS-K101 @ 185°C'''''
'''''+ UV6'''''
|''Chain''
|Coat-DSK101[5K]-185C-UV6[2K]-135C
|''DSK: 5krpm''
''UV6: 2.0krpm''
|DSK: 185°C
UV6: 135°C
|''Requires:''
''– HP4=185°C''

''– HP1=135°C''

''Plan for ~10-15 min per wafer.''
|-
|
|
|Coat-DSK101[5K]-185C-UV6[2.5K]-135C
|''DSK: 5krpm''
''UV6: 2.5krpm''
|''same as above''
|''same as above''
|-
|
|
|Coat-DSK101[5K]-185C-UV6[3K]-135C
|''DSK: 5krpm''
''UV6: 3.0krpm''
|''same as above''
|''same as above''
|-
|
|
|Coat-DSK101[5K]-185C-UV6[3.5K]-135C
|''DSK: 5krpm''
''UV6: 3.5krpm''
|''same as above''
|''same as above''
|-
|
|
|Coat-DSK101[5K]-185C-UV6[4K]-135C
|''DSK: 5krpm''
''UV6: 4.0krpm''
|''same as above''
|''same as above''
|-
|
|
|Coat-DSK101[5K]-185C-UV6[5K]-135C
|''DSK: 5krpm''
''UV6: 5.0krpm''
|''same as above''
|''same as above''
|-
|
|
|Coat-DSK101[5K]-185C-UV6[6K]-135C
|''DSK: 5krpm''
''UV6: 6.0krpm''
|''same as above''
|''same as above''
|-
|'''''Hotplate Set'''''
|''Route''
|''SET-HP4-220C''
|
|220°C
|''Hotplate 4 (top) between 218-222°C when done.''
|-
|
|
|''SET-HP4-210C''
|
|210°C
|
|-
|
|
|''SET-HP4-200C''
|
|200°C
|
|-
|
|
|''SET-HP4-185C''
|
|185*C
|
|}
==[[Holographic Lith/PL Setup (Custom)|Holography Recipes]]==
''The Holography recipes here use the BARC layer XHRiC-11 & the high-res. I-Line photoresist THMR-IP3600HP-D.''

*{{fl|Holography_Process_for_1D-lines_and_2D-dots_%28ARC-11_%26_THMR-IP3600HP-D%29-updated-4-8-2021.pdf|Standard Holography Process - on SiO2 on Si}}
*{{fl|Holography-Process-Variation-revA.pdf|Holography Process Variations - Set-up Angle - Etching into SiO2 and Si}}
*{{fl|05-SiO2_Nano-structure_Etch.pdf|Etch SiO2 Nano-structure - Changing Side-wall Angle - Etching into Si with a different line-width}}
*{{fl|30-Redicing_Nanowire_Diameter_by_Thermal_Oxidation_and_Vapored_HF_Etch.pdf|Reduce SiO2 Nanowire Diameter - Thermal Oxidation - Vapor HF Etching}}

==Low-K Spin-On Dielectric Recipes==

*{{fl|Lithography-BCB-photo-lowk-dielectric-spinon-4024-40-revA.docx|Photo BCB (4024-40)}}
*{{fl|BCB-cyclotene-3000-revA.pdf|Standard BCB (3022-46)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|SOG (T512B)}}

==Chemicals Stocked + Datasheets==
''The following is a list of the lithography chemicals we stock in the lab, with links to the datasheets for each. The datasheets will often have important processing info such as spin-speed vs. thickness curves, typical process parameters, bake temps/times etc.''
{|
|- valign="top"
| width="400" |
;<div id="PositivePR"><big>Positive Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AXP4000pb-Datasheet.pdf|AZP4000 (AZ4110, AZ4210, AZ4330)}}
*{{Fl|Az_p4620_photoresist_data_package.pdf|AZ P4620}}
*{{fl|OCG825-Positive-Resist-Datasheet.pdf|OCG825}}
*{{fl|SPR220-Positive-Resist-Datasheet.pdf|SPR220 (SPR220-3, SPR220-7)}}
*{{fl|SPR955-Positive-Resist-Datasheet.pdf|SPR955CM (SPR955CM-0.9, SPR955CM-1.8)}}
*THMR-3600HP (Thin I-Line & Holography)
**{{fl|THMR_iP_3500_iP3600.pdf|Evaluation Results: THMR-3600HP}}
**{{fl|3600_D,_D2v_Spin_Speed_Curve.pdf|Spin Curves for THMR-3600HP}}
**{{fl|THMR-iP3600_HP_D_20140801_(B)_GHS_US.pdf|Safety Datasheet for THMR-3600HP}}

'''''DUV-248nm'''''

*{{fl|UV210-Positive-Resist-Datasheet.pdf|UV210-0.3}}
*{{fl|UV6-Positive-Resist-Datasheet.pdf|UV6-0.8}}
*{{fl|UV26-Positive-Resist-Datasheet.pdf|UV26-2.5}}

;<div id="NegativePR"><big>Negative Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AZ5214-Negative-Resist-Datasheet.pdf|AZ5214}}
*{{fl|AZnLOF5510-Negative-Resist-Datasheet.pdf|AZnLOF5510}}
*{{fl|AZnLOF2020-Negative-Resist-Datasheet.pdf|AZnLOF2000 (AZnLOF2020, AZnLOF2035, AZnLOF2070)}}
*{{fl|NR9-1000PY-revA.pdf|Futurrex NR9-1000PY(use AZ300MIF dev)}}
*{{fl|NR9-3000PY-revA.pdf|Futurrex NR9-3000PY(use AZ300MIF dev)}}
*{{fl|NR9-6000PY-revA.pdf|Futurrex NR9-6000PY(use AZ300MIF dev)}}
*{{fl|SU-8-2015-revA.pdf|SU-8-2005,2010, 2015}}
*{{fl|SU-8-2075-revA.pdf|SU-8-2075}}

'''''DUV-248nm'''''

*{{fl|UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf|UVN-30-0.8}}

;<div id="Underlayers"><big>Underlayers</big></div>

*{{fl|PMGI-Underlayer-Datasheet.pdf|PMGI (PMGI SF3,5,8,11,15)}}
*{{fl|LOL2000-Underlayer-Datasheet.pdf|Shipley LOL2000}}

;<div id="EBLPR"><big>E-beam resists</big></div>

*{{fl|PMMA-E-Beam-Resist-Datasheet.pdf|PMMA (PMMA, P(MMA-MAA) copolymer)}}
*{{fl|maN2403-E-Beam-Resist-Datasheet.pdf|maN 2403}}

;<div id="NanoImprinting"><big>Nanoimprinting</big></div>

*{{fl|NX1020-Nanoimprinting-Datasheet.pdf|NX1020}}
*{{fl|MRI-7020-Nanoimprinting-Datasheet.pdf|MRI-7020}}
*{{fl|Mr-UVCur21.pdf|MR-UVCur21}}
*{{fl|OrmoStamp-NIL-Lithography-UV-Soft-RevA.pdf|Ormostamp}}

|
;<div id="ContrastEnhancement"><big>Contrast Enhancement Materials</big></div>

*{{fl|CEM365iS-Contrast-Enhancement-Datasheet.pdf|CEM365iS}}

;<div id="AntiReflectionCoatings"><big>Anti-Reflection Coatings</big></div>

*{{fl|XHRiC-Anti-Reflective-Coating.pdf|XHRiC-11 (i-line)}}
*{{fl|DUV42P-Anti-Reflective-Coating.pdf|DUV42P-6 (DUV) (For AR2 replacement)}}
*{{fl|DS-K101-304-Anti-Reflective-Coating.pdf|DS-K101-304 (DUV developable BARC)}}

;<div id="AdhesionPromoters"><big>Adhesion Promoters</big></div>

*HMDS
*AP3000 BCB Adhesion Promoter
*{{fl|OMNICOAT-revA.pdf|Omnicoat, SU-8 Adhesion Promoter}}
*{{fl|OrmoPrime-NIL-Adhesion-RevA.pdf|Ormoprime08-Ormostsmp Adhesion Promoter}}

;<div id="SpinOnDielectrics"><big>Spin-On Dielectrics</big></div>

''Low-K Spin-On Dielectrics such as Benzocyclobutane and Spin-on Glass''

*{{fl|BCB-cyclotene-3000-revA.pdf|BCB, Cyclotene 3022-46(Not Photosensitive)}}
*{{fl|BCB-cyclotene-4000-revA.pdf|PhotoBCB, Cyclotene 4022-40(Negative Polarity)}}
*{{fl|BCB-adhesion.pdf|BCB Adhesion Notes from Vendor}}
*{{fl|BCB-rework.pdf|BCB rework Notes from Vendor}}
*{{fl|512B-Datasheet-revA.pdf|Spin-on-Glass, Honeywell 512B (Not Photosensitive)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|Honeywell 512B Apps Data}}

;<div id="Developers"><big>Developers</big></div>

*{{fl|AZ400K-Developer-Datasheet.pdf|AZ400K (AZ400K, AZ400K1:4)}}
*{{fl|AZ300MIF-Developer-Datasheet.pdf|AZ300MIF}}
*DS2100 BCB Developer
*SU-8 Developer
*101A Developer (for DUV Flood Exposed PMGI)

;<div id="PRRemovers"><big>Photoresist Removers</big></div>

*[http://www.microchemicals.com/products/remover_stripper/nmp.html AZ NMP]
**''This replaces {{fl|1165-Resist-Remover.pdf|1165}}''
*{{fl|AZ300T-Resist-Remover.pdf|AZ300T}}
*{{fl|RemoverPG-revA.pdf|Remover PG, SU-8 stripper}}
*AZ EBR ("Edge Bead Remover", PGMEA)

|}

[[Category: Processing]]
[[category: Lithography]]
[[category: Recipes]]