UCSB Nanofab Wiki - User contributions [en]

Research

2026-05-19T17:02:51Z

John d: fixed duplicate lab names

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<div style="font-size: 1.6em; font-weight: bold; color: #003660; margin-bottom: 8px;">UCSB Nanofabrication Facility — Research Groups & Publications</div>
<div style="font-size: 1.05em; color: #444;">A curated directory of research groups utilizing the [https://www.nanotech.ucsb.edu/ UCSB Nanofab], organized by discipline. Each section highlights recent high-impact publications and representative research imagery.</div>
<div style="margin-top: 10px; font-size: 0.9em; color: #666;">''Last updated: April 2026''</div>
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== Photonics and Integrated Optics ==

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''Silicon photonics, III-V integration, optical communications, nanophotonic devices, and metasurfaces — enabling next-generation data links, sensing, and on-chip light manipulation.''
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=== Optical Communications & Photonic Integration Group — Prof. Daniel Blumenthal ===

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'''PI:''' [https://scholar.google.com/citations?user=4yjw1ecAAAAJ Prof. Daniel Blumenthal] (Google Scholar) • [https://ocpi.ece.ucsb.edu/ Group Website]

Develops ultra-low-loss silicon nitride (Si3N4) photonic integrated circuits for stimulated Brillouin lasers, optical gyroscopes, optical frequency synthesis, and emerging atom-photonic quantum integration on chip.

'''Selected Recent Publications:'''
* ''Integrated optical frequency division for microwave and mmWave generation'' — '''Nature''' 627, 540–545 (2024). [https://doi.org/10.1038/s41586-024-07057-0 DOI]
* ''Integrated photonic molecule Brillouin laser with a high-power sub-100-mHz fundamental linewidth'' — '''Optics Letters''' 49(1), 45–48 (2024). [https://doi.org/10.1364/OL.503126 DOI]
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[[File:2026-04-24_research_Blumenthal_SiN_coil_resonator.jpg|thumb|300px|Ultra-low-loss silicon nitride photonic coil resonator chip used for Brillouin lasers and high-Q resonators.]]
[[File:2026-04-24_research_Blumenthal_PZT_SiN_microcomb.png|thumb|300px|PZT-integrated silicon nitride microcomb resonator for chip-based optical frequency division.]]
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=== Silicon Photonics, AIM Photonics & Institute for Energy Efficiency — Prof. John Bowers ===

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'''PI:''' [https://scholar.google.com/citations?user=c6rbVa0AAAAJ Prof. John Bowers] (Google Scholar) • [https://siliconphotonics.ece.ucsb.edu/ Silicon Photonics] • [https://aim.ucsb.edu AIM Photonics] • [https://iee.ucsb.edu IEE]

Leads research on heterogeneous integration of III-V materials on silicon for lasers, amplifiers, and modulators, as well as advanced silicon photonic platforms for datacom, telecom, and ultra-narrow-linewidth laser sources.

'''Selected Recent Publications:'''
* ''Roadmapping the next generation of silicon photonics'' — '''Nature Communications''' 15, 751 (2024). [https://doi.org/10.1038/s41467-024-44750-0 DOI]
* ''Lithium niobate photonics: Unlocking the electromagnetic spectrum'' — '''Science''' 379(6627) (2023). [https://doi.org/10.1126/science.abj4396 DOI]
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[[File:2026-04-24_research_Bowers_3D_PIC_integration.png|thumb|300px|3D photonic integrated circuit: heterogeneous III-V on silicon architecture without an isolator (Nature, 2023).]]
[[File:2026-04-24_research_Bowers_racetrack_resonator.jpg|thumb|300px|Novel conjoined racetrack resonator geometry for silicon photonics.]]
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=== Integrated Photonics Laboratory — Prof. Jonathan Klamkin ===

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'''PI:''' [https://scholar.google.com/citations?user=vR_K3XYAAAAJ Prof. Jonathan Klamkin] (Google Scholar) • [https://web.ece.ucsb.edu/ipl Group Website]

Specializes in III-V photonic integrated circuits for free-space optical communications, LiDAR, microwave photonics, and monolithic integration of III-V quantum dot lasers on silicon via selective area heteroepitaxy.

'''Selected Recent Publications:'''
* ''Selective area heteroepitaxy of low dislocation density antiphase boundary free GaAs microridges on flat-bottom (001) Si for integrated silicon photonics'' — '''Applied Physics Letters''' 118, 122106 (2021). [https://doi.org/10.1063/5.0043027 DOI]
* ''Towards fully monolithic silicon-based integrated photonics: MOCVD grown lasers on silicon by blanket and selective area heteroepitaxy'' — '''Proc. SPIE''' (Photonics West, 2022). [https://doi.org/10.1117/12.2610644 DOI]
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[[File:2026-04-24_research_Klamkin_3D_hybrid_SiPh.jpg|thumb|300px|3D hybrid integrated silicon photonics platform merging InP and GaAs devices with SiPh.]]
[[File:2026-04-24_research_Klamkin_free_space_optical_comms.jpg|thumb|300px|Laser communication terminal for free-space optical links (NASA-funded research).]]
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=== Schow Lab ===

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'''PI:''' [https://scholar.google.com/citations?user=cVY3g4cAAAAJ Prof. Clint Schow] (Google Scholar) • [https://schow.ece.ucsb.edu/ Group Website]

Develops energy-efficient optical interconnects for data centers, with emphasis on analog coherent detection architectures that eliminate power-hungry DSP, leveraging silicon photonics and co-packaged optics.

'''Selected Recent Publications:'''
* ''A Monolithic O-Band Coherent Optical Receiver for Energy-Efficient Links'' — '''IEEE Journal of Solid-State Circuits''' 59(5) (2024). [https://doi.org/10.1109/JSSC.2023.3339494 DOI]
* ''Analog Coherent Detection for Energy Efficient Intra-Data Center Links at 200 Gbps Per Wavelength'' — '''Journal of Lightwave Technology''' 39(2) (2021). [https://doi.org/10.1109/JLT.2020.3029788 DOI]
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[[File:2026-04-24_research_Schow_coherent_optical_links.jpg|thumb|300px|Low-power coherent optical links for datacenter interconnects.]]
[[File:2026-04-24_research_Schow_cryogenic_optical_links.jpg|thumb|300px|Cryogenic silicon photonic optical links for classical and quantum computing.]]
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=== Schuller Lab ===

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'''PI:''' [https://scholar.google.com/citations?user=Ff90s74AAAAJ Prof. Jon Schuller] (Google Scholar) • [https://schuller.cnsi.ucsb.edu/ Group Website]

Investigates light-matter interactions at the nanoscale, designing dielectric and semiconductor metasurfaces for directional light emission, magneto-optical traps, and active reconfigurable photonic devices.

'''Selected Recent Publications:'''
* ''High efficiency large-angle polarization-insensitive retroreflecting metasurface for magneto-optical traps'' — '''Applied Physics Letters''' 124, 251704 (2024). [https://doi.org/10.1063/5.0210124 DOI]
* ''Optimizing Polarization Selective Unidirectional Photoluminescence from Phased-Array Metasurfaces'' — '''Advanced Optical Materials''' (2024). [https://doi.org/10.1002/adom.202303186 DOI]
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[[File:2026-04-24_research_Schuller_crystal_microstructures.jpg|thumb|300px|Hybrid organic/inorganic crystalline microstructures with quantum-confinement-induced red luminescence.]]
[[File:2026-04-24_research_Schuller_metasurface_beam_deflector.jpg|thumb|300px|Tunable dielectric metasurface beam deflector for engineered light steering.]]
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== Quantum Computing, Quantum Sensing & Quantum Materials ==

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''Quantum optics, entangled photon sources, NV-center sensing, topological qubits, and correlated electron systems — building the hardware foundations for quantum information science.''
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=== Quantum Optics & Quantum Information Group — Prof. Dirk Bouwmeester ===

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'''PI:''' [https://scholar.google.com/citations?user=r92BS5wAAAAJ Prof. Dirk Bouwmeester] (Google Scholar) • [https://bouwmeestergroup.physics.ucsb.edu Group Website]

Explores quantum optics and cavity quantum electrodynamics with semiconductor quantum dots, optomechanical systems using phononic crystal membranes, and quantum decoherence phenomena.

'''Selected Recent Publications:'''
* ''Single-emitter quantum key distribution over 175 km of fibre with optimised finite key rates'' — '''Nature Communications''' 14, 3573 (2023). [https://doi.org/10.1038/s41467-023-39219-5 DOI]
* ''Phononically shielded multi-wavelength photonic-crystal membrane for cavity quantum optomechanics'' — '''Optics Express''' 33(4), 8203 (2025). [https://doi.org/10.1364/OE.550826 DOI]
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[[File:2026-04-24_research_Bouwmeester_phononic_crystal_membrane_SEM.jpg|thumb|300px|SEM image of a phononic crystal membrane fabricated for optomechanical experiments (silicon nitride or diamond).]]
[[File:2026-04-24_research_Bouwmeester_QD_microcavity_defect.jpg|thumb|300px|Dark-field optical image of a quantum dot microcavity device showing the defect region of a photonic crystal structure.]]
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=== Quantum Photonics Laboratory — Prof. Galan Moody ===

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'''PI:''' [https://scholar.google.com/citations?user=FLokITkAAAAJ Prof. Galan Moody] (Google Scholar) • [https://qpl.ece.ucsb.edu Group Website]

Develops integrated quantum photonic devices on chip-scale platforms, including entangled photon-pair sources from microring resonators, 2D material quantum emitters, and scalable single-photon technologies for quantum networking.

'''Selected Recent Publications:'''
* ''2022 Roadmap on integrated quantum photonics'' — '''Journal of Physics: Photonics''' 4, 012501 (2022). [https://doi.org/10.1088/2515-7647/ac1ef4 DOI]
* ''Defect and strain engineering of monolayer WSe2 enables site-controlled single-photon emission up to 150 K'' — '''Nature Communications''' 12, 3585 (2021). [https://doi.org/10.1038/s41467-021-23709-5 DOI]
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[[File:2026-04-24_research_Moody_QPL_Cisco_entanglement_chip.jpg|thumb|300px|Packaged AlGaAs-on-insulator photonic integrated circuit (PIC) with entangled-pair sources, delivered to Cisco Quantum Labs for quantum networking.]]
[[File:2026-04-24_research_Moody_QPL_AlGaAs_ring_array_2025.jpg|thumb|300px|AlGaAsOI microresonator ring array for high-rate time- and frequency-bin entanglement generation (from PRX Quantum 2025 publication).]]
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=== Quantum Sensing & Imaging Group — Prof. Ania Jayich ===

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'''PI:''' [https://scholar.google.com/citations?user=EKElikcAAAAJ Prof. Ania Bleszynski Jayich] (Google Scholar) • [https://www.10-9lab.com/ Group Website (10−9 Lab)]

Engineers nitrogen-vacancy (NV) centers in diamond for ultra-sensitive nanoscale magnetometry and quantum sensing. Recent breakthroughs leverage many-body quantum dynamics for signal amplification in solid-state quantum sensors.

'''Selected Recent Publications:'''
* ''Signal amplification in a solid-state sensor through asymmetric many-body echo'' — '''Nature''' 646, 68–73 (2025). [https://doi.org/10.1038/s41586-025-09452-7 DOI]
* ''Scalable nanoscale positioning of highly coherent color centers in prefabricated diamond nanostructures'' — '''Nature Communications''' 16 (2025). [https://doi.org/10.1038/s41467-025-64758-4 DOI]
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[[File:2026-04-24_research_Jayich_NV_diamond_scanning_probe.jpg|thumb|300px|Diamond scanning probe tip with a single NV center, used for nanoscale magnetometry (pillar-cantilever geometry).]]
[[File:2026-04-24_research_Jayich_NV_magnetometry_scan.jpg|thumb|300px|Scanning NV magnetometry image showing nanoscale magnetic field mapping of a condensed matter sample.]]
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=== Palmstrom Group ===

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'''PI:''' [https://scholar.google.com/citations?user=c-B7OFcAAAAJ Prof. Chris Palmstrom] (Google Scholar) • [https://palmstrom.cnsi.ucsb.edu/ Group Website]

Grows quantum materials by molecular beam epitaxy (MBE), including III-V semiconductor heterostructures, Heusler compounds, and superconductor/semiconductor hybrids for topological quantum computing and superconducting circuits.

'''Selected Recent Publications:'''
* ''Cryogenic Growth of Tantalum Thin Films for Low-Loss Superconducting Circuits'' — '''Physical Review Applied''' 23(3), 034025 (2025). [https://doi.org/10.1103/PhysRevApplied.23.034025 DOI]
* ''Fabrication and Characterization of Low-Loss Al/Si/Al Parallel Plate Capacitors for Superconducting Quantum Information Applications'' — '''npj Quantum Information''' 11 (2025). [https://doi.org/10.1038/s41534-025-00967-5 DOI]
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[[File:2026-04-24_research_Palmstrom_Sn_InAs_Josephson_junction_nanowire.jpeg|thumb|300px|SEM/false-color image of Sn/InAs Josephson junctions on selective area grown nanowires with in-situ shadowed superconductor evaporation.]]
[[File:2026-04-24_research_Palmstrom_CryoMBE_chamber.jpg|thumb|300px|Scienta Omicron EVO 50 Cryo-MBE chamber for growing superconductors at cryogenic substrate temperatures (below 20 K).]]
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=== Young Lab ===

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'''PI:''' [https://scholar.google.com/citations?user=EbqS1EoAAAAJ Prof. Andrea Young] (Google Scholar) • [https://www.afylab.com/ Group Website]

Investigates correlated electronic phases in van der Waals heterostructures, including superconductivity, magnetism, and quantum Hall physics in graphene-based systems using nanofabrication and low-temperature transport measurements.

'''Selected Recent Publications:'''
* ''Superconductivity in rhombohedral trilayer graphene'' — '''Nature''' 598, 434–438 (2021). [https://doi.org/10.1038/s41586-021-03926-0 DOI]
* ''Isospin magnetism and spin-polarized superconductivity in Bernal bilayer graphene'' — '''Science''' 375(6582) (2022). [https://doi.org/10.1126/science.abm8386 DOI]
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[[File:2026-04-24_research_Young_nanoSQUID_tip_probe.jpg|thumb|300px|NanoSQUID-on-tip probe and tuning fork assembly used for cryogenic scanning magnetic and thermal imaging of quantum materials.]]
[[File:2026-04-24_research_Young_nanoSQUID_AC_sweep_scan.png|thumb|300px|NanoSQUID scanning image of a van der Waals heterostructure device, showing AC susceptibility mapping (likely graphene fractional quantum Hall system).]]
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== High-Speed Electronics & RF ==

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''Sub-THz transistors, 2D-material nanoelectronics, and advanced CMOS architectures — driving the next generation of wireless communications and computing.''
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=== High Speed Electronics Group — Prof. Mark Rodwell ===

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'''PI:''' [https://scholar.google.com/citations?user=u_C8sbEAAAAJ Prof. Mark Rodwell] (Google Scholar) • [https://web.ece.ucsb.edu/Faculty/rodwell/ Group Website]

Develops InP heterojunction bipolar transistor (HBT) integrated circuits and transceiver modules operating at 100–300 GHz for next-generation sub-THz wireless communication systems with multi-Gbps data rates.

'''Selected Recent Publications:'''
* ''100–300 GHz Wireless: Transistors, ICs, and Systems'' — '''IEEE Microwave Magazine''' (2025). [https://doi.org/10.1109/MMM.2025.3584028 DOI]
* ''A 280 GHz InP HBT Direct-Conversion Receiver with 10.8 dB NF'' — '''IEEE RFIC Symposium''' (2023). [https://doi.org/10.1109/RFIC54547.2023.10186179 DOI]
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[[File:2026-04-24_research_Rodwell_InP_HBT_CrossSection_SEM.jpg|thumb|300px|Cross-sectional SEM of a UCSB InP HBT showing sub-micron emitter, base, and collector mesa layers.]]
[[File:2026-04-24_research_Rodwell_THz_Transceiver_IC.jpg|thumb|300px|130 nm InP HBT transceiver IC layout for 100–300 GHz wireless systems.]]
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=== Nanoelectronics Research Lab — Prof. Kaustav Banerjee ===

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'''PI:''' [https://scholar.google.com/citations?user=zkZqDDcAAAAJ Prof. Kaustav Banerjee] (Google Scholar) • [https://nrl.ece.ucsb.edu/ Group Website]

Pioneers 2D material-based transistor architectures for future CMOS scaling, including 3D transistors with 2D semiconductors, neuromorphic computing platforms using tunnel-FETs, and cryogenic CMOS for quantum computing.

'''Selected Recent Publications:'''
* ''Three-dimensional Transistors with Two-dimensional Semiconductors for Future CMOS Scaling'' — '''Nature Electronics''' (2024). [https://doi.org/10.1038/s41928-024-01289-8 DOI]
* ''An Ultra Energy-efficient Hardware Platform for Neuromorphic Computing Enabled by 2D-TMD Tunnel-FETs'' — '''Nature Communications''' (2024). [https://doi.org/10.1038/s41467-024-46397-3 DOI]
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[[File:2026-04-24_research_Banerjee_Graphene_Kinetic_Inductor.jpg|thumb|300px|Intercalated multilayer graphene on-chip spiral inductors — the first kinetic inductors achieving 1.5× higher inductance density than copper.]]
[[File:2026-04-24_research_Banerjee_2D_3D_NanoplateFET.png|thumb|300px|3D nano-plate FET architecture using 2D WS2 semiconductors in gate-all-around configuration.]]
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== Wide-Bandgap Semiconductors & Power Electronics ==

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''GaN and Ga2O3 devices for solid-state lighting, micro-LEDs, laser diodes, and high-voltage power conversion — from Nobel Prize-winning blue LEDs to next-generation ultra-wide-bandgap power electronics.''
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=== Krishnamoorthy Research Group ===

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'''PI:''' [https://scholar.google.com/citations?user=msxQ2fYAAAAJ Prof. Sriram Krishnamoorthy] (Google Scholar) • [https://sites.google.com/view/krishnamoorthygroup/home Group Website]

Advances ultra-wide-bandgap semiconductor device technology, particularly β-Ga2O3 power electronics including kilovolt-class MOSFETs and Schottky barrier diodes grown by MOCVD for high-voltage, high-efficiency power conversion.

'''Selected Recent Publications:'''
* ''Kilovolt-Class β-Ga2O3 MOSFETs on 1-inch Bulk Substrates'' — '''Applied Physics Letters''' (2024). [https://doi.org/10.1063/5.0191366 DOI]
* ''2.1 kV (001)-β-Ga2O3 Vertical Schottky Barrier Diode with High-k Oxide Field Plate'' — '''Applied Physics Letters''' (2023). [https://doi.org/10.1063/5.0137935 DOI]
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[[File:2026-04-24_research_Krishnamoorthy_Ga2O3_TriGate_MESFET.jpg|thumb|300px|Wide-bandgap semiconductor device research: GaN/Ga2O3 power electronics for high-voltage, high-efficiency power conversion.]]
[[File:2026-04-24_research_Krishnamoorthy_Ga2O3_SiC_MOSFET.jpg|thumb|300px|Advanced materials research at UCSB CNSI for ultra-wide-bandgap semiconductor devices.]]
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=== Solid State Lighting & Electronic Center (SSLEEC) — Prof. Steven DenBaars & Prof. Shuji Nakamura ===

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'''Directors:''' [https://scholar.google.com/citations?user=CO1qY8cAAAAJ Prof. Steven DenBaars] (Google Scholar) • [https://scholar.google.com/citations?user=7Esq3V8AAAAJ Prof. Shuji Nakamura] (Nobel Laureate, 2014 — Google Scholar) • [https://ssleec.ucsb.edu/ SSLEEC Website]

Leads development of III-nitride (InGaN/GaN) optoelectronic devices including micro-LEDs scaled to the single-micron regime for AR/VR displays, edge-emitting laser diodes, and advanced LED architectures with metasurface and distributed Bragg reflector integration.

'''Selected Recent Publications:'''
* ''High External Quantum Efficiency in Ultra-small Amber InGaN MicroLEDs Scaled to 1 μm'' — '''Applied Physics Letters''' (2024). [https://doi.org/10.1063/5.0235915 DOI]
* ''Metasurface Light-Emitting Diodes with Directional and Focused Emission'' — '''Nano Letters''' (2023). [https://doi.org/10.1021/acs.nanolett.3c03272 DOI]
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[[File:2026-04-24_research_SSLEEC_MicroLED_DBR_SEM.png|thumb|300px|Comparison of 1 μm InGaN/GaN micro-LED with a human hair, demonstrating ultra-small scale device fabrication for AR/VR displays.]]
[[File:2026-04-24_research_SSLEEC_GaN_LED_DeviceStack.jpg|thumb|300px|SSLEEC optical bench with III-nitride LED/laser characterization equipment. Photo: Prof. Shuji Nakamura.]]
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== Advanced Materials & Novel Devices ==

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''Topological semimetals, memristive crossbar arrays, plasma nanoscience, and neuromorphic hardware — pushing the boundaries of materials science and unconventional computing architectures.''
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=== Stemmer Research Group ===

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'''PI:''' [https://scholar.google.com/citations?user=XFlNLAsAAAAJ Prof. Susanne Stemmer] (Google Scholar) • [https://stemmer.materials.ucsb.edu/ Group Website]

Investigates quantum materials including functional and correlated complex oxides and topological semimetals, with emphasis on thin-film epitaxial growth (MBE), quantum transport, and electronic structure engineering at heterostructure interfaces.

'''Selected Recent Publications:'''
* ''Two-Dimensional Topological Insulator State in Cadmium Arsenide Thin Films'' — '''Physical Review Letters''' 130, 046201 (2023). [https://doi.org/10.1103/PhysRevLett.130.046201 DOI]
* ''Similarity in the Critical Thicknesses for Superconductivity and Ferroelectricity in Strained SrTiO3 Films'' — '''Applied Physics Letters''' (2022). [https://doi.org/10.1063/5.0096834 DOI]
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[[File:2026-04-24_research_Stemmer_Cd3As2_HAADF_STEM.jpg|thumb|300px|Stemmer Research Group banner: MBE-grown quantum materials and topological semimetal thin films.]]
[[File:2026-04-24_research_Stemmer_SrTiO3_QSTEM_Vacancy.jpg|thumb|300px|Advanced characterization tools and discovery science at UCSB CNSI for quantum materials research.]]
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=== Strukov Research Group ===

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'''PI:''' [https://scholar.google.com/citations?user=SbPe9WEAAAAJ Prof. Dmitri Strukov] (Google Scholar) • [https://sites.google.com/site/strukov/home Group Website]

Develops novel memristive (resistive switching) devices and hybrid CMOS/memristor circuits for neuromorphic computing, in-memory computing, and hardware accelerators for neural networks and optimization problems.

'''Selected Recent Publications:'''
* ''Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems'' — '''ACS Nano''' (2023). [https://doi.org/10.1021/acsnano.3c03505 DOI]
* ''4K-Memristor Analog-Grade Passive Crossbar Circuit'' — '''Nature Communications''' 12 (2021). [https://doi.org/10.1038/s41467-021-25455-0 DOI]
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[[File:2026-04-24_research_Strukov_4K_Memristor_Crossbar_SEM.png|thumb|300px|SEM of a 64×64 passive memristive crossbar array (4,096 devices) with Ti/Al/TiN electrodes and Al2O3/TiO2-x switching layers.]]
[[File:2026-04-24_research_Strukov_Memristor_Einstein_Conductance.png|thumb|300px|4K-pixel grayscale Einstein image programmed into the memristive crossbar with <4% tuning error, demonstrating analog-grade conductance control.]]
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=== Gordon Lab ===

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'''PI:''' [https://scholar.google.com/citations?user=HUM5shgAAAAJ Prof. Michael J. Gordon] (Google Scholar) • [http://sites.chemengr.ucsb.edu/~mjgordon/research/home.html Group Website]

Works on plasma science and engineering (atmospheric and non-thermal plasmas), catalysis in molten metals for methane pyrolysis and hydrogen production, and nanoscale fabrication including colloidal lithography and micro-LED characterization.

'''Selected Recent Publications:'''
* ''AC Plasmas Directly Excited in Liquid-Phase Hydrocarbons for H2 and Unsaturated C2 Hydrocarbon Production'' — '''Journal of the American Chemical Society''' 147(1) (2025). [https://doi.org/10.1021/jacs.4c11174 DOI]
* ''Dry Reforming of Methane Catalysed by Molten Metal Alloys'' — '''Nature Catalysis''' 3, 83–89 (2020). [https://doi.org/10.1038/s41929-019-0416-2 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Gordon_Plasma_Shadowgraph_Hexane.png|thumb|300px|Laser shadowgraph of plasma discharge in liquid hexane showing streamer propagation and shock waves for hydrogen production.]]
[[File:2026-04-24_research_Gordon_AC_Plasma_Hexane_Timelapse.jpg|thumb|300px|Gordon Lab research: Plasma science, catalysis, and nanoscale fabrication for hydrogen production and sustainable chemistry.]]
</td>
</tr>
</table>





== Microfluidics & MEMS ==

<div style="border-left: 4px solid #08979c; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Nanofluidic transport, lab-on-chip biosensors, and microfabricated biomedical devices — bridging nanofabrication with biological and chemical applications.''
</div>



=== Pennathur Lab ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=dVbZMA0AAAAJ Prof. Sumita Pennathur] (Google Scholar) • [https://nanolab.engineering.ucsb.edu/ Group Website]

Studies electrokinetic transport in nanofluidic channels, ionic current rectification in bipolar nanochannels, and the design of nanofluidic diodes and biosensors, combining experimental micro/nanofabrication with computational modeling.

'''Selected Recent Publications:'''
* ''Coupling Charge-Regulated Interfacial Chemistry to Electrokinetic Ion Transport in Bipolar SiO2–Al2O3 Nanofluidic Diodes'' — '''Advanced Materials Interfaces''' (2024). [https://doi.org/10.1002/admi.202400495 DOI]
* ''Nanofluidic Diodes Based on Asymmetric Bio-Inspired Surface Coatings in Straight Glass Nanochannels'' — '''Faraday Discussions''' (2023). [https://doi.org/10.1039/D3FD00074E DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Pennathur_Nanochannel_Embedded_Electrode.png|thumb|300px|Nanofluidic channel with embedded electrodes for electric double layer modulation and electroosmotic flow control.]]
[[File:2026-04-24_research_Pennathur_Silicon_Microneedle_SEM.png|thumb|300px|Silicon microneedle array fabricated using MEMS wet etching techniques for minimally invasive biofluid extraction.]]
</td>
</tr>
</table>





== Astronomical Instrumentation ==

<div style="border-left: 4px solid #531dab; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Superconducting photon-counting detectors for ground-based astronomy — fabricating the cameras that image exoplanets.''
</div>



=== Mazin Laboratory ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [http://web.physics.ucsb.edu/~bmazin/index.html Prof. Benjamin Mazin] • [https://inspirehep.net/authors/1037976 INSPIRE-HEP Publications] • [http://web.physics.ucsb.edu/~bmazin/publications/ Lab Publication List]

Pioneers Microwave Kinetic Inductance Detectors (MKIDs) — superconducting photon-counting sensors with zero read noise that measure each photon's energy, arrival time, and position. Deploys MKID-based cameras (MEC, XKID) at major telescopes for direct imaging of exoplanets.

'''Selected Recent Publications:'''
* ''Characterization of Photon Arrival Timing Jitter in Microwave Kinetic Inductance Detector Arrays'' — '''Applied Physics Letters''' (2024). [https://doi.org/10.1063/5.0190172 DOI]
* ''Characterizing the Dark Count Rate of a Large-Format MKID Array'' — '''Optics Express''' 31(6), 10775 (2023). [https://doi.org/10.1364/OE.485003 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Mazin_MKID_20K_Array_Package.jpg|thumb|300px|Optical/near-IR MKID array — the revolutionary photon-counting detector technology at the core of Mazin Lab research.]]
[[File:2026-04-24_research_Mazin_MKID_10K_Array_Zoom.png|thumb|300px|10,000-pixel MKID array in gold sample box with progressive zoom-ins showing pixel grid and individual lumped-element resonator structures.]]
</td>
</tr>
</table>





----

<div style="border: 1px solid #d9d9d9; border-radius: 6px; padding: 16px; margin-top: 20px; background: #fafafa;">
== Publication Archives ==

* [[PubList2018|'''2018 Publications''']]
* [[Older Publications|'''Earlier Publications''']]
* [[Template:Publications|Select Publications]] — ''A selection of publications that utilized the UCSB NanoFab''

== Research Presentations ==

* [[Photonics Presentations|Photonics]]
* [[Electronics Presentations|Electronics]]
* [[THz Physics Presentations|THz Physics]]

== Research Image Galleries ==

* [[Photonics Pictures|Photonics]] • [[Electronics Pictures|Electronics]] • [[MEMS Pictures|MEMS]] • [[Physics Pictures|Physics]] • [[Fluidics Pictures|Fluidics]]
</div>

[[Category:Research]]
[[Category:Publications]]
[[Category:Nanofabrication]]
__FORCETOC__

Research

2026-05-19T17:00:25Z

John d: fixed image URLs

<div style="border: 2px solid #003660; border-radius: 8px; padding: 20px; margin-bottom: 20px; background: linear-gradient(135deg, #f8f9fa 0%, #e8eef5 100%);">
<div style="font-size: 1.6em; font-weight: bold; color: #003660; margin-bottom: 8px;">UCSB Nanofabrication Facility — Research Groups & Publications</div>
<div style="font-size: 1.05em; color: #444;">A curated directory of research groups utilizing the [https://www.nanotech.ucsb.edu/ UCSB Nanofab], organized by discipline. Each section highlights recent high-impact publications and representative research imagery.</div>
<div style="margin-top: 10px; font-size: 0.9em; color: #666;">''Last updated: April 2026''</div>
</div>

__TOC__





== Photonics and Integrated Optics ==

<div style="border-left: 4px solid #0077b6; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Silicon photonics, III-V integration, optical communications, nanophotonic devices, and metasurfaces — enabling next-generation data links, sensing, and on-chip light manipulation.''
</div>



=== Optical Communications & Photonic Integration Group — Prof. Daniel Blumenthal ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=4yjw1ecAAAAJ Prof. Daniel Blumenthal] (Google Scholar) • [https://ocpi.ece.ucsb.edu/ Group Website]

Develops ultra-low-loss silicon nitride (Si3N4) photonic integrated circuits for stimulated Brillouin lasers, optical gyroscopes, optical frequency synthesis, and emerging atom-photonic quantum integration on chip.

'''Selected Recent Publications:'''
* ''Integrated optical frequency division for microwave and mmWave generation'' — '''Nature''' 627, 540–545 (2024). [https://doi.org/10.1038/s41586-024-07057-0 DOI]
* ''Integrated photonic molecule Brillouin laser with a high-power sub-100-mHz fundamental linewidth'' — '''Optics Letters''' 49(1), 45–48 (2024). [https://doi.org/10.1364/OL.503126 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Blumenthal_SiN_coil_resonator.jpg|thumb|300px|Ultra-low-loss silicon nitride photonic coil resonator chip used for Brillouin lasers and high-Q resonators.]]
[[File:2026-04-24_research_Blumenthal_PZT_SiN_microcomb.png|thumb|300px|PZT-integrated silicon nitride microcomb resonator for chip-based optical frequency division.]]
</td>
</tr>
</table>



=== Silicon Photonics, AIM Photonics & Institute for Energy Efficiency — Prof. John Bowers ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=c6rbVa0AAAAJ Prof. John Bowers] (Google Scholar) • [https://siliconphotonics.ece.ucsb.edu/ Silicon Photonics] • [https://aim.ucsb.edu AIM Photonics] • [https://iee.ucsb.edu IEE]

Leads research on heterogeneous integration of III-V materials on silicon for lasers, amplifiers, and modulators, as well as advanced silicon photonic platforms for datacom, telecom, and ultra-narrow-linewidth laser sources.

'''Selected Recent Publications:'''
* ''Roadmapping the next generation of silicon photonics'' — '''Nature Communications''' 15, 751 (2024). [https://doi.org/10.1038/s41467-024-44750-0 DOI]
* ''Lithium niobate photonics: Unlocking the electromagnetic spectrum'' — '''Science''' 379(6627) (2023). [https://doi.org/10.1126/science.abj4396 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Bowers_3D_PIC_integration.png|thumb|300px|3D photonic integrated circuit: heterogeneous III-V on silicon architecture without an isolator (Nature, 2023).]]
[[File:2026-04-24_research_Bowers_racetrack_resonator.jpg|thumb|300px|Novel conjoined racetrack resonator geometry for silicon photonics.]]
</td>
</tr>
</table>



=== Integrated Photonics Laboratory — Prof. Jonathan Klamkin ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=vR_K3XYAAAAJ Prof. Jonathan Klamkin] (Google Scholar) • [https://web.ece.ucsb.edu/ipl Group Website]

Specializes in III-V photonic integrated circuits for free-space optical communications, LiDAR, microwave photonics, and monolithic integration of III-V quantum dot lasers on silicon via selective area heteroepitaxy.

'''Selected Recent Publications:'''
* ''Selective area heteroepitaxy of low dislocation density antiphase boundary free GaAs microridges on flat-bottom (001) Si for integrated silicon photonics'' — '''Applied Physics Letters''' 118, 122106 (2021). [https://doi.org/10.1063/5.0043027 DOI]
* ''Towards fully monolithic silicon-based integrated photonics: MOCVD grown lasers on silicon by blanket and selective area heteroepitaxy'' — '''Proc. SPIE''' (Photonics West, 2022). [https://doi.org/10.1117/12.2610644 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Klamkin_3D_hybrid_SiPh.jpg|thumb|300px|3D hybrid integrated silicon photonics platform merging InP and GaAs devices with SiPh.]]
[[File:2026-04-24_research_Klamkin_free_space_optical_comms.jpg|thumb|300px|Laser communication terminal for free-space optical links (NASA-funded research).]]
</td>
</tr>
</table>



=== Schow Lab — Prof. Clint Schow ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=cVY3g4cAAAAJ Prof. Clint Schow] (Google Scholar) • [https://schow.ece.ucsb.edu/ Group Website]

Develops energy-efficient optical interconnects for data centers, with emphasis on analog coherent detection architectures that eliminate power-hungry DSP, leveraging silicon photonics and co-packaged optics.

'''Selected Recent Publications:'''
* ''A Monolithic O-Band Coherent Optical Receiver for Energy-Efficient Links'' — '''IEEE Journal of Solid-State Circuits''' 59(5) (2024). [https://doi.org/10.1109/JSSC.2023.3339494 DOI]
* ''Analog Coherent Detection for Energy Efficient Intra-Data Center Links at 200 Gbps Per Wavelength'' — '''Journal of Lightwave Technology''' 39(2) (2021). [https://doi.org/10.1109/JLT.2020.3029788 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Schow_coherent_optical_links.jpg|thumb|300px|Low-power coherent optical links for datacenter interconnects.]]
[[File:2026-04-24_research_Schow_cryogenic_optical_links.jpg|thumb|300px|Cryogenic silicon photonic optical links for classical and quantum computing.]]
</td>
</tr>
</table>



=== Schuller Lab — Prof. Jon Schuller ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=Ff90s74AAAAJ Prof. Jon Schuller] (Google Scholar) • [https://schuller.cnsi.ucsb.edu/ Group Website]

Investigates light-matter interactions at the nanoscale, designing dielectric and semiconductor metasurfaces for directional light emission, magneto-optical traps, and active reconfigurable photonic devices.

'''Selected Recent Publications:'''
* ''High efficiency large-angle polarization-insensitive retroreflecting metasurface for magneto-optical traps'' — '''Applied Physics Letters''' 124, 251704 (2024). [https://doi.org/10.1063/5.0210124 DOI]
* ''Optimizing Polarization Selective Unidirectional Photoluminescence from Phased-Array Metasurfaces'' — '''Advanced Optical Materials''' (2024). [https://doi.org/10.1002/adom.202303186 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Schuller_crystal_microstructures.jpg|thumb|300px|Hybrid organic/inorganic crystalline microstructures with quantum-confinement-induced red luminescence.]]
[[File:2026-04-24_research_Schuller_metasurface_beam_deflector.jpg|thumb|300px|Tunable dielectric metasurface beam deflector for engineered light steering.]]
</td>
</tr>
</table>





== Quantum Computing, Quantum Sensing & Quantum Materials ==

<div style="border-left: 4px solid #7b2d8e; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Quantum optics, entangled photon sources, NV-center sensing, topological qubits, and correlated electron systems — building the hardware foundations for quantum information science.''
</div>



=== Quantum Optics & Quantum Information Group — Prof. Dirk Bouwmeester ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=r92BS5wAAAAJ Prof. Dirk Bouwmeester] (Google Scholar) • [https://bouwmeestergroup.physics.ucsb.edu Group Website]

Explores quantum optics and cavity quantum electrodynamics with semiconductor quantum dots, optomechanical systems using phononic crystal membranes, and quantum decoherence phenomena.

'''Selected Recent Publications:'''
* ''Single-emitter quantum key distribution over 175 km of fibre with optimised finite key rates'' — '''Nature Communications''' 14, 3573 (2023). [https://doi.org/10.1038/s41467-023-39219-5 DOI]
* ''Phononically shielded multi-wavelength photonic-crystal membrane for cavity quantum optomechanics'' — '''Optics Express''' 33(4), 8203 (2025). [https://doi.org/10.1364/OE.550826 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Bouwmeester_phononic_crystal_membrane_SEM.jpg|thumb|300px|SEM image of a phononic crystal membrane fabricated for optomechanical experiments (silicon nitride or diamond).]]
[[File:2026-04-24_research_Bouwmeester_QD_microcavity_defect.jpg|thumb|300px|Dark-field optical image of a quantum dot microcavity device showing the defect region of a photonic crystal structure.]]
</td>
</tr>
</table>



=== Quantum Photonics Laboratory — Prof. Galan Moody ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=FLokITkAAAAJ Prof. Galan Moody] (Google Scholar) • [https://qpl.ece.ucsb.edu Group Website]

Develops integrated quantum photonic devices on chip-scale platforms, including entangled photon-pair sources from microring resonators, 2D material quantum emitters, and scalable single-photon technologies for quantum networking.

'''Selected Recent Publications:'''
* ''2022 Roadmap on integrated quantum photonics'' — '''Journal of Physics: Photonics''' 4, 012501 (2022). [https://doi.org/10.1088/2515-7647/ac1ef4 DOI]
* ''Defect and strain engineering of monolayer WSe2 enables site-controlled single-photon emission up to 150 K'' — '''Nature Communications''' 12, 3585 (2021). [https://doi.org/10.1038/s41467-021-23709-5 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Moody_QPL_Cisco_entanglement_chip.jpg|thumb|300px|Packaged AlGaAs-on-insulator photonic integrated circuit (PIC) with entangled-pair sources, delivered to Cisco Quantum Labs for quantum networking.]]
[[File:2026-04-24_research_Moody_QPL_AlGaAs_ring_array_2025.jpg|thumb|300px|AlGaAsOI microresonator ring array for high-rate time- and frequency-bin entanglement generation (from PRX Quantum 2025 publication).]]
</td>
</tr>
</table>



=== Quantum Sensing & Imaging Group — Prof. Ania Jayich ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=EKElikcAAAAJ Prof. Ania Bleszynski Jayich] (Google Scholar) • [https://www.10-9lab.com/ Group Website (10−9 Lab)]

Engineers nitrogen-vacancy (NV) centers in diamond for ultra-sensitive nanoscale magnetometry and quantum sensing. Recent breakthroughs leverage many-body quantum dynamics for signal amplification in solid-state quantum sensors.

'''Selected Recent Publications:'''
* ''Signal amplification in a solid-state sensor through asymmetric many-body echo'' — '''Nature''' 646, 68–73 (2025). [https://doi.org/10.1038/s41586-025-09452-7 DOI]
* ''Scalable nanoscale positioning of highly coherent color centers in prefabricated diamond nanostructures'' — '''Nature Communications''' 16 (2025). [https://doi.org/10.1038/s41467-025-64758-4 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Jayich_NV_diamond_scanning_probe.jpg|thumb|300px|Diamond scanning probe tip with a single NV center, used for nanoscale magnetometry (pillar-cantilever geometry).]]
[[File:2026-04-24_research_Jayich_NV_magnetometry_scan.jpg|thumb|300px|Scanning NV magnetometry image showing nanoscale magnetic field mapping of a condensed matter sample.]]
</td>
</tr>
</table>



=== Palmstrom Group — Prof. Chris Palmstrom ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=c-B7OFcAAAAJ Prof. Chris Palmstrom] (Google Scholar) • [https://palmstrom.cnsi.ucsb.edu/ Group Website]

Grows quantum materials by molecular beam epitaxy (MBE), including III-V semiconductor heterostructures, Heusler compounds, and superconductor/semiconductor hybrids for topological quantum computing and superconducting circuits.

'''Selected Recent Publications:'''
* ''Cryogenic Growth of Tantalum Thin Films for Low-Loss Superconducting Circuits'' — '''Physical Review Applied''' 23(3), 034025 (2025). [https://doi.org/10.1103/PhysRevApplied.23.034025 DOI]
* ''Fabrication and Characterization of Low-Loss Al/Si/Al Parallel Plate Capacitors for Superconducting Quantum Information Applications'' — '''npj Quantum Information''' 11 (2025). [https://doi.org/10.1038/s41534-025-00967-5 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Palmstrom_Sn_InAs_Josephson_junction_nanowire.jpeg|thumb|300px|SEM/false-color image of Sn/InAs Josephson junctions on selective area grown nanowires with in-situ shadowed superconductor evaporation.]]
[[File:2026-04-24_research_Palmstrom_CryoMBE_chamber.jpg|thumb|300px|Scienta Omicron EVO 50 Cryo-MBE chamber for growing superconductors at cryogenic substrate temperatures (below 20 K).]]
</td>
</tr>
</table>



=== Young Lab — Prof. Andrea Young ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=EbqS1EoAAAAJ Prof. Andrea Young] (Google Scholar) • [https://www.afylab.com/ Group Website]

Investigates correlated electronic phases in van der Waals heterostructures, including superconductivity, magnetism, and quantum Hall physics in graphene-based systems using nanofabrication and low-temperature transport measurements.

'''Selected Recent Publications:'''
* ''Superconductivity in rhombohedral trilayer graphene'' — '''Nature''' 598, 434–438 (2021). [https://doi.org/10.1038/s41586-021-03926-0 DOI]
* ''Isospin magnetism and spin-polarized superconductivity in Bernal bilayer graphene'' — '''Science''' 375(6582) (2022). [https://doi.org/10.1126/science.abm8386 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Young_nanoSQUID_tip_probe.jpg|thumb|300px|NanoSQUID-on-tip probe and tuning fork assembly used for cryogenic scanning magnetic and thermal imaging of quantum materials.]]
[[File:2026-04-24_research_Young_nanoSQUID_AC_sweep_scan.png|thumb|300px|NanoSQUID scanning image of a van der Waals heterostructure device, showing AC susceptibility mapping (likely graphene fractional quantum Hall system).]]
</td>
</tr>
</table>





== High-Speed Electronics & RF ==

<div style="border-left: 4px solid #d4380d; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Sub-THz transistors, 2D-material nanoelectronics, and advanced CMOS architectures — driving the next generation of wireless communications and computing.''
</div>



=== High Speed Electronics Group — Prof. Mark Rodwell ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=u_C8sbEAAAAJ Prof. Mark Rodwell] (Google Scholar) • [https://web.ece.ucsb.edu/Faculty/rodwell/ Group Website]

Develops InP heterojunction bipolar transistor (HBT) integrated circuits and transceiver modules operating at 100–300 GHz for next-generation sub-THz wireless communication systems with multi-Gbps data rates.

'''Selected Recent Publications:'''
* ''100–300 GHz Wireless: Transistors, ICs, and Systems'' — '''IEEE Microwave Magazine''' (2025). [https://doi.org/10.1109/MMM.2025.3584028 DOI]
* ''A 280 GHz InP HBT Direct-Conversion Receiver with 10.8 dB NF'' — '''IEEE RFIC Symposium''' (2023). [https://doi.org/10.1109/RFIC54547.2023.10186179 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Rodwell_InP_HBT_CrossSection_SEM.jpg|thumb|300px|Cross-sectional SEM of a UCSB InP HBT showing sub-micron emitter, base, and collector mesa layers.]]
[[File:2026-04-24_research_Rodwell_THz_Transceiver_IC.jpg|thumb|300px|130 nm InP HBT transceiver IC layout for 100–300 GHz wireless systems.]]
</td>
</tr>
</table>



=== Nanoelectronics Research Lab — Prof. Kaustav Banerjee ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=zkZqDDcAAAAJ Prof. Kaustav Banerjee] (Google Scholar) • [https://nrl.ece.ucsb.edu/ Group Website]

Pioneers 2D material-based transistor architectures for future CMOS scaling, including 3D transistors with 2D semiconductors, neuromorphic computing platforms using tunnel-FETs, and cryogenic CMOS for quantum computing.

'''Selected Recent Publications:'''
* ''Three-dimensional Transistors with Two-dimensional Semiconductors for Future CMOS Scaling'' — '''Nature Electronics''' (2024). [https://doi.org/10.1038/s41928-024-01289-8 DOI]
* ''An Ultra Energy-efficient Hardware Platform for Neuromorphic Computing Enabled by 2D-TMD Tunnel-FETs'' — '''Nature Communications''' (2024). [https://doi.org/10.1038/s41467-024-46397-3 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Banerjee_Graphene_Kinetic_Inductor.jpg|thumb|300px|Intercalated multilayer graphene on-chip spiral inductors — the first kinetic inductors achieving 1.5× higher inductance density than copper.]]
[[File:2026-04-24_research_Banerjee_2D_3D_NanoplateFET.png|thumb|300px|3D nano-plate FET architecture using 2D WS2 semiconductors in gate-all-around configuration.]]
</td>
</tr>
</table>





== Wide-Bandgap Semiconductors & Power Electronics ==

<div style="border-left: 4px solid #389e0d; padding-left: 12px; margin-bottom: 10px; color: #333;">
''GaN and Ga2O3 devices for solid-state lighting, micro-LEDs, laser diodes, and high-voltage power conversion — from Nobel Prize-winning blue LEDs to next-generation ultra-wide-bandgap power electronics.''
</div>



=== Krishnamoorthy Research Group — Prof. Sriram Krishnamoorthy ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=msxQ2fYAAAAJ Prof. Sriram Krishnamoorthy] (Google Scholar) • [https://sites.google.com/view/krishnamoorthygroup/home Group Website]

Advances ultra-wide-bandgap semiconductor device technology, particularly β-Ga2O3 power electronics including kilovolt-class MOSFETs and Schottky barrier diodes grown by MOCVD for high-voltage, high-efficiency power conversion.

'''Selected Recent Publications:'''
* ''Kilovolt-Class β-Ga2O3 MOSFETs on 1-inch Bulk Substrates'' — '''Applied Physics Letters''' (2024). [https://doi.org/10.1063/5.0191366 DOI]
* ''2.1 kV (001)-β-Ga2O3 Vertical Schottky Barrier Diode with High-k Oxide Field Plate'' — '''Applied Physics Letters''' (2023). [https://doi.org/10.1063/5.0137935 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Krishnamoorthy_Ga2O3_TriGate_MESFET.jpg|thumb|300px|Wide-bandgap semiconductor device research: GaN/Ga2O3 power electronics for high-voltage, high-efficiency power conversion.]]
[[File:2026-04-24_research_Krishnamoorthy_Ga2O3_SiC_MOSFET.jpg|thumb|300px|Advanced materials research at UCSB CNSI for ultra-wide-bandgap semiconductor devices.]]
</td>
</tr>
</table>



=== Solid State Lighting & Electronic Center (SSLEEC) — Prof. Steven DenBaars & Prof. Shuji Nakamura ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''Directors:''' [https://scholar.google.com/citations?user=CO1qY8cAAAAJ Prof. Steven DenBaars] (Google Scholar) • [https://scholar.google.com/citations?user=7Esq3V8AAAAJ Prof. Shuji Nakamura] (Nobel Laureate, 2014 — Google Scholar) • [https://ssleec.ucsb.edu/ SSLEEC Website]

Leads development of III-nitride (InGaN/GaN) optoelectronic devices including micro-LEDs scaled to the single-micron regime for AR/VR displays, edge-emitting laser diodes, and advanced LED architectures with metasurface and distributed Bragg reflector integration.

'''Selected Recent Publications:'''
* ''High External Quantum Efficiency in Ultra-small Amber InGaN MicroLEDs Scaled to 1 μm'' — '''Applied Physics Letters''' (2024). [https://doi.org/10.1063/5.0235915 DOI]
* ''Metasurface Light-Emitting Diodes with Directional and Focused Emission'' — '''Nano Letters''' (2023). [https://doi.org/10.1021/acs.nanolett.3c03272 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_SSLEEC_MicroLED_DBR_SEM.png|thumb|300px|Comparison of 1 μm InGaN/GaN micro-LED with a human hair, demonstrating ultra-small scale device fabrication for AR/VR displays.]]
[[File:2026-04-24_research_SSLEEC_GaN_LED_DeviceStack.jpg|thumb|300px|SSLEEC optical bench with III-nitride LED/laser characterization equipment. Photo: Prof. Shuji Nakamura.]]
</td>
</tr>
</table>





== Advanced Materials & Novel Devices ==

<div style="border-left: 4px solid #d48806; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Topological semimetals, memristive crossbar arrays, plasma nanoscience, and neuromorphic hardware — pushing the boundaries of materials science and unconventional computing architectures.''
</div>



=== Stemmer Research Group — Prof. Susanne Stemmer ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=XFlNLAsAAAAJ Prof. Susanne Stemmer] (Google Scholar) • [https://stemmer.materials.ucsb.edu/ Group Website]

Investigates quantum materials including functional and correlated complex oxides and topological semimetals, with emphasis on thin-film epitaxial growth (MBE), quantum transport, and electronic structure engineering at heterostructure interfaces.

'''Selected Recent Publications:'''
* ''Two-Dimensional Topological Insulator State in Cadmium Arsenide Thin Films'' — '''Physical Review Letters''' 130, 046201 (2023). [https://doi.org/10.1103/PhysRevLett.130.046201 DOI]
* ''Similarity in the Critical Thicknesses for Superconductivity and Ferroelectricity in Strained SrTiO3 Films'' — '''Applied Physics Letters''' (2022). [https://doi.org/10.1063/5.0096834 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Stemmer_Cd3As2_HAADF_STEM.jpg|thumb|300px|Stemmer Research Group banner: MBE-grown quantum materials and topological semimetal thin films.]]
[[File:2026-04-24_research_Stemmer_SrTiO3_QSTEM_Vacancy.jpg|thumb|300px|Advanced characterization tools and discovery science at UCSB CNSI for quantum materials research.]]
</td>
</tr>
</table>



=== Strukov Research Group — Prof. Dmitri Strukov ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=SbPe9WEAAAAJ Prof. Dmitri Strukov] (Google Scholar) • [https://sites.google.com/site/strukov/home Group Website]

Develops novel memristive (resistive switching) devices and hybrid CMOS/memristor circuits for neuromorphic computing, in-memory computing, and hardware accelerators for neural networks and optimization problems.

'''Selected Recent Publications:'''
* ''Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems'' — '''ACS Nano''' (2023). [https://doi.org/10.1021/acsnano.3c03505 DOI]
* ''4K-Memristor Analog-Grade Passive Crossbar Circuit'' — '''Nature Communications''' 12 (2021). [https://doi.org/10.1038/s41467-021-25455-0 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Strukov_4K_Memristor_Crossbar_SEM.png|thumb|300px|SEM of a 64×64 passive memristive crossbar array (4,096 devices) with Ti/Al/TiN electrodes and Al2O3/TiO2-x switching layers.]]
[[File:2026-04-24_research_Strukov_Memristor_Einstein_Conductance.png|thumb|300px|4K-pixel grayscale Einstein image programmed into the memristive crossbar with <4% tuning error, demonstrating analog-grade conductance control.]]
</td>
</tr>
</table>



=== Gordon Lab — Prof. Mike Gordon ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=HUM5shgAAAAJ Prof. Michael J. Gordon] (Google Scholar) • [http://sites.chemengr.ucsb.edu/~mjgordon/research/home.html Group Website]

Works on plasma science and engineering (atmospheric and non-thermal plasmas), catalysis in molten metals for methane pyrolysis and hydrogen production, and nanoscale fabrication including colloidal lithography and micro-LED characterization.

'''Selected Recent Publications:'''
* ''AC Plasmas Directly Excited in Liquid-Phase Hydrocarbons for H2 and Unsaturated C2 Hydrocarbon Production'' — '''Journal of the American Chemical Society''' 147(1) (2025). [https://doi.org/10.1021/jacs.4c11174 DOI]
* ''Dry Reforming of Methane Catalysed by Molten Metal Alloys'' — '''Nature Catalysis''' 3, 83–89 (2020). [https://doi.org/10.1038/s41929-019-0416-2 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Gordon_Plasma_Shadowgraph_Hexane.png|thumb|300px|Laser shadowgraph of plasma discharge in liquid hexane showing streamer propagation and shock waves for hydrogen production.]]
[[File:2026-04-24_research_Gordon_AC_Plasma_Hexane_Timelapse.jpg|thumb|300px|Gordon Lab research: Plasma science, catalysis, and nanoscale fabrication for hydrogen production and sustainable chemistry.]]
</td>
</tr>
</table>





== Microfluidics & MEMS ==

<div style="border-left: 4px solid #08979c; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Nanofluidic transport, lab-on-chip biosensors, and microfabricated biomedical devices — bridging nanofabrication with biological and chemical applications.''
</div>



=== Pennathur Lab — Prof. Sumita Pennathur ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=dVbZMA0AAAAJ Prof. Sumita Pennathur] (Google Scholar) • [https://nanolab.engineering.ucsb.edu/ Group Website]

Studies electrokinetic transport in nanofluidic channels, ionic current rectification in bipolar nanochannels, and the design of nanofluidic diodes and biosensors, combining experimental micro/nanofabrication with computational modeling.

'''Selected Recent Publications:'''
* ''Coupling Charge-Regulated Interfacial Chemistry to Electrokinetic Ion Transport in Bipolar SiO2–Al2O3 Nanofluidic Diodes'' — '''Advanced Materials Interfaces''' (2024). [https://doi.org/10.1002/admi.202400495 DOI]
* ''Nanofluidic Diodes Based on Asymmetric Bio-Inspired Surface Coatings in Straight Glass Nanochannels'' — '''Faraday Discussions''' (2023). [https://doi.org/10.1039/D3FD00074E DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Pennathur_Nanochannel_Embedded_Electrode.png|thumb|300px|Nanofluidic channel with embedded electrodes for electric double layer modulation and electroosmotic flow control.]]
[[File:2026-04-24_research_Pennathur_Silicon_Microneedle_SEM.png|thumb|300px|Silicon microneedle array fabricated using MEMS wet etching techniques for minimally invasive biofluid extraction.]]
</td>
</tr>
</table>





== Astronomical Instrumentation ==

<div style="border-left: 4px solid #531dab; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Superconducting photon-counting detectors for ground-based astronomy — fabricating the cameras that image exoplanets.''
</div>



=== Mazin Laboratory — Prof. Ben Mazin ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [http://web.physics.ucsb.edu/~bmazin/index.html Prof. Benjamin Mazin] • [https://inspirehep.net/authors/1037976 INSPIRE-HEP Publications] • [http://web.physics.ucsb.edu/~bmazin/publications/ Lab Publication List]

Pioneers Microwave Kinetic Inductance Detectors (MKIDs) — superconducting photon-counting sensors with zero read noise that measure each photon's energy, arrival time, and position. Deploys MKID-based cameras (MEC, XKID) at major telescopes for direct imaging of exoplanets.

'''Selected Recent Publications:'''
* ''Characterization of Photon Arrival Timing Jitter in Microwave Kinetic Inductance Detector Arrays'' — '''Applied Physics Letters''' (2024). [https://doi.org/10.1063/5.0190172 DOI]
* ''Characterizing the Dark Count Rate of a Large-Format MKID Array'' — '''Optics Express''' 31(6), 10775 (2023). [https://doi.org/10.1364/OE.485003 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24_research_Mazin_MKID_20K_Array_Package.jpg|thumb|300px|Optical/near-IR MKID array — the revolutionary photon-counting detector technology at the core of Mazin Lab research.]]
[[File:2026-04-24_research_Mazin_MKID_10K_Array_Zoom.png|thumb|300px|10,000-pixel MKID array in gold sample box with progressive zoom-ins showing pixel grid and individual lumped-element resonator structures.]]
</td>
</tr>
</table>





----

<div style="border: 1px solid #d9d9d9; border-radius: 6px; padding: 16px; margin-top: 20px; background: #fafafa;">
== Publication Archives ==

* [[PubList2018|'''2018 Publications''']]
* [[Older Publications|'''Earlier Publications''']]
* [[Template:Publications|Select Publications]] — ''A selection of publications that utilized the UCSB NanoFab''

== Research Presentations ==

* [[Photonics Presentations|Photonics]]
* [[Electronics Presentations|Electronics]]
* [[THz Physics Presentations|THz Physics]]

== Research Image Galleries ==

* [[Photonics Pictures|Photonics]] • [[Electronics Pictures|Electronics]] • [[MEMS Pictures|MEMS]] • [[Physics Pictures|Physics]] • [[Fluidics Pictures|Fluidics]]
</div>

[[Category:Research]]
[[Category:Publications]]
[[Category:Nanofabrication]]
__FORCETOC__

Research

2026-05-19T16:39:37Z

John d: pasted Cursor output, maybe broken images

<div style="border: 2px solid #003660; border-radius: 8px; padding: 20px; margin-bottom: 20px; background: linear-gradient(135deg, #f8f9fa 0%, #e8eef5 100%);">
<div style="font-size: 1.6em; font-weight: bold; color: #003660; margin-bottom: 8px;">UCSB Nanofabrication Facility — Research Groups & Publications</div>
<div style="font-size: 1.05em; color: #444;">A curated directory of research groups utilizing the [https://www.nanotech.ucsb.edu/ UCSB Nanofab], organized by discipline. Each section highlights recent high-impact publications and representative research imagery.</div>
<div style="margin-top: 10px; font-size: 0.9em; color: #666;">''Last updated: April 2026''</div>
</div>

__TOC__





== Photonics and Integrated Optics ==

<div style="border-left: 4px solid #0077b6; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Silicon photonics, III-V integration, optical communications, nanophotonic devices, and metasurfaces — enabling next-generation data links, sensing, and on-chip light manipulation.''
</div>



=== Optical Communications & Photonic Integration Group — Prof. Daniel Blumenthal ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=4yjw1ecAAAAJ Prof. Daniel Blumenthal] (Google Scholar) • [https://ocpi.ece.ucsb.edu/ Group Website]

Develops ultra-low-loss silicon nitride (Si3N4) photonic integrated circuits for stimulated Brillouin lasers, optical gyroscopes, optical frequency synthesis, and emerging atom-photonic quantum integration on chip.

'''Selected Recent Publications:'''
* ''Integrated optical frequency division for microwave and mmWave generation'' — '''Nature''' 627, 540–545 (2024). [https://doi.org/10.1038/s41586-024-07057-0 DOI]
* ''Integrated photonic molecule Brillouin laser with a high-power sub-100-mHz fundamental linewidth'' — '''Optics Letters''' 49(1), 45–48 (2024). [https://doi.org/10.1364/OL.503126 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Blumenthal_SiN_coil_resonator.jpg|thumb|300px|Ultra-low-loss silicon nitride photonic coil resonator chip used for Brillouin lasers and high-Q resonators.]]
[[File:2026-04-24 images/Blumenthal_PZT_SiN_microcomb.png|thumb|300px|PZT-integrated silicon nitride microcomb resonator for chip-based optical frequency division.]]
</td>
</tr>
</table>



=== Silicon Photonics, AIM Photonics & Institute for Energy Efficiency — Prof. John Bowers ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=c6rbVa0AAAAJ Prof. John Bowers] (Google Scholar) • [https://siliconphotonics.ece.ucsb.edu/ Silicon Photonics] • [https://aim.ucsb.edu AIM Photonics] • [https://iee.ucsb.edu IEE]

Leads research on heterogeneous integration of III-V materials on silicon for lasers, amplifiers, and modulators, as well as advanced silicon photonic platforms for datacom, telecom, and ultra-narrow-linewidth laser sources.

'''Selected Recent Publications:'''
* ''Roadmapping the next generation of silicon photonics'' — '''Nature Communications''' 15, 751 (2024). [https://doi.org/10.1038/s41467-024-44750-0 DOI]
* ''Lithium niobate photonics: Unlocking the electromagnetic spectrum'' — '''Science''' 379(6627) (2023). [https://doi.org/10.1126/science.abj4396 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Bowers_3D_PIC_integration.png|thumb|300px|3D photonic integrated circuit: heterogeneous III-V on silicon architecture without an isolator (Nature, 2023).]]
[[File:2026-04-24 images/Bowers_racetrack_resonator.jpg|thumb|300px|Novel conjoined racetrack resonator geometry for silicon photonics.]]
</td>
</tr>
</table>



=== Integrated Photonics Laboratory — Prof. Jonathan Klamkin ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=vR_K3XYAAAAJ Prof. Jonathan Klamkin] (Google Scholar) • [https://web.ece.ucsb.edu/ipl Group Website]

Specializes in III-V photonic integrated circuits for free-space optical communications, LiDAR, microwave photonics, and monolithic integration of III-V quantum dot lasers on silicon via selective area heteroepitaxy.

'''Selected Recent Publications:'''
* ''Selective area heteroepitaxy of low dislocation density antiphase boundary free GaAs microridges on flat-bottom (001) Si for integrated silicon photonics'' — '''Applied Physics Letters''' 118, 122106 (2021). [https://doi.org/10.1063/5.0043027 DOI]
* ''Towards fully monolithic silicon-based integrated photonics: MOCVD grown lasers on silicon by blanket and selective area heteroepitaxy'' — '''Proc. SPIE''' (Photonics West, 2022). [https://doi.org/10.1117/12.2610644 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Klamkin_3D_hybrid_SiPh.jpg|thumb|300px|3D hybrid integrated silicon photonics platform merging InP and GaAs devices with SiPh.]]
[[File:2026-04-24 images/Klamkin_free_space_optical_comms.jpg|thumb|300px|Laser communication terminal for free-space optical links (NASA-funded research).]]
</td>
</tr>
</table>



=== Schow Lab — Prof. Clint Schow ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=cVY3g4cAAAAJ Prof. Clint Schow] (Google Scholar) • [https://schow.ece.ucsb.edu/ Group Website]

Develops energy-efficient optical interconnects for data centers, with emphasis on analog coherent detection architectures that eliminate power-hungry DSP, leveraging silicon photonics and co-packaged optics.

'''Selected Recent Publications:'''
* ''A Monolithic O-Band Coherent Optical Receiver for Energy-Efficient Links'' — '''IEEE Journal of Solid-State Circuits''' 59(5) (2024). [https://doi.org/10.1109/JSSC.2023.3339494 DOI]
* ''Analog Coherent Detection for Energy Efficient Intra-Data Center Links at 200 Gbps Per Wavelength'' — '''Journal of Lightwave Technology''' 39(2) (2021). [https://doi.org/10.1109/JLT.2020.3029788 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Schow_coherent_optical_links.jpg|thumb|300px|Low-power coherent optical links for datacenter interconnects.]]
[[File:2026-04-24 images/Schow_cryogenic_optical_links.jpg|thumb|300px|Cryogenic silicon photonic optical links for classical and quantum computing.]]
</td>
</tr>
</table>



=== Schuller Lab — Prof. Jon Schuller ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=Ff90s74AAAAJ Prof. Jon Schuller] (Google Scholar) • [https://schuller.cnsi.ucsb.edu/ Group Website]

Investigates light-matter interactions at the nanoscale, designing dielectric and semiconductor metasurfaces for directional light emission, magneto-optical traps, and active reconfigurable photonic devices.

'''Selected Recent Publications:'''
* ''High efficiency large-angle polarization-insensitive retroreflecting metasurface for magneto-optical traps'' — '''Applied Physics Letters''' 124, 251704 (2024). [https://doi.org/10.1063/5.0210124 DOI]
* ''Optimizing Polarization Selective Unidirectional Photoluminescence from Phased-Array Metasurfaces'' — '''Advanced Optical Materials''' (2024). [https://doi.org/10.1002/adom.202303186 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Schuller_crystal_microstructures.jpg|thumb|300px|Hybrid organic/inorganic crystalline microstructures with quantum-confinement-induced red luminescence.]]
[[File:2026-04-24 images/Schuller_metasurface_beam_deflector.jpg|thumb|300px|Tunable dielectric metasurface beam deflector for engineered light steering.]]
</td>
</tr>
</table>





== Quantum Computing, Quantum Sensing & Quantum Materials ==

<div style="border-left: 4px solid #7b2d8e; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Quantum optics, entangled photon sources, NV-center sensing, topological qubits, and correlated electron systems — building the hardware foundations for quantum information science.''
</div>



=== Quantum Optics & Quantum Information Group — Prof. Dirk Bouwmeester ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=r92BS5wAAAAJ Prof. Dirk Bouwmeester] (Google Scholar) • [https://bouwmeestergroup.physics.ucsb.edu Group Website]

Explores quantum optics and cavity quantum electrodynamics with semiconductor quantum dots, optomechanical systems using phononic crystal membranes, and quantum decoherence phenomena.

'''Selected Recent Publications:'''
* ''Single-emitter quantum key distribution over 175 km of fibre with optimised finite key rates'' — '''Nature Communications''' 14, 3573 (2023). [https://doi.org/10.1038/s41467-023-39219-5 DOI]
* ''Phononically shielded multi-wavelength photonic-crystal membrane for cavity quantum optomechanics'' — '''Optics Express''' 33(4), 8203 (2025). [https://doi.org/10.1364/OE.550826 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Bouwmeester_phononic_crystal_membrane_SEM.jpg|thumb|300px|SEM image of a phononic crystal membrane fabricated for optomechanical experiments (silicon nitride or diamond).]]
[[File:2026-04-24 images/Bouwmeester_QD_microcavity_defect.jpg|thumb|300px|Dark-field optical image of a quantum dot microcavity device showing the defect region of a photonic crystal structure.]]
</td>
</tr>
</table>



=== Quantum Photonics Laboratory — Prof. Galan Moody ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=FLokITkAAAAJ Prof. Galan Moody] (Google Scholar) • [https://qpl.ece.ucsb.edu Group Website]

Develops integrated quantum photonic devices on chip-scale platforms, including entangled photon-pair sources from microring resonators, 2D material quantum emitters, and scalable single-photon technologies for quantum networking.

'''Selected Recent Publications:'''
* ''2022 Roadmap on integrated quantum photonics'' — '''Journal of Physics: Photonics''' 4, 012501 (2022). [https://doi.org/10.1088/2515-7647/ac1ef4 DOI]
* ''Defect and strain engineering of monolayer WSe2 enables site-controlled single-photon emission up to 150 K'' — '''Nature Communications''' 12, 3585 (2021). [https://doi.org/10.1038/s41467-021-23709-5 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Moody_QPL_Cisco_entanglement_chip.jpg|thumb|300px|Packaged AlGaAs-on-insulator photonic integrated circuit (PIC) with entangled-pair sources, delivered to Cisco Quantum Labs for quantum networking.]]
[[File:2026-04-24 images/Moody_QPL_AlGaAs_ring_array_2025.jpg|thumb|300px|AlGaAsOI microresonator ring array for high-rate time- and frequency-bin entanglement generation (from PRX Quantum 2025 publication).]]
</td>
</tr>
</table>



=== Quantum Sensing & Imaging Group — Prof. Ania Jayich ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=EKElikcAAAAJ Prof. Ania Bleszynski Jayich] (Google Scholar) • [https://www.10-9lab.com/ Group Website (10−9 Lab)]

Engineers nitrogen-vacancy (NV) centers in diamond for ultra-sensitive nanoscale magnetometry and quantum sensing. Recent breakthroughs leverage many-body quantum dynamics for signal amplification in solid-state quantum sensors.

'''Selected Recent Publications:'''
* ''Signal amplification in a solid-state sensor through asymmetric many-body echo'' — '''Nature''' 646, 68–73 (2025). [https://doi.org/10.1038/s41586-025-09452-7 DOI]
* ''Scalable nanoscale positioning of highly coherent color centers in prefabricated diamond nanostructures'' — '''Nature Communications''' 16 (2025). [https://doi.org/10.1038/s41467-025-64758-4 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Jayich_NV_diamond_scanning_probe.jpg|thumb|300px|Diamond scanning probe tip with a single NV center, used for nanoscale magnetometry (pillar-cantilever geometry).]]
[[File:2026-04-24 images/Jayich_NV_magnetometry_scan.jpg|thumb|300px|Scanning NV magnetometry image showing nanoscale magnetic field mapping of a condensed matter sample.]]
</td>
</tr>
</table>



=== Palmstrom Group — Prof. Chris Palmstrom ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=c-B7OFcAAAAJ Prof. Chris Palmstrom] (Google Scholar) • [https://palmstrom.cnsi.ucsb.edu/ Group Website]

Grows quantum materials by molecular beam epitaxy (MBE), including III-V semiconductor heterostructures, Heusler compounds, and superconductor/semiconductor hybrids for topological quantum computing and superconducting circuits.

'''Selected Recent Publications:'''
* ''Cryogenic Growth of Tantalum Thin Films for Low-Loss Superconducting Circuits'' — '''Physical Review Applied''' 23(3), 034025 (2025). [https://doi.org/10.1103/PhysRevApplied.23.034025 DOI]
* ''Fabrication and Characterization of Low-Loss Al/Si/Al Parallel Plate Capacitors for Superconducting Quantum Information Applications'' — '''npj Quantum Information''' 11 (2025). [https://doi.org/10.1038/s41534-025-00967-5 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Palmstrom_Sn_InAs_Josephson_junction_nanowire.jpeg|thumb|300px|SEM/false-color image of Sn/InAs Josephson junctions on selective area grown nanowires with in-situ shadowed superconductor evaporation.]]
[[File:2026-04-24 images/Palmstrom_CryoMBE_chamber.jpg|thumb|300px|Scienta Omicron EVO 50 Cryo-MBE chamber for growing superconductors at cryogenic substrate temperatures (below 20 K).]]
</td>
</tr>
</table>



=== Young Lab — Prof. Andrea Young ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=EbqS1EoAAAAJ Prof. Andrea Young] (Google Scholar) • [https://www.afylab.com/ Group Website]

Investigates correlated electronic phases in van der Waals heterostructures, including superconductivity, magnetism, and quantum Hall physics in graphene-based systems using nanofabrication and low-temperature transport measurements.

'''Selected Recent Publications:'''
* ''Superconductivity in rhombohedral trilayer graphene'' — '''Nature''' 598, 434–438 (2021). [https://doi.org/10.1038/s41586-021-03926-0 DOI]
* ''Isospin magnetism and spin-polarized superconductivity in Bernal bilayer graphene'' — '''Science''' 375(6582) (2022). [https://doi.org/10.1126/science.abm8386 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Young_nanoSQUID_tip_probe.jpg|thumb|300px|NanoSQUID-on-tip probe and tuning fork assembly used for cryogenic scanning magnetic and thermal imaging of quantum materials.]]
[[File:2026-04-24 images/Young_nanoSQUID_AC_sweep_scan.png|thumb|300px|NanoSQUID scanning image of a van der Waals heterostructure device, showing AC susceptibility mapping (likely graphene fractional quantum Hall system).]]
</td>
</tr>
</table>





== High-Speed Electronics & RF ==

<div style="border-left: 4px solid #d4380d; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Sub-THz transistors, 2D-material nanoelectronics, and advanced CMOS architectures — driving the next generation of wireless communications and computing.''
</div>



=== High Speed Electronics Group — Prof. Mark Rodwell ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=u_C8sbEAAAAJ Prof. Mark Rodwell] (Google Scholar) • [https://web.ece.ucsb.edu/Faculty/rodwell/ Group Website]

Develops InP heterojunction bipolar transistor (HBT) integrated circuits and transceiver modules operating at 100–300 GHz for next-generation sub-THz wireless communication systems with multi-Gbps data rates.

'''Selected Recent Publications:'''
* ''100–300 GHz Wireless: Transistors, ICs, and Systems'' — '''IEEE Microwave Magazine''' (2025). [https://doi.org/10.1109/MMM.2025.3584028 DOI]
* ''A 280 GHz InP HBT Direct-Conversion Receiver with 10.8 dB NF'' — '''IEEE RFIC Symposium''' (2023). [https://doi.org/10.1109/RFIC54547.2023.10186179 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Rodwell_InP_HBT_CrossSection_SEM.jpg|thumb|300px|Cross-sectional SEM of a UCSB InP HBT showing sub-micron emitter, base, and collector mesa layers.]]
[[File:2026-04-24 images/Rodwell_THz_Transceiver_IC.jpg|thumb|300px|130 nm InP HBT transceiver IC layout for 100–300 GHz wireless systems.]]
</td>
</tr>
</table>



=== Nanoelectronics Research Lab — Prof. Kaustav Banerjee ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=zkZqDDcAAAAJ Prof. Kaustav Banerjee] (Google Scholar) • [https://nrl.ece.ucsb.edu/ Group Website]

Pioneers 2D material-based transistor architectures for future CMOS scaling, including 3D transistors with 2D semiconductors, neuromorphic computing platforms using tunnel-FETs, and cryogenic CMOS for quantum computing.

'''Selected Recent Publications:'''
* ''Three-dimensional Transistors with Two-dimensional Semiconductors for Future CMOS Scaling'' — '''Nature Electronics''' (2024). [https://doi.org/10.1038/s41928-024-01289-8 DOI]
* ''An Ultra Energy-efficient Hardware Platform for Neuromorphic Computing Enabled by 2D-TMD Tunnel-FETs'' — '''Nature Communications''' (2024). [https://doi.org/10.1038/s41467-024-46397-3 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Banerjee_Graphene_Kinetic_Inductor.jpg|thumb|300px|Intercalated multilayer graphene on-chip spiral inductors — the first kinetic inductors achieving 1.5× higher inductance density than copper.]]
[[File:2026-04-24 images/Banerjee_2D_3D_NanoplateFET.png|thumb|300px|3D nano-plate FET architecture using 2D WS2 semiconductors in gate-all-around configuration.]]
</td>
</tr>
</table>





== Wide-Bandgap Semiconductors & Power Electronics ==

<div style="border-left: 4px solid #389e0d; padding-left: 12px; margin-bottom: 10px; color: #333;">
''GaN and Ga2O3 devices for solid-state lighting, micro-LEDs, laser diodes, and high-voltage power conversion — from Nobel Prize-winning blue LEDs to next-generation ultra-wide-bandgap power electronics.''
</div>



=== Krishnamoorthy Research Group — Prof. Sriram Krishnamoorthy ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=msxQ2fYAAAAJ Prof. Sriram Krishnamoorthy] (Google Scholar) • [https://sites.google.com/view/krishnamoorthygroup/home Group Website]

Advances ultra-wide-bandgap semiconductor device technology, particularly β-Ga2O3 power electronics including kilovolt-class MOSFETs and Schottky barrier diodes grown by MOCVD for high-voltage, high-efficiency power conversion.

'''Selected Recent Publications:'''
* ''Kilovolt-Class β-Ga2O3 MOSFETs on 1-inch Bulk Substrates'' — '''Applied Physics Letters''' (2024). [https://doi.org/10.1063/5.0191366 DOI]
* ''2.1 kV (001)-β-Ga2O3 Vertical Schottky Barrier Diode with High-k Oxide Field Plate'' — '''Applied Physics Letters''' (2023). [https://doi.org/10.1063/5.0137935 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Krishnamoorthy_Ga2O3_TriGate_MESFET.jpg|thumb|300px|Wide-bandgap semiconductor device research: GaN/Ga2O3 power electronics for high-voltage, high-efficiency power conversion.]]
[[File:2026-04-24 images/Krishnamoorthy_Ga2O3_SiC_MOSFET.jpg|thumb|300px|Advanced materials research at UCSB CNSI for ultra-wide-bandgap semiconductor devices.]]
</td>
</tr>
</table>



=== Solid State Lighting & Electronic Center (SSLEEC) — Prof. Steven DenBaars & Prof. Shuji Nakamura ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''Directors:''' [https://scholar.google.com/citations?user=CO1qY8cAAAAJ Prof. Steven DenBaars] (Google Scholar) • [https://scholar.google.com/citations?user=7Esq3V8AAAAJ Prof. Shuji Nakamura] (Nobel Laureate, 2014 — Google Scholar) • [https://ssleec.ucsb.edu/ SSLEEC Website]

Leads development of III-nitride (InGaN/GaN) optoelectronic devices including micro-LEDs scaled to the single-micron regime for AR/VR displays, edge-emitting laser diodes, and advanced LED architectures with metasurface and distributed Bragg reflector integration.

'''Selected Recent Publications:'''
* ''High External Quantum Efficiency in Ultra-small Amber InGaN MicroLEDs Scaled to 1 μm'' — '''Applied Physics Letters''' (2024). [https://doi.org/10.1063/5.0235915 DOI]
* ''Metasurface Light-Emitting Diodes with Directional and Focused Emission'' — '''Nano Letters''' (2023). [https://doi.org/10.1021/acs.nanolett.3c03272 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/SSLEEC_MicroLED_DBR_SEM.png|thumb|300px|Comparison of 1 μm InGaN/GaN micro-LED with a human hair, demonstrating ultra-small scale device fabrication for AR/VR displays.]]
[[File:2026-04-24 images/SSLEEC_GaN_LED_DeviceStack.jpg|thumb|300px|SSLEEC optical bench with III-nitride LED/laser characterization equipment. Photo: Prof. Shuji Nakamura.]]
</td>
</tr>
</table>





== Advanced Materials & Novel Devices ==

<div style="border-left: 4px solid #d48806; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Topological semimetals, memristive crossbar arrays, plasma nanoscience, and neuromorphic hardware — pushing the boundaries of materials science and unconventional computing architectures.''
</div>



=== Stemmer Research Group — Prof. Susanne Stemmer ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=XFlNLAsAAAAJ Prof. Susanne Stemmer] (Google Scholar) • [https://stemmer.materials.ucsb.edu/ Group Website]

Investigates quantum materials including functional and correlated complex oxides and topological semimetals, with emphasis on thin-film epitaxial growth (MBE), quantum transport, and electronic structure engineering at heterostructure interfaces.

'''Selected Recent Publications:'''
* ''Two-Dimensional Topological Insulator State in Cadmium Arsenide Thin Films'' — '''Physical Review Letters''' 130, 046201 (2023). [https://doi.org/10.1103/PhysRevLett.130.046201 DOI]
* ''Similarity in the Critical Thicknesses for Superconductivity and Ferroelectricity in Strained SrTiO3 Films'' — '''Applied Physics Letters''' (2022). [https://doi.org/10.1063/5.0096834 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Stemmer_Cd3As2_HAADF_STEM.jpg|thumb|300px|Stemmer Research Group banner: MBE-grown quantum materials and topological semimetal thin films.]]
[[File:2026-04-24 images/Stemmer_SrTiO3_QSTEM_Vacancy.jpg|thumb|300px|Advanced characterization tools and discovery science at UCSB CNSI for quantum materials research.]]
</td>
</tr>
</table>



=== Strukov Research Group — Prof. Dmitri Strukov ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=SbPe9WEAAAAJ Prof. Dmitri Strukov] (Google Scholar) • [https://sites.google.com/site/strukov/home Group Website]

Develops novel memristive (resistive switching) devices and hybrid CMOS/memristor circuits for neuromorphic computing, in-memory computing, and hardware accelerators for neural networks and optimization problems.

'''Selected Recent Publications:'''
* ''Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems'' — '''ACS Nano''' (2023). [https://doi.org/10.1021/acsnano.3c03505 DOI]
* ''4K-Memristor Analog-Grade Passive Crossbar Circuit'' — '''Nature Communications''' 12 (2021). [https://doi.org/10.1038/s41467-021-25455-0 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Strukov_4K_Memristor_Crossbar_SEM.png|thumb|300px|SEM of a 64×64 passive memristive crossbar array (4,096 devices) with Ti/Al/TiN electrodes and Al2O3/TiO2-x switching layers.]]
[[File:2026-04-24 images/Strukov_Memristor_Einstein_Conductance.png|thumb|300px|4K-pixel grayscale Einstein image programmed into the memristive crossbar with <4% tuning error, demonstrating analog-grade conductance control.]]
</td>
</tr>
</table>



=== Gordon Lab — Prof. Mike Gordon ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=HUM5shgAAAAJ Prof. Michael J. Gordon] (Google Scholar) • [http://sites.chemengr.ucsb.edu/~mjgordon/research/home.html Group Website]

Works on plasma science and engineering (atmospheric and non-thermal plasmas), catalysis in molten metals for methane pyrolysis and hydrogen production, and nanoscale fabrication including colloidal lithography and micro-LED characterization.

'''Selected Recent Publications:'''
* ''AC Plasmas Directly Excited in Liquid-Phase Hydrocarbons for H2 and Unsaturated C2 Hydrocarbon Production'' — '''Journal of the American Chemical Society''' 147(1) (2025). [https://doi.org/10.1021/jacs.4c11174 DOI]
* ''Dry Reforming of Methane Catalysed by Molten Metal Alloys'' — '''Nature Catalysis''' 3, 83–89 (2020). [https://doi.org/10.1038/s41929-019-0416-2 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Gordon_Plasma_Shadowgraph_Hexane.png|thumb|300px|Laser shadowgraph of plasma discharge in liquid hexane showing streamer propagation and shock waves for hydrogen production.]]
[[File:2026-04-24 images/Gordon_AC_Plasma_Hexane_Timelapse.jpg|thumb|300px|Gordon Lab research: Plasma science, catalysis, and nanoscale fabrication for hydrogen production and sustainable chemistry.]]
</td>
</tr>
</table>





== Microfluidics & MEMS ==

<div style="border-left: 4px solid #08979c; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Nanofluidic transport, lab-on-chip biosensors, and microfabricated biomedical devices — bridging nanofabrication with biological and chemical applications.''
</div>



=== Pennathur Lab — Prof. Sumita Pennathur ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [https://scholar.google.com/citations?user=dVbZMA0AAAAJ Prof. Sumita Pennathur] (Google Scholar) • [https://nanolab.engineering.ucsb.edu/ Group Website]

Studies electrokinetic transport in nanofluidic channels, ionic current rectification in bipolar nanochannels, and the design of nanofluidic diodes and biosensors, combining experimental micro/nanofabrication with computational modeling.

'''Selected Recent Publications:'''
* ''Coupling Charge-Regulated Interfacial Chemistry to Electrokinetic Ion Transport in Bipolar SiO2–Al2O3 Nanofluidic Diodes'' — '''Advanced Materials Interfaces''' (2024). [https://doi.org/10.1002/admi.202400495 DOI]
* ''Nanofluidic Diodes Based on Asymmetric Bio-Inspired Surface Coatings in Straight Glass Nanochannels'' — '''Faraday Discussions''' (2023). [https://doi.org/10.1039/D3FD00074E DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Pennathur_Nanochannel_Embedded_Electrode.png|thumb|300px|Nanofluidic channel with embedded electrodes for electric double layer modulation and electroosmotic flow control.]]
[[File:2026-04-24 images/Pennathur_Silicon_Microneedle_SEM.png|thumb|300px|Silicon microneedle array fabricated using MEMS wet etching techniques for minimally invasive biofluid extraction.]]
</td>
</tr>
</table>





== Astronomical Instrumentation ==

<div style="border-left: 4px solid #531dab; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Superconducting photon-counting detectors for ground-based astronomy — fabricating the cameras that image exoplanets.''
</div>



=== Mazin Laboratory — Prof. Ben Mazin ===

<table style="width: 100%; border-collapse: collapse;">
<tr>
<td style="vertical-align: top; padding-right: 15px; width: 70%;">
'''PI:''' [http://web.physics.ucsb.edu/~bmazin/index.html Prof. Benjamin Mazin] • [https://inspirehep.net/authors/1037976 INSPIRE-HEP Publications] • [http://web.physics.ucsb.edu/~bmazin/publications/ Lab Publication List]

Pioneers Microwave Kinetic Inductance Detectors (MKIDs) — superconducting photon-counting sensors with zero read noise that measure each photon's energy, arrival time, and position. Deploys MKID-based cameras (MEC, XKID) at major telescopes for direct imaging of exoplanets.

'''Selected Recent Publications:'''
* ''Characterization of Photon Arrival Timing Jitter in Microwave Kinetic Inductance Detector Arrays'' — '''Applied Physics Letters''' (2024). [https://doi.org/10.1063/5.0190172 DOI]
* ''Characterizing the Dark Count Rate of a Large-Format MKID Array'' — '''Optics Express''' 31(6), 10775 (2023). [https://doi.org/10.1364/OE.485003 DOI]
</td>
<td style="vertical-align: top; width: 30%;">
[[File:2026-04-24 images/Mazin_MKID_20K_Array_Package.jpg|thumb|300px|Optical/near-IR MKID array — the revolutionary photon-counting detector technology at the core of Mazin Lab research.]]
[[File:2026-04-24 images/Mazin_MKID_10K_Array_Zoom.png|thumb|300px|10,000-pixel MKID array in gold sample box with progressive zoom-ins showing pixel grid and individual lumped-element resonator structures.]]
</td>
</tr>
</table>





----

<div style="border: 1px solid #d9d9d9; border-radius: 6px; padding: 16px; margin-top: 20px; background: #fafafa;">
== Publication Archives ==

* [[PubList2018|'''2018 Publications''']]
* [[Older Publications|'''Earlier Publications''']]
* [[Template:Publications|Select Publications]] — ''A selection of publications that utilized the UCSB NanoFab''

== Research Presentations ==

* [[Photonics Presentations|Photonics]]
* [[Electronics Presentations|Electronics]]
* [[THz Physics Presentations|THz Physics]]

== Research Image Galleries ==

* [[Photonics Pictures|Photonics]] • [[Electronics Pictures|Electronics]] • [[MEMS Pictures|MEMS]] • [[Physics Pictures|Physics]] • [[Fluidics Pictures|Fluidics]]
</div>

[[Category:Research]]
[[Category:Publications]]
[[Category:Nanofabrication]]
__FORCETOC__

Research OLD 2026 05 19

2026-05-19T16:37:44Z

John d: John d moved page Research to Research OLD 2026 05 19 without leaving a redirect: replacing with new version, keeping this in case we need it

==Research Groups==

'''<big>To find the most up-to-date publications and a history of research, please see the group websites below</big>'''

===[https://nrl.ece.ucsb.edu/ Nanoelectronics Research Lab, PI Prof. Kaustav Banerjee]===

===[https://ocpi.ece.ucsb.edu Optical Communications and Photonic Integration Group, PI Prof. Daniel Blumenthal]===
===[https://bouwmeestergroup.physics.ucsb.edu Quantum optics and quantum information group, UCSB Physics, PI Prof. Dirk Bouwmeester]===
===[https://iee.ucsb.edu Institute for Energy Efficiency, Director Prof. John Bowers]===
===[https://aim.ucsb.edu AIM Photonics - West Coast, Director Prof. John Bowers]===
===[https://siliconphotonics.ece.ucsb.edu Silicon Photonics Center, PI Prof. John Bowers]===

===[https://ssleec.ucsb.edu/ Solid State Lighting and Electronic Center, Director Prof. Steven DenBaars, Research Director Prof. Shuji Nakamura]===
===[https://web.ece.ucsb.edu/ipl Integrated Photonics Laboratory, PI Prof. Jonathan Klamkin]===
===[http://web.physics.ucsb.edu/~bmazin/index.html Mazin Laboratory, PI Prof. Ben Mazin]===
===[https://qpl.ece.ucsb.edu Quantum Photonics Laboratory, PI Prof. Galan Moody]===
===[https://web.ece.ucsb.edu/Faculty/rodwell/ High Speed Electronics Group, PI Prof. Mark Rodwell]===
===[https://www.10-9lab.com/ Quantum Sensing and Imaging Group, PI Prof. Ania Jayich]===
===[https://palmstrom.cnsi.ucsb.edu/ Chris Palmstrom Group, PI Prof. Chris Palmstrom]===

===[https://sites.google.com/view/krishnamoorthygroup/home Krishnamoorthy Research Group, PI Prof. Sriram Krishnamoorthy]===

===[https://www.afylab.com/ Young Lab, PI Prof. Andrea Young]===
===[https://schuller.cnsi.ucsb.edu/ Schuller Lab, PI Prof. Jon Schuller]===
===[https://schow.ece.ucsb.edu/ Schow Lab, PI Prof. Clint Schow]===
===[https://nanolab.engineering.ucsb.edu/ Pennathur Lab, PI Prof. Sumita Pennathur]===
===[https://stemmer.materials.ucsb.edu/ Stemmer Research Group, PI Prof. Susanne Stemmer]===
===[https://sites.google.com/site/strukov/home Strukov Research Group, PI Prof. Dmitri Strukov]===
===[http://sites.chemengr.ucsb.edu/~mjgordon/research/home.html Gordon Lab, PI Prof. Mike Gordon]===

==Publication Lists==

===[[Template:Publications|Select Publications]]===

*''A selection of recent and relevant publications that utilized the UCSB NanoFab.''
*To see more complete publication lists, please visit group websites linked above

[[PubList2018|'''2018 Publications''']]

'''[[Older Publications|Earlier Publications]]'''

==Research Presentations==

===[[Photonics Presentations|Photonics]]===

===[[Electronics Presentations|Electronics]]===

===[[THz Physics Presentations|THz Physics]]===

==Pictures==

===[[Photonics Pictures|Photonics]]===

===[[Electronics Pictures|Electronics]]===

===[[MEMS Pictures|MEMS]]===

===[[Physics Pictures|Physics]]===

===[[Fluidics Pictures|Fluidics]]===
__FORCETOC__

RIE 3 (MRC)

2026-05-12T05:19:01Z

John d: updated tool infobox

'''<big>DECOMISSIONED - This tool had been moved to the Teaching Cleanroom for teaching purposes Only. This page is only for historical informational purposes only.</big>'''
{{tool2|{{PAGENAME}}
|picture=RIE3.jpg
|type = Dry Etch
|super=
|super2=
|location=Bay 2
|description = RIE #3 Fluorine-Based System MRC 51
|manufacturer = Materials Research Corporation (MRC)
|materials =
|toolid=
}}
==About==

This is a Materials Research Corporation RIE-51 parallel plate, 13.56 MHz system used for etching with fluorine-containing gases (CF4, SF6, and CHF3). The system is used primarily for etching of Si, SiO2, and Si3N4 films. Metals such as tungsten may also be etched. Tool features include: six inch diameter water cooled cathode/substrate platform, pyrex cylinder for plasma confinement and gas flow control, adjustable cathode-anode spacing, fixed DC bias or RF power control and a HeNe laser etch monitor with chart recorder. It is turbo pumped and has no loadlock.

CF4/O2 and SF6/O2 will etch Si, SiO2 and Si3N4 readily since free fluorine is readily liberated in the plasma. The oxygen (up to 40%) initially enhances the fluorine concentration resulting in a higher etch rate. The oxygen also minimizes polymer formation in CF4/O2. Too much Oxygen will compete for fluorine available, suppressing the etch rate. Argon can be added to increase the physical component of etching. The highest etch rates are achieved with SF6 due to the ease of liberating fluorine compared with CF4. The relative etch rate decreases as one goes from Si to Si3N4 to SiO2. CF4 and CHF3 can be used to selectivity etch SiO2 over Si and resist due to increased polymer formation from the presence of hydrogen. This polymer layer is thicker on Si and resist than on SiO2. The trade-off is selectivity versus sidewall profile as the polymer will result in a tapered wall profile. Also, the polymer can be difficult to remove after etching.

The etches have good selectivity to many metals and semiconductors such as Ni, Al, Cr, Ti, GaAs, InP, and GaN. The system generally produces anisotropic etch profiles unless one goes into a purely chemical fluorine etch mode with higher pressure SF6 processes. The system also has a strong loading effect so that larger substrates and open areas will require more feed gas and higher pressure to compensate. As a result, individual processes need to be characterized.

==Detailed Specifications==

*Etch gases include: CF4, CHF3, SF6, Ar, O2
*Low 1 E -6 ultimate chamber pressure
*13.56 Mhz excitation frequency
*Manual gas control
*Automatic pressure control
*Manual RF tuning network
*Timer circuit for stopping the plasma
*Sample size limited to approximately 4 inches
*Masking materials include: Ni, photoresist (limited to low bias/power), Cr, Al

==Documentation==

*[https://wiki.nanotech.ucsb.edu/w/images/a/a6/RIE_3_SOP_Rev_D.pdf RIE #3 Standard Operating Procedure]

= Recipes =
==SiO2 Etching (RIE 3)==
*[//wiki.nanotech.ucsb.edu/w/images/2/2f/SiO2-Etch-Recipe-using-RIE-3-a.pdf SiO2 Etch Recipe with a very low surface damage - CHF3]
==SiNx Etching (RIE 3)==
*[//wiki.nanotech.ucsb.edu/w/images/9/98/51-SiNx-Etch-Recipe-using-RIE3.pdf SiNx Etch Recipe with a very low surface damage - CHF3]

RIE 3 (MRC)

2026-05-12T05:18:14Z

John d:

'''<big>DECOMISSIONED - This tool had been moved to the Teaching Cleanroom for teaching purposes Only. This page is only for historical informational purposes only.</big>'''
{{tool2|{{PAGENAME}}
|picture=RIE3.jpg
|type = Dry Etch
|super= Lee Sawyer
|super2= Aidan Hopkins
|phone= 805-893-2123
|location=Bay 2
|email=lee_sawyer@ucsb.edu
|description = RIE #3 Fluorine-Based System MRC 51
|manufacturer = Materials Research Corporation (MRC)
|materials =
|toolid=26
}}
==About==

This is a Materials Research Corporation RIE-51 parallel plate, 13.56 MHz system used for etching with fluorine-containing gases (CF4, SF6, and CHF3). The system is used primarily for etching of Si, SiO2, and Si3N4 films. Metals such as tungsten may also be etched. Tool features include: six inch diameter water cooled cathode/substrate platform, pyrex cylinder for plasma confinement and gas flow control, adjustable cathode-anode spacing, fixed DC bias or RF power control and a HeNe laser etch monitor with chart recorder. It is turbo pumped and has no loadlock.

CF4/O2 and SF6/O2 will etch Si, SiO2 and Si3N4 readily since free fluorine is readily liberated in the plasma. The oxygen (up to 40%) initially enhances the fluorine concentration resulting in a higher etch rate. The oxygen also minimizes polymer formation in CF4/O2. Too much Oxygen will compete for fluorine available, suppressing the etch rate. Argon can be added to increase the physical component of etching. The highest etch rates are achieved with SF6 due to the ease of liberating fluorine compared with CF4. The relative etch rate decreases as one goes from Si to Si3N4 to SiO2. CF4 and CHF3 can be used to selectivity etch SiO2 over Si and resist due to increased polymer formation from the presence of hydrogen. This polymer layer is thicker on Si and resist than on SiO2. The trade-off is selectivity versus sidewall profile as the polymer will result in a tapered wall profile. Also, the polymer can be difficult to remove after etching.

The etches have good selectivity to many metals and semiconductors such as Ni, Al, Cr, Ti, GaAs, InP, and GaN. The system generally produces anisotropic etch profiles unless one goes into a purely chemical fluorine etch mode with higher pressure SF6 processes. The system also has a strong loading effect so that larger substrates and open areas will require more feed gas and higher pressure to compensate. As a result, individual processes need to be characterized.

==Detailed Specifications==

*Etch gases include: CF4, CHF3, SF6, Ar, O2
*Low 1 E -6 ultimate chamber pressure
*13.56 Mhz excitation frequency
*Manual gas control
*Automatic pressure control
*Manual RF tuning network
*Timer circuit for stopping the plasma
*Sample size limited to approximately 4 inches
*Masking materials include: Ni, photoresist (limited to low bias/power), Cr, Al

==Documentation==

*[https://wiki.nanotech.ucsb.edu/w/images/a/a6/RIE_3_SOP_Rev_D.pdf RIE #3 Standard Operating Procedure]

= Recipes =
==SiO2 Etching (RIE 3)==
*[//wiki.nanotech.ucsb.edu/w/images/2/2f/SiO2-Etch-Recipe-using-RIE-3-a.pdf SiO2 Etch Recipe with a very low surface damage - CHF3]
==SiNx Etching (RIE 3)==
*[//wiki.nanotech.ucsb.edu/w/images/9/98/51-SiNx-Etch-Recipe-using-RIE3.pdf SiNx Etch Recipe with a very low surface damage - CHF3]

E-Beam Lithography System (Raith EBPG 5150+)

2026-05-04T22:57:55Z

John d: /* Detailed Specifications */ typos, added ASML matching

{{tool|{{PAGENAME}}
|picture=RaithEBPG_2026-03.png
|type = Lithography
|super= Bill Mitchell
|location=Bay 7
|description = Vector Scan Electron Beam Lithography System
|manufacturer = [https://raith.com Raith GmbH]
|model = EBPG 5150+
|materials =
|toolid=87
}}
{{ToolActions
|toolid = 87
|ProcessControlURL =
|ProceduresURL =
|TrainingURL =
}}

__TOC__

== About ==
'''Raith EBPG5150 Plus - Ultra High-Performance e-Beam Writer'''

The Raith EBPG Electron-Beam Lithography (EBL) tool is a high-speed, high current lithography tool for achieving lower than 10nm features, but also capable of very fast writing with the 350nA max current and higher speed 125MHz pattern generator & increased write-field size. The tool has fully automated/programmable aperture switching and beam calibrations. This enables the Raith EBL to write full-wafers at high speed for larger features (high current) and automatically switch+calibrate to exposure small (<<50nm) features in a single exposure, with sophisticated mix+match capabilities and pattern generation for maximum throughput while achieving the best high-resolution performance.

== Detailed Specifications ==
* Minimum feature size: 8nm
** 0.6nm stage movement resolution
* Layer-to-Layer Alignment/Overlay Accuracy: ≤5nm
* Maximum wafer/substrate size:
** Diameter: 150mm wafer (155mm x 155mm stage traverse)
** Thickness: 3mm
** (smaller piece-parts are common)
* 10-holder load-lock
** 2x Cassette loader/substrate holders available,
** Programmable/automated loading/switchout available via software.
* Beam Voltage: 50kV + 100kV
* Beam Current: 50pA – 350nA
** Automatic aperture changer
* Scanner Speed: 125MHz
* Exposure Field Size: 1.048 mm field size, continuously variable down to < 0.1 mm
** Single-nanometer stepping within the field
** Available at all beam currents and voltages
* Stand-alone optical alignment station (for pre-alignment of wafer to holder)
* Other capabilities:
** Automatic, dynamic off-axis focus, stigmation and field distortion corrections
** Integrated Laser height sensor for field-by-field or pre-mapping mode with direct electron feedback to deflection and focus corrections.

*Advanced write software available: Layout BEAMER from GeniSys Inc.
** Automated proximity correction of patterns possible
** Ability to manually position write fields within a pattern for optimum inter-field writing performance
** Ability to adjust beam scanning strategy within a write field for optimum intra-field writing performance
** Fine tuning of line-edge roughness by shot pitch correction & non-Manhattan scanning for curved edges

== Operating Procedures ==

* [[Media:Raith EBPG5150 - Operation Guide.pdf|EBPG5150 - Operation Guide]]

=== Training Procedure ===

* Contact Bill Mitchell for training, via SUM:
{{ToolTrainingButton
|toolid = 87
}}

== [[Direct-Write Lithography Recipes#E-Beam Lithography Recipes (Raith EBPG 5150+)|Recipes]] ==
All recipes can be found on the following page:

* ''Recipes > Litho. > Direct-Write > [[Direct-Write Lithography Recipes#E-Beam Lithography Recipes (Raith EBPG 5150+)|'''EBL Recipes''']].''
We have a number of litho processes "matching" between the [[Stepper 3 (ASML DUV)|ASML DUV Stepper]] and this tool.

Vacuum Sealer

2026-04-30T17:22:16Z

John d: addedc both sealers, info on suppllies and logn term storage with dessicant

{{tool2|{{PAGENAME}}
|picture=Vacuum.jpg
|type = Packaging
|super= Michael Barreraz
|super2= Aidan Hopkins
|location=Bay 4
|description = ?
|manufacturer = ?
}}

== About ==

To prevent samples from oxidizing, we have two vacuum sealers, silica dessicant packets and aluminum foil coated bags.

== Mini-pack Torre Vacuum Sealer ==

Larger chamber, can accommodate 100mm cassettes of 150mm individual wafer trays.

== Food Vacuum Sealer ==

[[File:Vacuum Sealer photo IMG 9946.png|link=https://wiki.nanofab.ucsb.edu/wiki/File:Vacuum%20Sealer%20photo%20IMG%209946.png|alt=Bonsen Kitchen vacuum sealer photo|none|thumb|280x280px]]Perfect for small wafer trays, very easy to use and fast.

== Bags + Dessicant packets ==

We provide silica dessicant packets, which you should place inside your bag to absorb water.

Plastic bags are provided at various sizes. For short-term (eg. few-month) storage these will work. However water-vapor does diffuse through plastic over time (eg. months).

For long-term storage, it is recommended to use the Aluminum-coated bags, which block diffusion of water & oxygen. Combined with dessicant packets, this should provide a good long-term storage solution for wafers sensitive to atmospheric water (eg. with Aluminum-containing epitaxial layers).

File:Vacuum Sealer photo IMG 9946.png

2026-04-30T17:15:35Z

John d:

Bonsen Kitchen vacuum sealer photo

Demis D. John

2026-04-28T23:32:16Z

John d: /* Current Work */ added intern programs

{{staff|{{PAGENAME}}
|position = Process Scientist Manager
|room = 1109D
|phone = (805) 893-5934
|email = demis@ucsb.edu
}}

==Contact If...==

*You are interested in [https://www.nanotech.ucsb.edu/services#comp-k3t1h1jc fabrication services performed by NanoFab Staff]
*You need immediate help with one of the [[Demis D. John#Tools|Tools listed below]]
*You have a question about the capabilities or usage of a Tool listed below
*You have a question about your fabrication process, or are designing a new fabrication process
*You want help solving some fabrication problem or interpreting fabrication data

==About==
[[File:Demis UCSB-Photonics-Gif.gif|alt=animation UCSB Engineering - Photonics|frame]]
Demis John graduated with his Ph.D. in 2012 from the [http://ocpi.ece.ucsb.edu/ research group of Dr. Daniel J. Blumenthal at UCSB].
He worked on creating [http://ocpi.ece.ucsb.edu/research/photonic-integration/ultra-low-loss-platforms/ ultra-low-loss optical waveguides], in close collaboration with the [http://optoelectronics.ece.ucsb.edu/ John E. Bowers research group], involving a great deal of materials analysis and fabrication along with optoelectronic simulation.
From 2012 to 2017, Demis worked at [http://praevium.com/ Praevium Research Inc.] where he developed near-infrared and mid-infrared tunable semiconductor lasers for medical imaging and gas spectroscopy, respectively. Combined, Demis has been using the Nanofab since 2006.

==Current Work==
Demis is the manager of the [[Staff List#Process Group|Process Group]], and is knowledgeable in fabrication techniques and troubleshooting processing issues, along with materials characterization techniques and developing new repeatable procedures for fabricating devices. Users are encouraged to ask Demis for help regarding fabrication.

In addition, Demis is managing all "remote fabrication jobs" for external customers, and assigns these customer jobs and internal processing tasks to the Process Group Staff. External users should contact Demis for inquiries regarding high-resolution lithography & experimental processing tasks.

Demis also has scaled up and manages the Nanofab internship programs, both in the Process Group (hands-on fabrication) and Equipment Group (facilities+equipment repair etc).

Lastly, he is paying attention to usability and user needs in the NanoFab (including websites, procedures etc.), so please notify him of any comments or concerns.

==Tools==
Demis D. John is the supervisor for the following tools.

=== Supervisor ===

*[[Stepper 3 (ASML DUV)]]
*[[Laser Etch Monitoring|Intellemetrics Laser Monitors on Etching Systems]]
*[[Microscopes|Optical Microscopes]]
*[[Holographic Lith/PL Setup (Custom)|Holography & Photoluminescence]]
*[[Probe Station & Curve Tracer]]
*[[IR Thermal Microscope (QFI)]] - ''training only''
*1-cm Wafer-Bonding Fixture (custom)

=== Backup Engineer ===

* [[Optical Film Thickness & Wafer-Mapping (Filmetrics F50)|Filmetrics F50 wafer mapper]]
* [[Optical Film Spectra + Optical Properties (Filmetrics F10-RT-UVX)|Filmetrics F10RT optical spectrometer]]
* [[Ellipsometer (Woollam)|J.A. Woollam Ellipsometer]]

==External Professional Websites==

*[https://www.linkedin.com/in/demis-john-4790938/ LinkedIn]
*[https://scholar.google.com/citations?user=MZwxgnMAAAAJ&hl=en&authuser=1 Google Scholar]
*[https://www.researchgate.net/profile/Demis_John ResearchGate Profile]
*[https://github.com/demisjohn/ GitHub]
*[http://ips.ece.ucsb.edu Photonics Society at UCSB]

ICP Etching Recipes

2026-04-28T15:23:43Z

John d: /* Through Silicon Via (TSV) etch (DSEiii) */ updated TSV DSE etch to ↑ EtchA bias + time

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''[[ICP Etching Recipes#Process Control Data (DSEiii)|Process Control Data below]]''' - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==
*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with Al2O3 hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**Larger open area → lower selectivity & lower etch rate.
***<1% center to edge variability in etch rate for small open area.
***More variation across wafer for larger open area (eg. plasma dicing)
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}

=== '''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)''' ===
[[File:DSE plot.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281|232x232px]]
* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots''']

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
We have a new wafer-mounting process for through-silicon etching, using the UV-Release Dicing tape. Contact [[Demis D. John|staff]] for more info.
-- [[Demis D. John|Demis]] 2026-02-10

'''NOTE''':
'''DO NOT RUN''' the wax-mounting process without discussing with staff first. The wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer!
''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11

{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
with wax-mounting (small pieces only)
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - to eliminate grassing:

* Increase EtchA LF-Bias Power and Duration
** EtchA: 300W for 3.5–4sec
** New method as of ~2025
Old method: reduce Dep step:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

=== Plasma Dicing (DSEIII) ===
'''''Coming Soon''''': Plasma Dicing process with Dicing Tape as backing film.

This process has been developed by staff, is currently in the final stages of finalizing a public recipe. [[Demis D. John|'''''Contact staff''''']] if you want to use it sooner.

==Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)==

*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
**Smooth, Vertical, E.R. uniformity is within 5% on wafer
**Tested with 4" wafers that are ~50% open with UV6 PR
*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Older, alternate Si "shallow/smooth" etch recipe.
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

== SiO2 Etch (DSEiii) ==
These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].
*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
**Vertical/Smooth
**Tested by mounting 1cmx1cm piece with oil on 4" Si

==F-ICP Backup Recipes (DSEiii)==
These recipes were developed to serve as backup processes for the calibrated [[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|'''Fluorine-ICP''']] SiO2 and Si etches [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]].

[https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing FICP to DSE etch processes].

*'''[[ICP Etching Recipes#Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)|Si Etch v1 (⭐️Production)]]'''
*'''[[ICP Etching Recipes#SiO2 Etch (DSEiii)|SiO2 Etch v1 (⭐️Production)]]'''

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the [[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|'''Process Control Data below''']] - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

=== Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
[[File:FICP-Si.png|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots''']

==SiO2 Etch Recipes (Fluorine ICP Etcher)==
[[File:FL-ICP_50W_SiO2_etch_with_Ru_Hard_Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|thumb|266x266px|50W SiO2 Etch w/ Ru Hardmask]]
[[File:FL-ICP_200W_SiO2_Etch_with_Ru_Hardmask_-_Ning_Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|thumb|266x266px|200W SiO2 Etch w/ Ru Hardmask (Ning Cao)]]
*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.

=== [//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] ===

* Click above for [http://wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf Full Process Traveler]
** Process written for Sputtered Ru & I-Line GCA Stepper litho
** Can be transferred to ALD Ru or DUV/EBL Litho.

*''Ning Cao & Bill Mitchell, 2019-06''
*''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
*''Etch also works well with PR masking''
*''Chemistry: CHF3/CF4''
*''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
*Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
*50W Bias: ('''recommended''')
**Selectivity to photoresist: 1.10–1.20
**SiO2 selectivity to Ru: 36
**SiO2 etch rate: 263nm/min
**''Smoothest vertical etch for SiO2.''
*200W Bias: (higher etch rate)
**SiO2 selectivity to Ru: 38
**SiO2 etch rate: 471nm/min
*This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
*Updates: Many users have found that SiO2-masking the Ru hardmask results in vastly improved photoresist selectivity, making litho+etch of small features much better.
**Layer stack looks like: SiO2 (or other dielectric target layer to etch) / Ru hardmask / SiO2 hardmask (thin) / Photoresist.
**Typically strip the masks+PR with all dry etching. That means the entire etch process (all etches and strips) can be run ''in situ'' on the Panasonic ICP in a rapid single-tool etch process.
===Process Control: SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
[[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots''']

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===
[[File:SEM Image.png|thumb|New PR Strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Old PR strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**45sec-1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue

==Cleaning Procedures (Fluorine ICP Etcher)==

* [https://wiki.nanotech.ucsb.edu/w/images/6/69/Cleaning_Rules_for_Fluorine_ICP_Etch_tool.pdf '''Cleaning Rules'''] - for various etches. All cleans are O2 plasma.

=[[ICP Etch 1 (Panasonic E646V)]]=
'''Panasonic ICP#1 is currently down -''' Use Panasonic ICP#2 instead. Most processes directly transfer with only small change in etch rate. Data kept here for historical purposes only.

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure & Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get on the ''back'' of the carrier wafer or you will get Helium cooling errors.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch, and see their SEM's.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
**''This etch is used in our Process Control weekly cals run by [[Process Group Interns|NanoFab Interns]]. Very stable over time ±5%.''
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

===Process Control: SiO2 Etch with CHF3/CF4 (Panasonic 2)===
[[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|thumb|269x269px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts] for SiO2 etching.|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]''Weekly cal etches of the CF4/CHF3 SiO2 etch, run by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots''']

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*GaAs Etch Cal - ''Noah Dutra & Fatt Foong, 2025-02-12''
**Etch Rates ~1um/min, Selectivity to SiO2 ~ 27:1, Sidewalls ~ 90°
**Etch Rate/Selectivity [https://wiki.nanofab.ucsb.edu/w/images/7/76/GaAs_pressure_experiment.png highly sensitive to pressure] (image credit: Terry Guerrero)
**Cal Sample: ~1cm sample etched mounted with oil onto 150mm Si carrier
**Recipe: 0.5Pa, 100/900W, N2/Cl2=10/20sccm
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf Non-Calibration GaAs Etch Recipes - Panasonic 2 - Cl2N2]

===Process Control: GaAs Etch with N2/Cl2 (Panasonic 2)===
[[File:GaAs Etch ICP2 SPC.png|alt=example ICP2 process control chart|thumb|249x249px|[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for GaAs etching.|link=https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281]]
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=0#gid=0 GaAs Etch with N2/Cl2 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 GaAs Etch with N2/Cl2 - '''Plots''']

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

=== Process Tips ===
* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* InP requires fairly high temperatures for making the Indium products volatile - so going to full-wafers (which are cooler) may requiring the table temperature. We have found that temperatures of ~150⁰C minimum may be required for preventing grassing etc.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==InP Ridge Etch (Oxford ICP Etcher)==
===High-Temp (200°C) InP Etch Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
[[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|thumb|218x218px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for 200°C InP Etch|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

===Low-Temp (60°C) InP Etch Process===
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: Low-Temp (60°C) InP Etch ====
[[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts] for 60°C InP Etch|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots''']

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''OLD 4" configuration: [https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: GaN Etch ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''

* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.

* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]

[[File:GaN SPC.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279|219x219px]]OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]
==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning
*''[https://wiki.nanofab.ucsb.edu/w/images/d/d1/GaAs_Etch_Ver3_Recipe_Finalized_120925.pdf Std GaAs Etch - Cl2/N2 - 30C Etch Characterization] - F. Foong, 2025-12-10''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

ICP Etching Recipes

2026-04-28T00:32:23Z

John d: /* Cleaning Procedures (Fluorine ICP Etcher) */ linked to cleaning rules.

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''[[ICP Etching Recipes#Process Control Data (DSEiii)|Process Control Data below]]''' - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==
*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with Al2O3 hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**Larger open area → lower selectivity & lower etch rate.
***<1% center to edge variability in etch rate for small open area.
***More variation across wafer for larger open area (eg. plasma dicing)
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}

=== '''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)''' ===
[[File:DSE plot.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281|232x232px]]
* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots''']

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
We have a new wafer-mounting process for through-silicon etching, using the UV-Release Dicing tape. Contact [[Demis D. John|staff]] for more info.
-- [[Demis D. John|Demis]] 2026-02-10

'''NOTE''':
'''DO NOT RUN''' the wax-mounting process without discussing with staff first. The wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer!
''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11

{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
with wax-mounting (small pieces only)
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

=== Plasma Dicing (DSEIII) ===
'''''Coming Soon''''': Plasma Dicing process with Dicing Tape as backing film.

This process has been developed by staff, is currently in the final stages of finalizing a public recipe. [[Demis D. John|'''''Contact staff''''']] if you want to use it sooner.

==Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)==

*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
**Smooth, Vertical, E.R. uniformity is within 5% on wafer
**Tested with 4" wafers that are ~50% open with UV6 PR
*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Older, alternate Si "shallow/smooth" etch recipe.
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

== SiO2 Etch (DSEiii) ==
These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].
*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
**Vertical/Smooth
**Tested by mounting 1cmx1cm piece with oil on 4" Si

==F-ICP Backup Recipes (DSEiii)==
These recipes were developed to serve as backup processes for the calibrated [[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|'''Fluorine-ICP''']] SiO2 and Si etches [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]].

[https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing FICP to DSE etch processes].

*'''[[ICP Etching Recipes#Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)|Si Etch v1 (⭐️Production)]]'''
*'''[[ICP Etching Recipes#SiO2 Etch (DSEiii)|SiO2 Etch v1 (⭐️Production)]]'''

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the [[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|'''Process Control Data below''']] - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

=== Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
[[File:FICP-Si.png|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots''']

==SiO2 Etch Recipes (Fluorine ICP Etcher)==
[[File:FL-ICP_50W_SiO2_etch_with_Ru_Hard_Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|thumb|266x266px|50W SiO2 Etch w/ Ru Hardmask]]
[[File:FL-ICP_200W_SiO2_Etch_with_Ru_Hardmask_-_Ning_Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|thumb|266x266px|200W SiO2 Etch w/ Ru Hardmask (Ning Cao)]]
*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.

=== [//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] ===

* Click above for [http://wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf Full Process Traveler]
** Process written for Sputtered Ru & I-Line GCA Stepper litho
** Can be transferred to ALD Ru or DUV/EBL Litho.

*''Ning Cao & Bill Mitchell, 2019-06''
*''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
*''Etch also works well with PR masking''
*''Chemistry: CHF3/CF4''
*''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
*Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
*50W Bias: ('''recommended''')
**Selectivity to photoresist: 1.10–1.20
**SiO2 selectivity to Ru: 36
**SiO2 etch rate: 263nm/min
**''Smoothest vertical etch for SiO2.''
*200W Bias: (higher etch rate)
**SiO2 selectivity to Ru: 38
**SiO2 etch rate: 471nm/min
*This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
*Updates: Many users have found that SiO2-masking the Ru hardmask results in vastly improved photoresist selectivity, making litho+etch of small features much better.
**Layer stack looks like: SiO2 (or other dielectric target layer to etch) / Ru hardmask / SiO2 hardmask (thin) / Photoresist.
**Typically strip the masks+PR with all dry etching. That means the entire etch process (all etches and strips) can be run ''in situ'' on the Panasonic ICP in a rapid single-tool etch process.
===Process Control: SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
[[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots''']

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===
[[File:SEM Image.png|thumb|New PR Strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Old PR strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**45sec-1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue

==Cleaning Procedures (Fluorine ICP Etcher)==

* [https://wiki.nanotech.ucsb.edu/w/images/6/69/Cleaning_Rules_for_Fluorine_ICP_Etch_tool.pdf '''Cleaning Rules'''] - for various etches. All cleans are O2 plasma.

=[[ICP Etch 1 (Panasonic E646V)]]=
'''Panasonic ICP#1 is currently down -''' Use Panasonic ICP#2 instead. Most processes directly transfer with only small change in etch rate. Data kept here for historical purposes only.

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure & Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get on the ''back'' of the carrier wafer or you will get Helium cooling errors.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch, and see their SEM's.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
**''This etch is used in our Process Control weekly cals run by [[Process Group Interns|NanoFab Interns]]. Very stable over time ±5%.''
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

===Process Control: SiO2 Etch with CHF3/CF4 (Panasonic 2)===
[[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|thumb|269x269px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts] for SiO2 etching.|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]''Weekly cal etches of the CF4/CHF3 SiO2 etch, run by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots''']

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*GaAs Etch Cal - ''Noah Dutra & Fatt Foong, 2025-02-12''
**Etch Rates ~1um/min, Selectivity to SiO2 ~ 27:1, Sidewalls ~ 90°
**Etch Rate/Selectivity [https://wiki.nanofab.ucsb.edu/w/images/7/76/GaAs_pressure_experiment.png highly sensitive to pressure] (image credit: Terry Guerrero)
**Cal Sample: ~1cm sample etched mounted with oil onto 150mm Si carrier
**Recipe: 0.5Pa, 100/900W, N2/Cl2=10/20sccm
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf Non-Calibration GaAs Etch Recipes - Panasonic 2 - Cl2N2]

===Process Control: GaAs Etch with N2/Cl2 (Panasonic 2)===
[[File:GaAs Etch ICP2 SPC.png|alt=example ICP2 process control chart|thumb|249x249px|[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for GaAs etching.|link=https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281]]
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=0#gid=0 GaAs Etch with N2/Cl2 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 GaAs Etch with N2/Cl2 - '''Plots''']

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

=== Process Tips ===
* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* InP requires fairly high temperatures for making the Indium products volatile - so going to full-wafers (which are cooler) may requiring the table temperature. We have found that temperatures of ~150⁰C minimum may be required for preventing grassing etc.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==InP Ridge Etch (Oxford ICP Etcher)==
===High-Temp (200°C) InP Etch Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
[[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|thumb|218x218px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for 200°C InP Etch|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

===Low-Temp (60°C) InP Etch Process===
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: Low-Temp (60°C) InP Etch ====
[[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts] for 60°C InP Etch|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots''']

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''OLD 4" configuration: [https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: GaN Etch ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''

* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.

* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]

[[File:GaN SPC.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279|219x219px]]OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]
==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning
*''[https://wiki.nanofab.ucsb.edu/w/images/d/d1/GaAs_Etch_Ver3_Recipe_Finalized_120925.pdf Std GaAs Etch - Cl2/N2 - 30C Etch Characterization] - F. Foong, 2025-12-10''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

Research Pubs 2026-04-24

2026-04-24T16:32:46Z

John d: pasted from AI

<div style="border: 2px solid #003660; border-radius: 8px; padding: 20px; margin-bottom: 20px; background: linear-gradient(135deg, #f8f9fa 0%, #e8eef5 100%);">
<div style="font-size: 1.6em; font-weight: bold; color: #003660; margin-bottom: 8px;">UCSB Nanofabrication Facility — Research Groups & Publications</div>
<div style="font-size: 1.05em; color: #444;">A curated directory of research groups utilizing the [https://www.nanotech.ucsb.edu/ UCSB Nanofab], organized by discipline. Each section highlights recent high-impact publications and representative research imagery.</div>
<div style="margin-top: 10px; font-size: 0.9em; color: #666;">''Last updated: April 2026''</div>
</div>

__TOC__





== Photonics and Integrated Optics ==

<div style="border-left: 4px solid #0077b6; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Silicon photonics, III-V integration, optical communications, nanophotonic devices, and metasurfaces — enabling next-generation data links, sensing, and on-chip light manipulation.''
</div>



=== Optical Communications & Photonic Integration Group — Prof. Daniel Blumenthal ===

{| style="width: 100%;"
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'''PI:''' [https://scholar.google.com/citations?user=4yjw1ecAAAAJ Prof. Daniel Blumenthal] (Google Scholar) • [https://ocpi.ece.ucsb.edu/ Group Website]

Develops ultra-low-loss silicon nitride (Si3N4) photonic integrated circuits for stimulated Brillouin lasers, optical gyroscopes, optical frequency synthesis, and emerging atom-photonic quantum integration on chip.

'''Selected Recent Publications:'''
* ''Integrated optical frequency division for microwave and mmWave generation'' — '''Nature''' 627, 540–545 (2024). [https://doi.org/10.1038/s41586-024-07057-0 DOI]
* ''Integrated photonic molecule Brillouin laser with a high-power sub-100-mHz fundamental linewidth'' — '''Optics Letters''' 49(1), 45–48 (2024). [https://doi.org/10.1364/OL.503126 DOI]

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[[File:Blumenthal_SiN_coil_resonator.jpg|thumb|300px|Ultra-low-loss silicon nitride photonic coil resonator chip used for Brillouin lasers and high-Q resonators.]]

[[File:Blumenthal_PZT_SiN_microcomb.png|thumb|300px|PZT-integrated silicon nitride microcomb resonator for chip-based optical frequency division.]]

|}



=== Silicon Photonics, AIM Photonics & Institute for Energy Efficiency — Prof. John Bowers ===

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'''PI:''' [https://scholar.google.com/citations?user=c6rbVa0AAAAJ Prof. John Bowers] (Google Scholar) • [https://siliconphotonics.ece.ucsb.edu/ Silicon Photonics] • [https://aim.ucsb.edu AIM Photonics] • [https://iee.ucsb.edu IEE]

Leads research on heterogeneous integration of III-V materials on silicon for lasers, amplifiers, and modulators, as well as advanced silicon photonic platforms for datacom, telecom, and ultra-narrow-linewidth laser sources.

'''Selected Recent Publications:'''
* ''Roadmapping the next generation of silicon photonics'' — '''Nature Communications''' 15, 751 (2024). [https://doi.org/10.1038/s41467-024-44750-0 DOI]
* ''Lithium niobate photonics: Unlocking the electromagnetic spectrum'' — '''Science''' 379(6627) (2023). [https://doi.org/10.1126/science.abj4396 DOI]

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[[File:Bowers_3D_PIC_integration.png|thumb|300px|3D photonic integrated circuit: heterogeneous III-V on silicon architecture without an isolator (Nature, 2023).]]

[[File:Bowers_racetrack_resonator.jpg|thumb|300px|Novel conjoined racetrack resonator geometry for silicon photonics.]]

|}



=== Integrated Photonics Laboratory — Prof. Jonathan Klamkin ===

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'''PI:''' [https://scholar.google.com/citations?user=vR_K3XYAAAAJ Prof. Jonathan Klamkin] (Google Scholar) • [https://web.ece.ucsb.edu/ipl Group Website]

Specializes in III-V photonic integrated circuits for free-space optical communications, LiDAR, microwave photonics, and monolithic integration of III-V quantum dot lasers on silicon via selective area heteroepitaxy.

'''Selected Recent Publications:'''
* ''Selective area heteroepitaxy of low dislocation density antiphase boundary free GaAs microridges on flat-bottom (001) Si for integrated silicon photonics'' — '''Journal of Applied Physics''' 129, 123103 (2021). [https://doi.org/10.1063/5.0042666 DOI]
* ''Towards fully monolithic silicon-based integrated photonics: MOCVD grown lasers on silicon by blanket and selective area heteroepitaxy'' — '''Proc. SPIE''' (Photonics West, 2022). [https://doi.org/10.1117/12.2612366 DOI]

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[[File:Klamkin_3D_hybrid_SiPh.jpg|thumb|300px|3D hybrid integrated silicon photonics platform merging InP and GaAs devices with SiPh.]]

[[File:Klamkin_free_space_optical_comms.jpg|thumb|300px|Laser communication terminal for free-space optical links (NASA-funded research).]]

|}



=== Schow Lab — Prof. Clint Schow ===

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'''PI:''' [https://scholar.google.com/citations?user=cVY3g4cAAAAJ Prof. Clint Schow] (Google Scholar) • [https://schow.ece.ucsb.edu/ Group Website]

Develops energy-efficient optical interconnects for data centers, with emphasis on analog coherent detection architectures that eliminate power-hungry DSP, leveraging silicon photonics and co-packaged optics.

'''Selected Recent Publications:'''
* ''A Monolithic O-Band Coherent Optical Receiver for Energy-Efficient Intra-Data Center Links'' — '''Journal of Lightwave Technology''' 42(7) (2024). [https://doi.org/10.1109/JLT.2023.3341666 DOI]
* ''Analog Coherent Detection for Energy Efficient Intra-Data Center Links at 200 Gbps Per Wavelength'' — '''Journal of Lightwave Technology''' 39(2) (2021). [https://doi.org/10.1109/JLT.2020.3030566 DOI]

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[[File:Schow_coherent_optical_links.jpg|thumb|300px|Low-power coherent optical links for datacenter interconnects.]]

[[File:Schow_cryogenic_optical_links.jpg|thumb|300px|Cryogenic silicon photonic optical links for classical and quantum computing.]]

|}



=== Schuller Lab — Prof. Jon Schuller ===

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'''PI:''' [https://scholar.google.com/citations?user=Ff90s74AAAAJ Prof. Jon Schuller] (Google Scholar) • [https://schuller.cnsi.ucsb.edu/ Group Website]

Investigates light-matter interactions at the nanoscale, designing dielectric and semiconductor metasurfaces for directional light emission, magneto-optical traps, and active reconfigurable photonic devices.

'''Selected Recent Publications:'''
* ''High efficiency large-angle polarization-insensitive retroreflecting metasurface for magneto-optical traps'' — '''Applied Physics Letters''' 124, 251704 (2024). [https://doi.org/10.1063/5.0210124 DOI]
* ''Optimizing Polarization Selective Unidirectional Photoluminescence from Phased-Array Metasurfaces'' — '''Advanced Optical Materials''' (2024). [https://doi.org/10.1002/adom.202303186 DOI]

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[[File:Schuller_crystal_microstructures.jpg|thumb|300px|Hybrid organic/inorganic crystalline microstructures with quantum-confinement-induced red luminescence.]]

[[File:Schuller_metasurface_beam_deflector.jpg|thumb|300px|Tunable dielectric metasurface beam deflector for engineered light steering.]]

|}





== Quantum Computing, Quantum Sensing & Quantum Materials ==

<div style="border-left: 4px solid #7b2d8e; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Quantum optics, entangled photon sources, NV-center sensing, topological qubits, and correlated electron systems — building the hardware foundations for quantum information science.''
</div>



=== Quantum Optics & Quantum Information Group — Prof. Dirk Bouwmeester ===

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'''PI:''' [https://scholar.google.com/citations?user=r92BS5wAAAAJ Prof. Dirk Bouwmeester] (Google Scholar) • [https://bouwmeestergroup.physics.ucsb.edu Group Website]

Explores quantum optics and cavity quantum electrodynamics with semiconductor quantum dots, optomechanical systems using phononic crystal membranes, and quantum decoherence phenomena.

'''Selected Recent Publications:'''
* ''Single-emitter quantum key distribution over 175 km of fibre with optimised finite key rates'' — '''Nature Communications''' 14, 3573 (2023). [https://doi.org/10.1038/s41467-023-39219-7 DOI]
* ''Phononically shielded photonic-crystal mirror membranes for cavity quantum optomechanics'' — '''Quantum Science and Technology''' 10(4), 045004 (2025). [https://doi.org/10.1088/2058-9565/ad865a DOI]

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[[File:Bouwmeester_micropillar_quantum_dot.png|thumb|300px|Micropillar samples with embedded quantum dots for cavity-QED experiments and single-photon sources.]]

[[File:Bouwmeester_phononic_crystal_membrane.png|thumb|300px|Phononically shielded photonic-crystal membrane for cavity quantum optomechanics.]]

|}



=== Quantum Photonics Laboratory — Prof. Galan Moody ===

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'''PI:''' [https://scholar.google.com/citations?user=FLokITkAAAAJ Prof. Galan Moody] (Google Scholar) • [https://qpl.ece.ucsb.edu Group Website]

Develops integrated quantum photonic devices on chip-scale platforms, including entangled photon-pair sources from microring resonators, 2D material quantum emitters, and scalable single-photon technologies for quantum networking.

'''Selected Recent Publications:'''
* ''2022 Roadmap on integrated quantum photonics'' — '''Journal of Physics: Photonics''' 4, 012501 (2022). [https://doi.org/10.1088/2515-7647/ac1ef4 DOI]
* ''Defect and strain engineering of monolayer WSe2 enables site-controlled single-photon emission up to 150 K'' — '''Nature Communications''' 12, 3585 (2021). [https://doi.org/10.1038/s41467-021-23709-5 DOI]

| style="vertical-align: top; width: 320px;" |
[[File:Moody_AlGaAsOI_entanglement_chip.jpg|thumb|300px|AlGaAs-on-insulator chip with microring array devices for high-rate entangled photon-pair generation.]]

[[File:Moody_NanoLetters_cover_2D_emitters_SiN.jpg|thumb|300px|Nano Letters cover: 2D material quantum emitters (hBN) integrated with silicon nitride microring resonators.]]

|}



=== Quantum Sensing & Imaging Group — Prof. Ania Jayich ===

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'''PI:''' [https://scholar.google.com/citations?user=EKElikcAAAAJ Prof. Ania Bleszynski Jayich] (Google Scholar) • [https://www.10-9lab.com/ Group Website (10−9 Lab)]

Engineers nitrogen-vacancy (NV) centers in diamond for ultra-sensitive nanoscale magnetometry and quantum sensing. Recent breakthroughs leverage many-body quantum dynamics for signal amplification in solid-state quantum sensors.

'''Selected Recent Publications:'''
* ''Signal amplification in a solid-state sensor through asymmetric many-body echo'' — '''Nature''' 646, 68–73 (2025). [https://doi.org/10.1038/s41586-025-09452-7 DOI]
* ''Scalable nanoscale positioning of highly coherent color centers in prefabricated diamond nanostructures'' — '''Nature Communications''' 16 (2025). [https://doi.org/10.1038/s41467-025-64758-4 DOI]

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[[File:Jayich_NV_diamond_probe.jpg|thumb|300px|Diamond scanning probe tip with embedded NV center for nanoscale magnetometry of condensed matter systems.]]

[[File:Jayich_diamond_NV_AoS_Hughes.jpg|thumb|300px|Diamond NV center engineering for quantum sensing applications.]]

|}



=== Palmstrom Group — Prof. Chris Palmstrom ===

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'''PI:''' [https://scholar.google.com/citations?user=c-B7OFcAAAAJ Prof. Chris Palmstrom] (Google Scholar) • [https://palmstrom.cnsi.ucsb.edu/ Group Website]

Grows quantum materials by molecular beam epitaxy (MBE), including III-V semiconductor heterostructures, Heusler compounds, and superconductor/semiconductor hybrids for topological quantum computing and superconducting circuits.

'''Selected Recent Publications:'''
* ''Cryogenic Growth of Tantalum Thin Films for Low-Loss Superconducting Circuits'' — '''Physical Review Applied''' 23(3), 034025 (2025). [https://doi.org/10.1103/PhysRevApplied.23.034025 DOI]
* ''Fabrication and Characterization of Low-Loss Al/Si/Al Parallel Plate Capacitors for Superconducting Quantum Information Applications'' — '''npj Quantum Information''' 11 (2025). [https://doi.org/10.1038/s41534-025-00967-5 DOI]

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[[File:Palmstrom_hashtag_nanowire_Majorana_SEM.jpg|thumb|300px|SEM of InSb "hashtag" nanowire networks grown by MBE, partially coated with superconducting aluminum for Majorana quasiparticle experiments.]]

[[File:Palmstrom_MBE_lab_UCSB.jpg|thumb|300px|The Palmstrom MBE lab at UCSB for growing novel quantum materials. Photo: Lilli McKinney.]]

|}



=== Young Lab — Prof. Andrea Young ===

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'''PI:''' [https://scholar.google.com/citations?user=EbqS1EoAAAAJ Prof. Andrea Young] (Google Scholar) • [https://www.afylab.com/ Group Website]

Investigates correlated electronic phases in van der Waals heterostructures, including superconductivity, magnetism, and quantum Hall physics in graphene-based systems using nanofabrication and low-temperature transport measurements.

'''Selected Recent Publications:'''
* ''Superconductivity in rhombohedral trilayer graphene'' — '''Nature''' 598, 434–438 (2021). [https://doi.org/10.1038/s41586-021-03926-0 DOI]
* ''Isospin magnetism and spin-polarized superconductivity in Bernal bilayer graphene'' — '''Science''' 375(6582) (2022). [https://doi.org/10.1126/science.abm8386 DOI]

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[[File:Young_nanoSQUID_microscope.jpg|thumb|300px|NanoSQUID-on-tip cryogenic microscope for nanoscale magnetic and thermal imaging of quantum materials.]]

[[File:Young_graphene_Corbino_device.jpg|thumb|300px|Corbino-geometry monolayer graphene device for quantum Hall measurements and correlated electron state studies.]]

|}





== High-Speed Electronics & RF ==

<div style="border-left: 4px solid #d4380d; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Sub-THz transistors, 2D-material nanoelectronics, and advanced CMOS architectures — driving the next generation of wireless communications and computing.''
</div>



=== High Speed Electronics Group — Prof. Mark Rodwell ===

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'''PI:''' [https://scholar.google.com/citations?user=u_C8sbEAAAAJ Prof. Mark Rodwell] (Google Scholar) • [https://web.ece.ucsb.edu/Faculty/rodwell/ Group Website]

Develops InP heterojunction bipolar transistor (HBT) integrated circuits and transceiver modules operating at 100–300 GHz for next-generation sub-THz wireless communication systems with multi-Gbps data rates.

'''Selected Recent Publications:'''
* ''100–300 GHz Wireless: Transistors, ICs, and Systems'' — '''IEEE Microwave Magazine''' (2025). [https://doi.org/10.1109/MMM.2025.3584028 DOI]
* ''A 280 GHz InP HBT Direct-Conversion Receiver with 10.8 dB NF'' — '''IEEE RFIC Symposium''' (2023). [https://doi.org/10.1109/RFIC54547.2023.10186179 DOI]

| style="vertical-align: top; width: 320px;" |
[[File:Rodwell_InP_HBT_CrossSection_SEM.png|thumb|300px|Cross-sectional SEM of a UCSB InP HBT showing sub-micron emitter, base, and collector mesa layers.]]

[[File:Rodwell_THz_Transceiver_IC.png|thumb|300px|130 nm InP HBT transceiver IC layout for 100–300 GHz wireless systems.]]

|}



=== Nanoelectronics Research Lab — Prof. Kaustav Banerjee ===

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'''PI:''' [https://scholar.google.com/citations?user=zkZqDDcAAAAJ Prof. Kaustav Banerjee] (Google Scholar) • [https://nrl.ece.ucsb.edu/ Group Website]

Pioneers 2D material-based transistor architectures for future CMOS scaling, including 3D transistors with 2D semiconductors, neuromorphic computing platforms using tunnel-FETs, and cryogenic CMOS for quantum computing.

'''Selected Recent Publications:'''
* ''Three-dimensional Transistors with Two-dimensional Semiconductors for Future CMOS Scaling'' — '''Nature Electronics''' (2024). [https://doi.org/10.1038/s41928-024-01289-8 DOI]
* ''An Ultra Energy-efficient Hardware Platform for Neuromorphic Computing Enabled by 2D-TMD Tunnel-FETs'' — '''Nature Communications''' (2024). [https://doi.org/10.1038/s41467-024-46397-3 DOI]

| style="vertical-align: top; width: 320px;" |
[[File:Banerjee_Graphene_Kinetic_Inductor.png|thumb|300px|Intercalated multilayer graphene on-chip spiral inductors — the first kinetic inductors achieving 1.5× higher inductance density than copper.]]

[[File:Banerjee_2D_3D_NanoplateFET.png|thumb|300px|3D nano-plate FET architecture using 2D WS2 semiconductors in gate-all-around configuration.]]

|}





== Wide-Bandgap Semiconductors & Power Electronics ==

<div style="border-left: 4px solid #389e0d; padding-left: 12px; margin-bottom: 10px; color: #333;">
''GaN and Ga2O3 devices for solid-state lighting, micro-LEDs, laser diodes, and high-voltage power conversion — from Nobel Prize-winning blue LEDs to next-generation ultra-wide-bandgap power electronics.''
</div>



=== Krishnamoorthy Research Group — Prof. Sriram Krishnamoorthy ===

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'''PI:''' [https://scholar.google.com/citations?user=msxQ2fYAAAAJ Prof. Sriram Krishnamoorthy] (Google Scholar) • [https://sites.google.com/view/krishnamoorthygroup/home Group Website]

Advances ultra-wide-bandgap semiconductor device technology, particularly β-Ga2O3 power electronics including kilovolt-class MOSFETs and Schottky barrier diodes grown by MOCVD for high-voltage, high-efficiency power conversion.

'''Selected Recent Publications:'''
* ''Kilovolt-Class β-Ga2O3 MOSFETs on 1-inch Bulk Substrates'' — '''Applied Physics Letters''' (2024). [https://doi.org/10.1063/5.0191366 DOI]
* ''2.1 kV (001)-β-Ga2O3 Vertical Schottky Barrier Diode with High-k Oxide Field Plate'' — '''Applied Physics Letters''' (2023). [https://doi.org/10.1063/5.0137935 DOI]

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[[File:Krishnamoorthy_Ga2O3_TriGate_MESFET.png|thumb|300px|Tri-gate β-Ga2O3 MESFET with SiNx passivation, achieving record 0.95 GW/cm2 power figure of merit.]]

[[File:Krishnamoorthy_Ga2O3_SiC_MOSFET.png|thumb|300px|β-Ga2O3-on-SiC MOSFET for enhanced thermal management of UWBG power devices.]]

|}



=== Solid State Lighting & Electronic Center (SSLEEC) — Prof. Steven DenBaars & Prof. Shuji Nakamura ===

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'''Directors:''' [https://scholar.google.com/citations?user=CO1qY8cAAAAJ Prof. Steven DenBaars] (Google Scholar) • [https://scholar.google.com/citations?user=7Esq3V8AAAAJ Prof. Shuji Nakamura] (Nobel Laureate, 2014 — Google Scholar) • [https://ssleec.ucsb.edu/ SSLEEC Website]

Leads development of III-nitride (InGaN/GaN) optoelectronic devices including micro-LEDs scaled to the single-micron regime for AR/VR displays, edge-emitting laser diodes, and advanced LED architectures with metasurface and distributed Bragg reflector integration.

'''Selected Recent Publications:'''
* ''High External Quantum Efficiency in Ultra-small Amber InGaN MicroLEDs Scaled to 1 μm'' — '''Applied Physics Letters''' (2024). [https://doi.org/10.1063/5.0235915 DOI]
* ''Metasurface Light-Emitting Diodes with Directional and Focused Emission'' — '''Nano Letters''' (2023). [https://doi.org/10.1021/acs.nanolett.3c03272 DOI]

| style="vertical-align: top; width: 320px;" |
[[File:SSLEEC_MicroLED_DBR_SEM.png|thumb|300px|Angled SEM of a 10×10 μm InGaN/GaN micro-LED with distributed Bragg reflectors achieving 130% higher light output.]]

[[File:SSLEEC_GaN_LED_DeviceStack.png|thumb|300px|GaN-based LED/laser diode epitaxial device stack for blue-violet emission.]]

|}





== Advanced Materials & Novel Devices ==

<div style="border-left: 4px solid #d48806; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Topological semimetals, memristive crossbar arrays, plasma nanoscience, and neuromorphic hardware — pushing the boundaries of materials science and unconventional computing architectures.''
</div>



=== Stemmer Research Group — Prof. Susanne Stemmer ===

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'''PI:''' [https://scholar.google.com/citations?user=XFlNLAsAAAAJ Prof. Susanne Stemmer] (Google Scholar) • [https://stemmer.materials.ucsb.edu/ Group Website]

Investigates quantum materials including functional and correlated complex oxides and topological semimetals, with emphasis on thin-film epitaxial growth (MBE), quantum transport, and electronic structure engineering at heterostructure interfaces.

'''Selected Recent Publications:'''
* ''Two-Dimensional Topological Insulator State in Cadmium Arsenide Thin Films'' — '''Physical Review Letters''' 130, 046201 (2023). [https://doi.org/10.1103/PhysRevLett.130.046201 DOI]
* ''Similarity in the Critical Thicknesses for Superconductivity and Ferroelectricity in Strained SrTiO3 Films'' — '''Applied Physics Letters''' (2022). [https://doi.org/10.1063/5.0096834 DOI]

| style="vertical-align: top; width: 320px;" |
[[File:Stemmer_Cd3As2_HAADF_STEM.png|thumb|300px|High-resolution HAADF-STEM of a Cd3As2 topological semimetal thin film grown by MBE, revealing ordered cadmium vacancies at atomic resolution.]]

[[File:Stemmer_SrTiO3_QSTEM_Vacancy.png|thumb|300px|Quantitative STEM image revealing individual strontium vacancy sites in SrTiO3 with picometer-scale displacement mapping.]]

|}



=== Strukov Research Group — Prof. Dmitri Strukov ===

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'''PI:''' [https://scholar.google.com/citations?user=SbPe9WEAAAAJ Prof. Dmitri Strukov] (Google Scholar) • [https://sites.google.com/site/strukov/home Group Website]

Develops novel memristive (resistive switching) devices and hybrid CMOS/memristor circuits for neuromorphic computing, in-memory computing, and hardware accelerators for neural networks and optimization problems.

'''Selected Recent Publications:'''
* ''Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems'' — '''ACS Nano''' (2023). [https://doi.org/10.1021/acsnano.3c03505 DOI]
* ''4K-Memristor Analog-Grade Passive Crossbar Circuit'' — '''Nature Communications''' 12 (2021). [https://doi.org/10.1038/s41467-021-25455-0 DOI]

| style="vertical-align: top; width: 320px;" |
[[File:Strukov_4K_Memristor_Crossbar_SEM.png|thumb|300px|SEM of a 64×64 passive memristive crossbar array (4,096 devices) with Ti/Al/TiN electrodes and Al2O3/TiO2-x switching layers.]]

[[File:Strukov_Memristor_Einstein_Conductance.png|thumb|300px|4K-pixel grayscale Einstein image programmed into the memristive crossbar with <4% tuning error, demonstrating analog-grade conductance control.]]

|}



=== Gordon Lab — Prof. Mike Gordon ===

{| style="width: 100%;"
| style="vertical-align: top; padding-right: 15px;" |
'''PI:''' [https://scholar.google.com/citations?user=HUM5shgAAAAJ Prof. Michael J. Gordon] (Google Scholar) • [http://sites.chemengr.ucsb.edu/~mjgordon/research/home.html Group Website]

Works on plasma science and engineering (atmospheric and non-thermal plasmas), catalysis in molten metals for methane pyrolysis and hydrogen production, and nanoscale fabrication including colloidal lithography and micro-LED characterization.

'''Selected Recent Publications:'''
* ''AC Plasmas Directly Excited in Liquid-Phase Hydrocarbons for H2 and Unsaturated C2 Hydrocarbon Production'' — '''Journal of the American Chemical Society''' (2025). [https://doi.org/10.1021/jacs.4c13685 DOI]
* ''Dry Reforming of Methane Catalysed by Molten Metal Alloys'' — '''Nature Catalysis''' 3, 83–89 (2020). [https://doi.org/10.1038/s41929-019-0416-2 DOI]

| style="vertical-align: top; width: 320px;" |
[[File:Gordon_Plasma_Shadowgraph_Hexane.png|thumb|300px|Laser shadowgraph of a nanosecond-pulsed plasma discharge in liquid hexane showing streamer propagation and shock waves.]]

[[File:Gordon_AC_Plasma_Hexane_Timelapse.png|thumb|300px|Time-resolved high-speed images of AC arc discharges in liquid hexane at 17.3 kHz for hydrogen production.]]

|}





== Microfluidics & MEMS ==

<div style="border-left: 4px solid #08979c; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Nanofluidic transport, lab-on-chip biosensors, and microfabricated biomedical devices — bridging nanofabrication with biological and chemical applications.''
</div>



=== Pennathur Lab — Prof. Sumita Pennathur ===

{| style="width: 100%;"
| style="vertical-align: top; padding-right: 15px;" |
'''PI:''' [https://scholar.google.com/citations?user=dVbZMA0AAAAJ Prof. Sumita Pennathur] (Google Scholar) • [https://nanolab.engineering.ucsb.edu/ Group Website]

Studies electrokinetic transport in nanofluidic channels, ionic current rectification in bipolar nanochannels, and the design of nanofluidic diodes and biosensors, combining experimental micro/nanofabrication with computational modeling.

'''Selected Recent Publications:'''
* ''Coupling Charge-Regulated Interfacial Chemistry to Electrokinetic Ion Transport in Bipolar SiO2–Al2O3 Nanofluidic Diodes'' — '''Advanced Materials Interfaces''' (2024). [https://doi.org/10.1002/admi.202400495 DOI]
* ''Nanofluidic Diodes Based on Asymmetric Bio-Inspired Surface Coatings in Straight Glass Nanochannels'' — '''Faraday Discussions''' (2023). [https://doi.org/10.1039/D3FD00074E DOI]

| style="vertical-align: top; width: 320px;" |
[[File:Pennathur_Nanochannel_Embedded_Electrode.png|thumb|300px|Cross-section schematic and SEM of a fused silica nanofluidic channel with embedded electrodes for electric double layer modulation.]]

[[File:Pennathur_Silicon_Microneedle_SEM.png|thumb|300px|SEM of silicon microneedle array for minimally invasive biofluid extraction, fabricated using MEMS techniques.]]

|}





== Astronomical Instrumentation ==

<div style="border-left: 4px solid #531dab; padding-left: 12px; margin-bottom: 10px; color: #333;">
''Superconducting photon-counting detectors for ground-based astronomy — fabricating the cameras that image exoplanets.''
</div>



=== Mazin Laboratory — Prof. Ben Mazin ===

{| style="width: 100%;"
| style="vertical-align: top; padding-right: 15px;" |
'''PI:''' [http://web.physics.ucsb.edu/~bmazin/index.html Prof. Benjamin Mazin] • [https://inspirehep.net/authors/1037976 INSPIRE-HEP Publications] • [http://web.physics.ucsb.edu/~bmazin/publications/ Lab Publication List]

Pioneers Microwave Kinetic Inductance Detectors (MKIDs) — superconducting photon-counting sensors with zero read noise that measure each photon's energy, arrival time, and position. Deploys MKID-based cameras (MEC, XKID) at major telescopes for direct imaging of exoplanets.

'''Selected Recent Publications:'''
* ''Characterization of Photon Arrival Timing Jitter in Microwave Kinetic Inductance Detector Arrays'' — '''Applied Physics Letters''' (2024). [https://doi.org/10.1063/5.0190172 DOI]
* ''Characterizing the Dark Count Rate of a Large-Format MKID Array'' — '''Optics Express''' (2023). [https://doi.org/10.1364/OE.484599 DOI]

| style="vertical-align: top; width: 320px;" |
[[File:Mazin_MKID_20K_Array_Package.jpg|thumb|300px|The MEC 20,440-pixel MKID array mounted in its gold-plated copper package — deployed at the Subaru 8m Telescope for high-contrast exoplanet imaging.]]

[[File:Mazin_MKID_10K_Array_Zoom.jpg|thumb|300px|10,000-pixel MKID array in gold sample box with progressive zoom-ins showing pixel grid and individual lumped-element resonator structures.]]

|}





----

<div style="border: 1px solid #d9d9d9; border-radius: 6px; padding: 16px; margin-top: 20px; background: #fafafa;">
== Publication Archives ==

* [[PubList2018|'''2018 Publications''']]
* [[Older Publications|'''Earlier Publications''']]
* [[Template:Publications|Select Publications]] — ''A selection of publications that utilized the UCSB NanoFab''

== Research Presentations ==

* [[Photonics Presentations|Photonics]]
* [[Electronics Presentations|Electronics]]
* [[THz Physics Presentations|THz Physics]]

== Research Image Galleries ==

* [[Photonics Pictures|Photonics]] • [[Electronics Pictures|Electronics]] • [[MEMS Pictures|MEMS]] • [[Physics Pictures|Physics]] • [[Fluidics Pictures|Fluidics]]
</div>

[[Category:Research]]
[[Category:Publications]]
[[Category:Nanofabrication]]
__FORCETOC__

E-Beam 4 (CHA)

2026-04-22T21:32:06Z

John d: max dep thickness put into bullet list

{{tool2|{{PAGENAME}}
|picture=e-beam4.jpg
|type = Vacuum Deposition
|super= Michael Barreraz
|super2= Bill Millerski
|phone=(805)839-7975
|location=Bay 3
|email=dfreeborn@ece.ucsb.edu
|description = Multi-Wafer Evaporator
|manufacturer = CHA Industries
|model = SEC-600-RAP
|materials =
|toolid=10
}}
[[File:EBeam4 Controls.jpeg|thumb|EBeam4's controls]]

== About ==
This electron-beam evaporation system is a bell-jar type system and has the capability to do up to 9-4” wafers in a lift-off configuration and up to 18-4” wafers in a sidewall coverage configuration. Rotational motion in combination with baffling is used for lift-off and provides roughly 5% uniformity across a 4” wafer. The system has an 8-pocket e-beam source and an Inficon IC/5 deposition controller that allows for programming of fully automated multiple layer depositions.

The sidewall coverage fixturing uses full planetary motion to provide coverage over all sidewalls.

The metals available for deposition are Al, Ti, Au, Pt, Ni, Pd, Ag, Ge, and Cr.

This system is used for n-type ohmic contact metalization to compound semiconductors, Schottky contacts to semiconductors, bond pads, and other general metalizations.

== Detailed Specifications ==
*Temescal 10kV power supply
*1-Temescal 8-pocket series, 260 e-beam sources
*Cryo-pumped system with ~ 5e-7 ultimate base pressure
*Rotation with baffle for 5% uniformity over 4” wafer
*Automatic vacuum sequencing
*Temescal e-beam sweep control
*Inficon IC/5 programmable crystal thickness monitoring system
*Automatic deposition of multiple layer stacks
*Sample size:
**Pieces or
**9x 4” wafers for lift-off (normal incidence)
**24x 4” wafers for sidewall coverage (planetary)
**4x 6-inch wafers for normal incidence
*Metals: Al, Ti, Au, Pt, Ni, Pd, Ag, Ge, and Cr.
*Maximum deposition thickness during a run is limited to 1.0 microns.

== Documentation ==
*[https://wiki.nanofab.ucsb.edu/w/images/4/46/EB4_Operating_Instructions_6-6-24.pdf Operating Procedures]
*[https://wiki.nanofab.ucsb.edu/w/images/9/9b/EBeam4_Planetary_Fixture_SOP_12-11-25.pdf Planetary Fixture SOP] (Requires SUM Reservation)

== Recipes ==

=== Materials Table ===
For tables listing all available materials and deposition parameters, please visit the [[E-Beam_Evaporation_Recipes#Materials_Table_(E-Beam #4)|'''E-Beam Recipe Page''']].

=== Process Control Data ===
*E-Beam 4 Ti: [https://docs.google.com/spreadsheets/d/1W7OFMAlRIcbpjm7FsbCh9ZLCCbhEp0bhtAC7UqEmJ5U/edit?gid=0#gid=0 Titanium Datasheet] & [https://docs.google.com/spreadsheets/d/1W7OFMAlRIcbpjm7FsbCh9ZLCCbhEp0bhtAC7UqEmJ5U/edit?gid=384597990#gid=384597990 Titanium Plots]
*E-Beam 4 Au: [https://docs.google.com/spreadsheets/d/1W7OFMAlRIcbpjm7FsbCh9ZLCCbhEp0bhtAC7UqEmJ5U/edit?gid=834604706#gid=834604706 Gold Datasheet] & [https://docs.google.com/spreadsheets/d/1W7OFMAlRIcbpjm7FsbCh9ZLCCbhEp0bhtAC7UqEmJ5U/edit?gid=721807140#gid=721807140 Gold Plots]
*E-Beam 4 Cr: [https://docs.google.com/spreadsheets/d/1W7OFMAlRIcbpjm7FsbCh9ZLCCbhEp0bhtAC7UqEmJ5U/edit?gid=1629968393#gid=1629968393 Chromium Datasheet] & [https://docs.google.com/spreadsheets/d/1W7OFMAlRIcbpjm7FsbCh9ZLCCbhEp0bhtAC7UqEmJ5U/edit?gid=701729811#gid=701729811 Chromium Plots]
*E-Beam 4 Ni: [https://docs.google.com/spreadsheets/d/1W7OFMAlRIcbpjm7FsbCh9ZLCCbhEp0bhtAC7UqEmJ5U/edit?gid=649905488#gid=649905488 Nickel Datasheet] & [https://docs.google.com/spreadsheets/d/1W7OFMAlRIcbpjm7FsbCh9ZLCCbhEp0bhtAC7UqEmJ5U/edit?gid=1525197973#gid=1525197973 Nickel Plots]

E-Beam 1 (Sharon)

2026-04-22T19:36:20Z

John d: /* Detailed Specifications */ added film limit

{{tool2|{{PAGENAME}}
|picture=e-beam1.jpg
|type = Vacuum Deposition
|super= Michael Barreraz
|super2= Bill Millerski
|phone=(805)839-7975
|location=Bay 3
|email=mikebarreraz@ece.ucsb.edu
|description = Four Pocket Electron Beam Evaporator
|manufacturer = Sharon Vacuum Co., Inc.
|toolid=7
}}
[[File:EBEAM1 Controls Sept2022.jpeg|thumb|EBeam#1 Deposition + Beam Controllers]]

=About=

The Sharon is a cryo-pumped thin film evaporator with a Telemark 8 pocket electron beam evaporation source. Fixturing in EBeam1 will accept any size sample up to 4-inch diameter. In addition, a rotation fixture is easily installed which permits adjustable angle, 360° rotation of any size sample, up to 4-inch diameter. This feature is particularly useful for promoting step coverage of irregular surfaces.

EBeam1 is used for the evaporation of high purity metals, e.a. Al, Au, Ni, Ge, AuGe, Ti, Pt etc., for interconnect and ohmic contact metallization for fabrication of III-V compound semiconductor and silicon device fabrication.

=Detailed Specifications=

*Cryopump: CTI Cryotorr 8F with air-cooled compressor
*Pumping speed: 4,000 l/sec. for H2O, 1,500 l/sec. for air, 2,200 l/sec. for H2, 200 l/sec. for Ar
*Mechanical Pump: Ebara EV-A10, 35 CFM
*Electron Beam Source: Temescal, Model STIH-270-2MB, four 15 cc hearths
*Electron Beam Power Supply: Temescal, Model CV-6SLX, 0 - 10 kV dc, 0–600 mA dc beam current; TemEBeam Sweep Control
*Deposition Control: : Inficon IC/5, 6 film programs; 37 parameters for automatic or manual deposition control based on a resonating quartz crystal sensor
*Pieces up to Four - 4" wafers in one run.
*For single wafers: tilt with motorized rotation and sample lowering for higher effective rates, sidewall coverage, angled evaporation.
*Maximum allowed film thickness: 1µm
**Please ask supervisor if you need to go thicker
**Please provide justification for your needs (eg. Not “2 µm is a nice round number”)

=Documentation=

*[https://wiki.nanofab.ucsb.edu/w/images/f/f0/EB-1_operation_instructions_6-6-24.pdf EBeam 1 Operating Procedure]
**Operating Instructions
**[https://wiki.nanofab.ucsb.edu/w/images/a/a1/EB1_Rotation_Fixture_SOP_5-16-25.pdf Rotation Fixture SOP]
**[[E-Beam 1 - 4-inch, 4-wafer Fixture SOP|4-inch, 4-wafer Fixture SOP]]

=Recipes=

*See the [[E-Beam_Evaporation_Recipes#Materials_Table_(E-Beam #1)|'''E-Beam Recipe Page''']], for the materials tables and deposition parameters for various materials.
*[[Process Group - Process Control Data#E-Beam 1 (Sharon) - Process Control|'''Process Control Data''']] - Calibration data for the most utilized metals on this sytem.

Tube Furnace (Tystar 8300)

2026-04-21T18:11:49Z

John d: corrected model

{{tool|{{PAGENAME}}
|picture=Tystar.jpg
|type = Thermal Processing
|super= Tony Bosch
|phone=(805)839-3918x217
|location=Bay 4
|email=bosch@ece.ucsb.edu
|description = Tystar 8" 3-Tube Oxidation/Annealing System
|manufacturer = Tystar Corporation
|model = Tytan 3-Stack 8300
|materials =
|toolid=999
}}
==About==
The three stack Tystar 8” furnace is used primarily for 3 processes. The processes are dedicated for specific tubes as follows:

*'''Tube #1''': SOG curing & low-temp oxidation
*'''Tubes #2 and #3''': Dry or wet oxidation of silicon (unprocessed, clean)
*'''Tube #3''': General furnace annealing & oxidation, including processed material

==Process Information==

Recipe Characterization Data, such as thermal oxidation times, can be found on the recipe page:

*[[Thermal Processing Recipes|Thermal Processing Recipes: Tystar 8300]]

Use the [http://cleanroom.byu.edu/OxideTimeCalc BYU] or [http://www.lelandstanfordjunior.com/thermaloxide.html Stanford Leland Jr.] Thermal Oxidation Calculators to determine the time and temperature that will be necessary for your process needs. You can "calibrate" your oxidations to the Stanford calculator by adjusting the ''Partial Pressure'' on the calculator to match your experimental data.

Keep in mind that all process must be 30 minutes in length at a minimum. Processes less than 30 minutes will suffer from poor uniformity because the process tube will not have sufficient time to saturate with O2 or DI-H2O.

Each process tube can accommodate up to one hundred 8” wafers per cycle. We have boats for 2", 3", 4", 6", 8" and irregular shaped pieces.

The maximum temperature is 1100°C for the system. Gases used are O2, Steam from DI-H2O, N2.

===Gases Available===

*N2 (15/5 slpm)
*O2 High-range "O2HI" - 15 slpm
*O2 Low-range "O2LO" - 1 slpm
*All gasses flow through the H2O bubbler, which can optionally be filled with heated water to flow steam, or evacuated (no steam, gas only).

==Recipes==

* '''Tube 1''' - low temperature tube. Applications: Wafer Bonding, Curing Spin-on-glass/dielectrics, AlGaAs oxidation, annealing.
* '''Tube 2''' - ''CLEAN'' Silicon only, Wet and Dry oxidations only.
* '''Tube 3''' - Wet/Dry Oxidation, Annealing
* [[Thermal Processing Recipes#Available Recipes (Tystar 8300)|'''Thermal Processing Recipes (Tystar 8300)''']] - lists all available recipes on each tube
* [[Thermal Processing Recipes#Process Limits (Tystar 8300)|'''Process Limits''']] - each tube has different process limits - see this page for requirements for each tube. Contact [[Tony Bosch|supervisor]] for advice on long (≥24hr) or high-temp processes.

===[[Thermal Processing Recipes#Tystar 8300|Oxidation Rates & Data]]===
''See the above recipes page for data on oxidation rates for standard oxidation recipes.''

==Useful Information==
[//wiki.nanotech.ucsb.edu/w/images/8/89/TystarMechDrawWaferBoat.pdf Tystar Wafer Boat Drawing - 4" Wafer with 0.5mm Slots]

==See Also==

*[http://www.tystar.com/ Tystar] - Manufacturer of the tool
*[http://cleanroom.byu.edu/OxideThickCalc Silicon Thermal Oxide Thickness Calculator (BYU)] - Use this on-line calculator to calculate times for silicon oxidation.
*[http://www.lelandstanfordjunior.com/thermaloxide.html Advanced Silicon Thermal Oxide Thickness Calculator (Stanford Leland Jr.)] - Another thermal oxide calculator, with flexibility to vary ''partial pressure'' parameter to calibrate to your own process.

==Operational Instructions==

*[//wiki.nanotech.ucsb.edu/w/images/8/8a/Tystar_Operational_Procedure.pdf Operating Instructions]

ICP Etching Recipes

2026-04-20T22:54:45Z

John d: /* High Rate Bosch Etch (DSEIII) */ added Plasma Dicing section with "coming soon" info

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''[[ICP Etching Recipes#Process Control Data (DSEiii)|Process Control Data below]]''' - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==
*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with Al2O3 hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**Larger open area → lower selectivity & lower etch rate.
***<1% center to edge variability in etch rate for small open area.
***More variation across wafer for larger open area (eg. plasma dicing)
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}

=== '''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)''' ===
[[File:DSE plot.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281|232x232px]]
* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots''']

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
We have a new wafer-mounting process for through-silicon etching, using the UV-Release Dicing tape. Contact [[Demis D. John|staff]] for more info.
-- [[Demis D. John|Demis]] 2026-02-10

'''NOTE''':
'''DO NOT RUN''' the wax-mounting process without discussing with staff first. The wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer!
''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11

{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
with wax-mounting (small pieces only)
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

=== Plasma Dicing (DSEIII) ===
'''''Coming Soon''''': Plasma Dicing process with Dicing Tape as backing film.

This process has been developed by staff, is currently in the final stages of finalizing a public recipe. [[Demis D. John|'''''Contact staff''''']] if you want to use it sooner.

==Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)==

*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
**Smooth, Vertical, E.R. uniformity is within 5% on wafer
**Tested with 4" wafers that are ~50% open with UV6 PR
*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Older, alternate Si "shallow/smooth" etch recipe.
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

== SiO2 Etch (DSEiii) ==
These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].
*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
**Vertical/Smooth
**Tested by mounting 1cmx1cm piece with oil on 4" Si

==F-ICP Backup Recipes (DSEiii)==
These recipes were developed to serve as backup processes for the calibrated [[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|'''Fluorine-ICP''']] SiO2 and Si etches [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]].

[https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing FICP to DSE etch processes].

*'''[[ICP Etching Recipes#Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)|Si Etch v1 (⭐️Production)]]'''
*'''[[ICP Etching Recipes#SiO2 Etch (DSEiii)|SiO2 Etch v1 (⭐️Production)]]'''

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the [[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|'''Process Control Data below''']] - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

=== Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
[[File:FICP-Si.png|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots''']

==SiO2 Etch Recipes (Fluorine ICP Etcher)==
[[File:FL-ICP_50W_SiO2_etch_with_Ru_Hard_Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|thumb|266x266px|50W SiO2 Etch w/ Ru Hardmask]]
[[File:FL-ICP_200W_SiO2_Etch_with_Ru_Hardmask_-_Ning_Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|thumb|266x266px|200W SiO2 Etch w/ Ru Hardmask (Ning Cao)]]
*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.

=== [//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] ===

* Click above for [http://wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf Full Process Traveler]
** Process written for Sputtered Ru & I-Line GCA Stepper litho
** Can be transferred to ALD Ru or DUV/EBL Litho.

*''Ning Cao & Bill Mitchell, 2019-06''
*''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
*''Etch also works well with PR masking''
*''Chemistry: CHF3/CF4''
*''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
*Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
*50W Bias: ('''recommended''')
**Selectivity to photoresist: 1.10–1.20
**SiO2 selectivity to Ru: 36
**SiO2 etch rate: 263nm/min
**''Smoothest vertical etch for SiO2.''
*200W Bias: (higher etch rate)
**SiO2 selectivity to Ru: 38
**SiO2 etch rate: 471nm/min
*This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
*Updates: Many users have found that SiO2-masking the Ru hardmask results in vastly improved photoresist selectivity, making litho+etch of small features much better.
**Layer stack looks like: SiO2 (or other dielectric target layer to etch) / Ru hardmask / SiO2 hardmask (thin) / Photoresist.
**Typically strip the masks+PR with all dry etching. That means the entire etch process (all etches and strips) can be run ''in situ'' on the Panasonic ICP in a rapid single-tool etch process.
===Process Control: SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
[[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots''']

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===
[[File:SEM Image.png|thumb|New PR Strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Old PR strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**45sec-1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=
'''Panasonic ICP#1 is currently down -''' Use Panasonic ICP#2 instead. Most processes directly transfer with only small change in etch rate. Data kept here for historical purposes only.

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure & Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get on the ''back'' of the carrier wafer or you will get Helium cooling errors.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch, and see their SEM's.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
**''This etch is used in our Process Control weekly cals run by [[Process Group Interns|NanoFab Interns]]. Very stable over time ±5%.''
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

===Process Control: SiO2 Etch with CHF3/CF4 (Panasonic 2)===
[[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|thumb|269x269px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts] for SiO2 etching.|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]''Weekly cal etches of the CF4/CHF3 SiO2 etch, run by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots''']

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*GaAs Etch Cal - ''Noah Dutra & Fatt Foong, 2025-02-12''
**Etch Rates ~1um/min, Selectivity to SiO2 ~ 27:1, Sidewalls ~ 90°
**Etch Rate/Selectivity [https://wiki.nanofab.ucsb.edu/w/images/7/76/GaAs_pressure_experiment.png highly sensitive to pressure] (image credit: Terry Guerrero)
**Cal Sample: ~1cm sample etched mounted with oil onto 150mm Si carrier
**Recipe: 0.5Pa, 100/900W, N2/Cl2=10/20sccm
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf Non-Calibration GaAs Etch Recipes - Panasonic 2 - Cl2N2]

===Process Control: GaAs Etch with N2/Cl2 (Panasonic 2)===
[[File:GaAs Etch ICP2 SPC.png|alt=example ICP2 process control chart|thumb|249x249px|[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for GaAs etching.|link=https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281]]
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=0#gid=0 GaAs Etch with N2/Cl2 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 GaAs Etch with N2/Cl2 - '''Plots''']

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

=== Process Tips ===
* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* InP requires fairly high temperatures for making the Indium products volatile - so going to full-wafers (which are cooler) may requiring the table temperature. We have found that temperatures of ~150⁰C minimum may be required for preventing grassing etc.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==InP Ridge Etch (Oxford ICP Etcher)==
===High-Temp (200°C) InP Etch Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
[[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|thumb|218x218px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for 200°C InP Etch|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

===Low-Temp (60°C) InP Etch Process===
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: Low-Temp (60°C) InP Etch ====
[[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts] for 60°C InP Etch|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots''']

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''OLD 4" configuration: [https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: GaN Etch ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''

* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.

* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]

[[File:GaN SPC.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279|219x219px]]OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]
==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning
*''[https://wiki.nanofab.ucsb.edu/w/images/d/d1/GaAs_Etch_Ver3_Recipe_Finalized_120925.pdf Std GaAs Etch - Cl2/N2 - 30C Etch Characterization] - F. Foong, 2025-12-10''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

E-Beam Lithography System (Raith EBPG 5150+)

2026-04-19T04:57:20Z

John d: /* Operating Procedures */ link to SOP v1.0

{{tool|{{PAGENAME}}
|picture=RaithEBPG_2026-03.png
|type = Lithography
|super= Bill Mitchell
|location=Bay 7
|description = Vector Scan Electron Beam Lithography System
|manufacturer = [https://raith.com Raith GmbH]
|model = EBPG 5150+
|materials =
|toolid=87
}}
{{ToolActions
|toolid = 87
|ProcessControlURL =
|ProceduresURL =
|TrainingURL =
}}

__TOC__

== About ==
'''Raith EBPG5150 Plus - Ultra High-Performance e-Beam Writer'''

The Raith EBPG Electron-Beam Lithography (EBL) tool is a high-speed, high current lithography tool for achieving lower than 10nm features, but also capable of very fast writing with the 350nA max current and higher speed 125MHz pattern generator & increased write-field size. The tool has fully automated/programmable aperture switching and beam calibrations. This enables the Raith EBL to write full-wafers at high speed for larger features (high current) and automatically switch+calibrate to exposure small (<<50nm) features in a single exposure, with sophisticated mix+match capabilities and pattern generation for maximum throughput while achieving the best high-resolution performance.

== Detailed Specifications ==
* Minimum feature size: 8nm
** 0.6nm stage movement resolution
* Layer-to-Layer Alignment/Overlay Accuracy: ≤5nm
* Maximum wafer/substrate size:
** Diameter: 150mm wafer (155mm x 155mm stage traverse)
** Thickness: 3mm
** (smaller piece-parts are common)
* 10-holder load-lock
** 2x Cassette loader/substrate holders available,
** Programmable/automated loading/switchout available via software.
* Beam Voltage: 50vK + 100kV
* Beam Current: 50pA – 350nA
** Automatic aperture changer
* Scanner Speed (or other speed specs): 125MHz
* Exposure Field Size: Continuously variable from < 0.1 mm to 1.048 mm field size
** Single-nanometer stepping within the field
** Available at all beam currents and voltages
* Stand-alone optical alignment station (for pre-alignment of wafer to holder)
* Other capabilities:
** Automatic, dynamic off-axis focus, stigmation and field distortion corrections
** Integrated Laser height sensor for field-by-field or pre-mapping mode with direct electron feedback to deflection and focus corrections.

*Advanced write software available: Layout BEAMER from GeniSys Inc.
** Automated proximity correction of patterns possible
** Ability to manually position write fields within a pattern for optimum inter-field writing performance
** Ability to adjust beam scanning strategy within a write field for optimum intra-field writing performance
** Fine tuning of line-edge roughness by shot pitch correction & non-Manhattan scanning for curved edges

== Operating Procedures ==

* [[Media:Raith EBPG5150 - Operation Guide.pdf|EBPG5150 - Operation Guide]]

=== Training Procedure ===

* Contact Bill Mitchell for training, via SUM:
{{ToolTrainingButton
|toolid = 87
}}

== [[Direct-Write Lithography Recipes#E-Beam Lithography Recipes (Raith EBPG 5150+)|Recipes]] ==
All recipes can be found on the following page:

* ''Recipes > Litho. > Direct-Write > [[Direct-Write Lithography Recipes#E-Beam Lithography Recipes (Raith EBPG 5150+)|'''EBL Recipes''']].''

File:Raith EBPG5150 - Operation Guide.pdf

2026-04-19T04:56:49Z

John d: SOP for Raith EBPG 5150

== Summary ==
SOP for Raith EBPG 5150

E-Beam Lithography System (Raith EBPG 5150+)

2026-04-19T04:55:53Z

John d: /* Detailed Specifications */ added SOP + tool training button

{{tool|{{PAGENAME}}
|picture=RaithEBPG_2026-03.png
|type = Lithography
|super= Bill Mitchell
|location=Bay 7
|description = Vector Scan Electron Beam Lithography System
|manufacturer = [https://raith.com Raith GmbH]
|model = EBPG 5150+
|materials =
|toolid=87
}}
{{ToolActions
|toolid = 87
|ProcessControlURL =
|ProceduresURL =
|TrainingURL =
}}

__TOC__

== About ==
'''Raith EBPG5150 Plus - Ultra High-Performance e-Beam Writer'''

The Raith EBPG Electron-Beam Lithography (EBL) tool is a high-speed, high current lithography tool for achieving lower than 10nm features, but also capable of very fast writing with the 350nA max current and higher speed 125MHz pattern generator & increased write-field size. The tool has fully automated/programmable aperture switching and beam calibrations. This enables the Raith EBL to write full-wafers at high speed for larger features (high current) and automatically switch+calibrate to exposure small (<<50nm) features in a single exposure, with sophisticated mix+match capabilities and pattern generation for maximum throughput while achieving the best high-resolution performance.

== Detailed Specifications ==
* Minimum feature size: 8nm
** 0.6nm stage movement resolution
* Layer-to-Layer Alignment/Overlay Accuracy: ≤5nm
* Maximum wafer/substrate size:
** Diameter: 150mm wafer (155mm x 155mm stage traverse)
** Thickness: 3mm
** (smaller piece-parts are common)
* 10-holder load-lock
** 2x Cassette loader/substrate holders available,
** Programmable/automated loading/switchout available via software.
* Beam Voltage: 50vK + 100kV
* Beam Current: 50pA – 350nA
** Automatic aperture changer
* Scanner Speed (or other speed specs): 125MHz
* Exposure Field Size: Continuously variable from < 0.1 mm to 1.048 mm field size
** Single-nanometer stepping within the field
** Available at all beam currents and voltages
* Stand-alone optical alignment station (for pre-alignment of wafer to holder)
* Other capabilities:
** Automatic, dynamic off-axis focus, stigmation and field distortion corrections
** Integrated Laser height sensor for field-by-field or pre-mapping mode with direct electron feedback to deflection and focus corrections.

*Advanced write software available: Layout BEAMER from GeniSys Inc.
** Automated proximity correction of patterns possible
** Ability to manually position write fields within a pattern for optimum inter-field writing performance
** Ability to adjust beam scanning strategy within a write field for optimum intra-field writing performance
** Fine tuning of line-edge roughness by shot pitch correction & non-Manhattan scanning for curved edges

== Operating Procedures ==

* EBPG5150 - Operation Guide

=== Training Procedure ===

* Contact Bill Mitchell for training, via SUM:
{{ToolTrainingButton
|toolid = 87
}}

== [[Direct-Write Lithography Recipes#E-Beam Lithography Recipes (Raith EBPG 5150+)|Recipes]] ==
All recipes can be found on the following page:

* ''Recipes > Litho. > Direct-Write > [[Direct-Write Lithography Recipes#E-Beam Lithography Recipes (Raith EBPG 5150+)|'''EBL Recipes''']].''

Wet Etching Recipes

2026-04-16T22:10:47Z

John d: /* Table of Wet Etching Recipes */ added InGaAsP stop-etch removal.

__TOC__

==Chemicals Available==

*[[Chemical List|'''The Chemical Lists''']] show stocked chemicals, photolithography chemicals, and how to bring new chemicals.

=='''Table of Wet Etching Recipes'''==
''Use the ↑ ↓ Arrows in the header row to sort the entire table by material, selectivity, etchant etc.''
{| class="wikitable sortable"
|-
!Material!!Etchant!!Rate (nm/min)!!Anisotropy!!Selective to!!Selectivity!!Ref.!!Notes!!Confirmed By/Date
|-
|Photoresist, polymers/organics
|H2SO4:H2O2 = 3:1
[[Wet Etching Recipes#Organic%20removal|Piranha Solution]]
|typ. 5-10min etch for polymer residue
|
|Cr, W, Au, Pt, Si, SiO2, SiN
|
|
|'''''Dangerous''''' boiling hazard - see '''''[[Wet Etching Recipes#Piranha%20Solution|Piranha Solution]]'''''
section below. Etches Ti, Ni, Hf
|[[Demis D. John]], 2017
|-
|InP
|H3PO4:HCl = 3:1
|~1000
|Highly
|InGaAsP
|High
|[http://tel.archives-ouvertes.fr/docs/00/76/94/02/PDF/VA2_LAMPONI_MARCO_15032012.pdf Lamponi (p.102)]
|
|
|-
|InP||H3PO4:HCl = 3:1||~1000||Highly||InGaAs||High||[http://tel.archives-ouvertes.fr/docs/00/76/94/02/PDF/VA2_LAMPONI_MARCO_15032012.pdf Lamponi (p.102)]||
|
|-
|InP
|HCl:H2O = 3:1
|~5000
|
|InGaAs or InGaAsP
~200nm stop-etch
|High
|
|Bubbles while etching
|
|-
|InGaAs
|H2SO4:H2O2:H2O = 1:1:10
|~600
|
|InP
|High
|
|Exothermic, may reduce selectivity if hot
|
|-
|InGaAsP
|H2SO4:H2O2:H2O = 1:1:10
|~600
|
|InP
|High
|
|Exothermic, may reduce selectivity if hot
(same as InGaAs stop-etch removal)
|
|-
|GaAs
|NH4OH:H2O2 = 1:30
|
| -
|AlGaAs,
Al > 80%

~200nm stop-etch
|High
|
|
|Garrett Cole
|-
|AlGaAs,
Al ≥80%
|HF:H2O = 1:20
|
| -
|GaAs
|High
|
|
|Garrett Cole
|-
|Oxide of InP
|NH4OH:H2O = 1:10
|1min to remove
|
|InP
|unknown
|
|
|[[Ning Cao]]
|-
|Oxide of GaAs
|HCl:H2O = 1:10
|1min to remove
|
|GaAs
|unknown
|
|
|[[Demis D. John]]
|-
|Al2O3 ''(ALD Plasma 300C)''||Developer: 300MIF||~1.6||None
|Most non-Al Materials.
|High||Measured in-house||Rate slows with time.||JTB
|-
|Al2O3 ''(ALD Plasma 300C)''||Developer: 400K||~2.2||None
|Most non-Al Materials.
|High||Measured in-house||Rate slows with time.||JTB
|-
|Al2O3 ''(ALD Plasma 300C)''||Developer: 400K (1:4)||~1.6||None
|Most non-Al Materials.
|High||Measured in-house||Rate slows with time.||JTB
|-
|Al2O3 ''(ALD Plasma 300C)''||NH4OH:H2O2:H2O (1:2:50)||~<0.5|| || || ||Measured in-house||Rate slows with time||JTB
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Al2O3 ''(IBD)'']
|HF ("Buffered HF Improved", Transene)
|~170
|None
|Photoresist
|High
|Measured in-house
|May need to increase adhesion with thin SiO2 layer, and 100°C baked HMDS.
|Biljana Stamenic,
2017-12
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Al2O3 ''(IBD)'']
|Developer: 726 MiF
|3.5
|None
|Most non-Al Materials.
|High
|Measured in-house
|
|Demis D. John,
2017-11
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 Al2O3 ''(AJA#4)'']
|Developer: 300 MiF
|4.30
|None
|Most non-Al Materials.
|High
|Measured in-house
|
|Demis D. John
2018-02
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=PECVD_Recipes#SiO2_deposition_.28PECVD_.231.29 SiO2 ''(PECVD #1)'']
|HF ("Buffered HF Improved", Transene)
|~550
|None
|Photoresist
|High
|Measured in-house
|May need to increase adhesion with 100°C baked HMDS.
|Biljana Stamenic
2023
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=PECVD_Recipes#SiO2_deposition_.28PECVD_.232.29 SiO2 ''(PECVD #2)'']
|HF ("Buffered HF Improved", Transene)
|~680
|None
|Photoresist
|High
|Measured in-house
|May need to increase adhesion with 100°C baked HMDS.
|Biljana Stamenic
2023
|-
|SiO2 ''(ALD -BDEAS 300C)''
|HF ("Buffered")
Diluted with DI
BHF:H2O = 1:100
|~7.46
|
|
|
|Measured in-house
|
|Biljana Stamenic
2024
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#SiO2_deposition_.28IBD.29 SiO2 (IBD)]
|HF ("Buffered HF Improved", Transene)
|~260
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanofab.ucsb.edu/wiki/PECVD_Recipes#ICP-PECVD_.28Unaxis_VLR.29 SiO2 LDR ''(Unaxis VLR)'']
|HF ("Buffered HF Improved", Transene)
|~170
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanofab.ucsb.edu/wiki/PECVD_Recipes#ICP-PECVD_.28Unaxis_VLR.29 SiO2 HDR ''(Unaxis VLR)'']
|HF ("Buffered HF Improved", Transene)
|~230
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=PECVD_Recipes#SiN_deposition_.28PECVD_.231.29 Si3N4 (PECVD#1)]
|HF ("Buffered HF Improved", Transene)
|~120
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=PECVD_Recipes#SiN_deposition_.28PECVD_.232.29 Si3N4 (PECVD#2)]
|HF ("Buffered HF Improved", Transene)
|~35
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=PECVD_Recipes#Low-Stress_SiN_deposition_.28PECVD_.232.29 Si3N4 Low-Stress (PECVD#2)]
|HF ("Buffered HF Improved", Transene)
|~30
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Si3N4_deposition_.28IBD.29 Si3N4 (IBD)]
|HF ("Buffered HF Improved", Transene)
|~5
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanofab.ucsb.edu/wiki/PECVD_Recipes#ICP-PECVD_.28Unaxis_VLR.29 SiN ''(Unaxis VLR)'']
|HF ("Buffered HF Improved", Transene)
|~10
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanofab.ucsb.edu/wiki/PECVD_Recipes#ICP-PECVD_.28Unaxis_VLR.29 SiN Low Stress ''(Unaxis VLR)'']
|HF ("Buffered HF Improved", Transene)
|~135
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Ta2O5_deposition_.28IBD.29 Ta2O5 (IBD)]
|HF ("Buffered HF Improved", Transene)
|0.07
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2023
|-
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#TiO2_deposition_.28IBD.29 TiO2 (IBD)]
|HF ("Buffered HF Improved", Transene)
|1.0–2.0
|None
|Photoresist
|High
|Measured in-house
|
|Biljana Stamenic
2014-12
|-
|Si (<100> crystalline)
|KOH (45%) @ 87°C
|~730
|High, Crystallographic, ~55°
|Low-Stress Si3N4 - either [[PECVD Recipes#Low-Stress SiN deposition .28PECVD .232.29|PECVD #2]] or Commercial LPCVD Si3N4
Other Si3N4 also OK.
|LS-SiN: High
PR etches quickly, SiO2 etches slowly.
|Measured In-House
- Search online.
|Use the Covered, Heated vertical bath ([[Wet Benches#Wafer Toxic Corrosive Benches|Dedi cated bath in Bay 4]]). Slight Bubbler.
|Brian Thibeault
2017
|-
!Material!!Etchant!!Rate (nm/min)!!Anisotropy!!Selective to!!Selectivity!!Ref.!!Notes!!Confirmed By/Date
|}

==Wet Etching References==

#[http://ieeexplore.ieee.org/abstract/document/546406/ Etch rates for Micromachining Processing (IEEE Jnl. MEMS, 1996)] - includes tables of etch rates of numerous metals vs. various wet and dry etchants.
#[http://ieeexplore.ieee.org/abstract/document/1257354/ Etch rates for micromachining-Part II (IEEE Jnl. MEMS, 2003)] - expanded tables containing resists, dielectrics, metals and semiconductors vs. many wet etch chemicals.
#[http://www.sciencedirect.com/science/article/pii/S0927796X00000279 Guide to references on III±V semiconductor chemical etching] - exhaustive list of wet etchants for etching various semiconductors, including selective etches.
#[http://transene.com/etch-compatibility/ Transene's Chemical Compatibility Chart] provides a useful quick-reference for which Transene etchants attack which materials.
##As a side-note, [http://transene.com/ Transene] provides many pre-mixed solutions that you can order, saving you the time and uncertainty of measuring/mixing such chemicals yourself. Make sure you check with us before ordering so we know how to handle the chemical before it arrives.

===Compound Semiconductor Etching===
[http://www.sciencedirect.com/science/article/pii/S0927796X00000279 Guide to references on III±V semiconductor chemical etching (A.R. Clawson, 2001)]

* Impressively vast list of various III-V wet etches, organized by various applications (eg. "selective GaAs against AlGaAs" or "non-selective InP/InGaAsP" etc.)
* Please add any confirmed etches from this reference to the {{HLink|Wet Etching Recipes|The Master Table of Wet Etching (Include All Materials)}}.

===Metal Etching===

*[//wiki.nanotech.ucsb.edu/w/images/c/c3/Ta_and_Cr_E-beam_deposition_and_wet_etch_test.pdf Selective Wet Etch of Cr over Ta using Cr Etchant]
*[//wiki.nanotech.ucsb.edu/w/images/d/dc/ITO_Deposition-250C-Ebeam2-HCl-Wet-Etch.pdf Wet Etch of ITO using Heated, Diluted HCl Solution]

===Silicon etching===
[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=546406 Etch rates for micromachining processing]

[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1257354 Etch rates for micromachining processing-part II]

Please add any confirmed etches from this reference to the {{HLink|Wet Etching Recipes|The Master Table of Wet Etching (Include All Materials)}}.

==Organic removal==

===Piranha Solution===

*'''Careful!''' Read about how to prepare and handle this safely:
**[http://web.mit.edu/cortiz/www/PiranhaSafety.doc MIT's Piranha Solution safety document]
**[https://www.ehs.harvard.edu/sites/default/files/lab_safety_guideline_piranha_etch.pdf Harvard EHS's Handling Document]
**Used for etching away Photoresist residues after dry etching.

===PureStrip (Transene)===

*Heat to @ 70°C
**[[Wet Benches#Wafer Toxic Corrosive Benches|Vertical heated bath on Wafer Toxic-Corrosive bench in Bay 4]]
**After a few days heated, it loses potency - must drain + replenish with fresh solution.
**~30-90min will remove stubborn, microscopic PR residues from dry etching.

==[[Gold Plating Bench|Gold Plating Bench (Technic SEMCON 1000)]]==
Standard plating recipes are described and taught during the equipment training for this tool.

Electroplating first requires a Gold seed layer to be present on all surfaces to be plated. Common ways to produce this are to:

*[[Tool List#Sputter Deposition|Sputter-coat]] a thin (~100nm) Au "seed layer" on all surfaces of the wafer, being careful to consider shadowing effects during the dep (eg. in high-aspect ratio trenches).
*Perform photolithography to protect (and prevent plating) in desired areas - areas with no photoresist will be plated.
**Leave ''Open'' the 4 contact points on the edge of the wafer, or some other contact point, for an electrode to make contact to the Seed layer.
**Optionally use EBR100 to swab away photoresist from the contact points.
*Perform the electroplating on the [[Gold Plating Bench|Technic SemCon]], contacting the seed layer with electrodes and executing the program for the desired current/time to achieve the plating thickness (typically microns).
*Strip the photoresist using standard solvents.
*Use the [[CAIBE (Oxford Ion Mill)|Oxford Ion Mill]] to blanket etch the seed layer all over the wafer (the 100nm removed from the plated regions will be negligible compared to the ~1µm plated).

==[[Chemical-Mechanical Polisher (Logitech)|Chemi-Mechanical Polishing (CMP)]]==
''To Be Added''

==[[Mechanical Polisher (Allied)|Mechanical Polishing (Allied)]]==
''To Be Added''
[[Category:Processing]]

E-Beam Lithography System (Raith EBPG 5150+)

2026-04-16T18:07:52Z

John d: added info from tool quote

{{tool|{{PAGENAME}}
|picture=RaithEBPG_2026-03.png
|type = Lithography
|super= Bill Mitchell
|location=Bay 7
|description = Vector Scan Electron Beam Lithography System
|manufacturer = [https://raith.com Raith GmbH]
|model = EBPG 5150+
|materials =
|toolid=87
}}
{{ToolActions
|toolid = 87
|ProcessControlURL =
|ProceduresURL =
|TrainingURL =
}}

__TOC__

== About ==
'''Raith EBPG5150 Plus - Ultra High-Performance e-Beam Writer'''

The Raith EBPG Electron-Beam Lithography (EBL) tool is a high-speed, high current lithography tool for achieving lower than 10nm features, but also capable of very fast writing with the 350nA max current and higher speed 125MHz pattern generator & increased write-field size. The tool has fully automated/programmable aperture switching and beam calibrations. This enables the Raith EBL to write full-wafers at high speed for larger features (high current) and automatically switch+calibrate to exposure small (<<50nm) features in a single exposure, with sophisticated mix+match capabilities and pattern generation for maximum throughput while achieving the best high-resolution performance.

== Detailed Specifications ==
* Minimum feature size: 8nm
** 0.6nm stage movement resolution
* Layer-to-Layer Alignment/Overlay Accuracy: ≤5nm
* Maximum wafer/substrate size:
** Diameter: 150mm wafer (155mm x 155mm stage traverse)
** Thickness: 3mm
** (smaller piece-parts are common)
* 10-holder load-lock
** 2x Cassette loader/substrate holders available,
** Programmable/automated loading/switchout available via software.
* Beam Voltage: 50vK + 100kV
* Beam Current: 50pA – 350nA
** Automatic aperture changer
* Scanner Speed (or other speed specs): 125MHz
* Exposure Field Size: Continuously variable from < 0.1 mm to 1.048 mm field size
** Single-nanometer stepping within the field
** Available at all beam currents and voltages
* Stand-alone optical alignment station (for pre-alignment of wafer to holder)
* Other capabilities:
** Automatic, dynamic off-axis focus, stigmation and field distortion corrections
** Integrated Laser height sensor for field-by-field or pre-mapping mode with direct electron feedback to deflection and focus corrections.

*Advanced write software available (Layout BEAMER from GeniSys, Inc)
** Automated proximity correction of patterns possible
** Ability to manually position write fields within a pattern for optimum inter-field writing performance
** Ability to adjust beam scanning strategy within a write field for optimum intra-field writing performance
** Fine tuning of line-edge roughness by shot pitch correction & non-Manhattan scanning for curved edges

== [[Direct-Write Lithography Recipes#E-Beam Lithography Recipes (Raith EBPG 5150+)|Recipes]] ==
All recipes can be found on the following page:

* ''Recipes > Litho. > Direct-Write > [[Direct-Write Lithography Recipes#E-Beam Lithography Recipes (Raith EBPG 5150+)|'''EBL Recipes''']].''

Calculators + Utilities

2026-04-12T03:59:02Z

John d: /* Refractive Indices/Dispersion Models for Python Scripts */

''This page lists a few online calculators and utilities that are useful to lab users.''

==Fabrication Processes & Converters==

*[https://trello.com/b/Oxs8nMlt/example-fabrication-jobs-board Example Fab Job tracking on Trello]
**Includes Example Travelers/Process Followers ([https://en.wikipedia.org/wiki/Manufacturing_execution_system MEC], process documentation+tracking)
**Includes Example [https://en.wikipedia.org/wiki/Design_of_experiments DOE] spreadsheets - how to organize a process development experiment according to the scientific method.

*[https://cleanroom.byu.edu/oxidetimecalc/ Thermal Oxide Calculator (BYU)]
*[http://www.lelandstanfordjunior.com/thermaloxide.html Thermal Oxide Calculator (Leland Stanford Jr.)]
**''This Thermal Ox calculator allows you to tweak the calculation using the Partial Pressure variable, to match your experimental data.''
*[http://www.calculatoredge.com/optical%20engg/pressure%20converter%20calc.htm Conversion of Pressure Units (calculatoredge.com)]
*[https://www.pfeiffer-vacuum.com/en/know-how/introduction-to-vacuum-technology/fundamentals/mean-free-path/ Mean Free Path tables (Pfeiffer Vacuum)]
*[http://www.lelandstanfordjunior.com LelandStanfordJunior.com]: Film Stress, Ion Implant, Thermal Oxidation, KOH Etching & online curve-fitting

==Material Parameters==

*[https://www.webelements.com/compounds.html WebElements: Compounds]
**''Boiling points of various compounds can tell you how volatile an etch product may be in a reactive ion etch, or whether they need to be wet-etched instead.''
*[http://www.ioffe.ru/SVA/NSM/Semicond/index.html Physical Properties of Semiconductors (Ioffe Institute)]
*[https://www.lesker.com/newweb/deposition_materials/materialdepositionchart.cfm?pgid=0 Kurt J Lesker: Material Deposition Chart]
**''Useful info about evaporating and sputtering many materials''
*[https://www.lesker.com/newweb/ped/rateuniformity.cfm Kurt J. Lesker: Sputter Rates]
**''Sputter rates of various materials, indicative or hardness and dry etching properties.''

==Wet Etching==

*[http://transene.com/etch-compatibility/ Transene Inc. Chemical Compatibility Chart]
**''This table shows common metals and which Transene etchants they are attacked by/impervious to.''
*[http://www.sciencedirect.com/science/article/pii/S0927796X00000279 A.R. Clawson, "Guide to references on III±V semiconductor chemical etching", 2001]
**''Enormous review of published wet etches of many semiconductors and alloys. The only thing it's missing is a hyperlinked table of contents.''

==Refractive Indices==
''Optical constants of many common materials. Useful for Optical thin-film analysis (ellipsometry/spectroscopic fitting), laser etch monitoring, optical filter/mirror/anti-reflection coating design, photonic devices etc.''

*[http://luxpop.com/HU_v172.cgi?OpCode=73 LuxPop.com]
*[https://refractiveindex.info RefractiveIndex.info]
*[https://filmetrics.com/refractive-index-database Filmetrics Inc.]
*[http://www.ioffe.ru/SVA/NSM/nk/index.html Ioffe Institute]

==== Refractive Indices/Dispersion Models for Python Scripts ====

* [https://github.com/demisjohn/nk.py '''nk.py (GitHub)'''] - Python functions for returning '''''n''''' (refractive index) & '''''k''''' (extinction coefficient) of various NanoFab thin-films at a specified wavelength (aka. optical dispersion models).

==Scripts + Programs==

===Analysis Programs===

*[https://www.amscope.com/software-download AmScope Software] - microscope image analysis software
**AmScope Calibration File containing calibrations for all NanoFab microscopes: [https://wiki.nanotech.ucsb.edu/wiki/Images/uploads/2020/AmScopeCalsAll.magn Download Here]
**Also available on '''''Nanofiles-SFTP / Manuals / Amscope'''''
*[https://fiji.sc FIJI] - scientific image anaylsis software
**[[FIJI - Microscope Measurement Tools|The Microscope Measurement Tools plugin]] has pre-configured calibrations for NanoFab microscopes & SEMs, and allows you to draw length measurements.
***''Calibrations in this plugin repository are out of date as of microscope upgrades in 2019''.
**There are many [https://imagej.net/Category:Plugins other useful plugins], for particle counting, [https://stackoverflow.com/questions/6230353/how-to-create-gif-animation-from-a-stack-of-jpgs/37193012#37193012 creating animations] etc.
*[http://gwyddion.net Gwyddion] - free analysis software for Atomic Force Microscopes (AFMs) and other 3D data.
**Sophisticated leveling, slicing, roughness/particulate analysis functions etc.
**Can open Bruker NanoScope files, from the [[Atomic_Force_Microscope_(Dimension_3100/Nanoscope_IVA)|AFM]]
*[https://www.profilmonline.com ProfilmOnline.com (Filmetrics)] - online analysis/storage/sharing of 3D topographical data and images.
**You can share an interactive 3D render of your [[Atomic Force Microscope (Bruker ICON)|AFM]] or [[Optical Profilometer - White-Light/Phase-Shift Interference (Filmetrics Profilm3D)|Profilm3D]] scans with this tool.
**[https://www.profilmonline.com/s/cjezAEur8mC2 Example AFM Scan], taken with NanoFab equipment, shared online for interactive analysis (slice, flatten etc.).

== CAD Layout and Mask Design ==

===CAD Layout Programs===
''Use these for designing your lithography mask plates.''

====L-Edit====
Powerful multi-layer layout program. Sophisticated object instantiation and array layout, to reduce files sizes and easily push changes to multiple cells.

*UCSB's ECE dept. provides an '''academic''' license for this software (no industrial users!), email [mailto:help@ece.ucsb.edu help@ece.ucsb.edu] to obtain the software.
*Windows only.
*See [https://wiki.nanotech.ucsb.edu/wiki/Images/uploads/2018/LEdit_GettingStarted_CherryGupta.pdf this '''L-Edit Tutorial'''] for a good starter guide. Written by [https://scholar.google.com/citations?user=qKzZc7AAAAAJ&hl=en Cherry Gupta], courtesy of [https://me.ucsb.edu/people/sumita-pennathur Prof. Sumita Pennathur].

====[https://www.klayout.de KLayout]====
A free, open-source, and fast/simple CAD tool for mask/reticle layout. Also has powerful functions, DRC, scriptiable and can handle very large files (GB's) efficiently.

Download at [https://www.klayout.de/ klayout.de].

*Available on Windows, Mac or *Nix.
*Fast viewing of layer overlay, overlay multiple files, cell hierarchy, large (>1GB) files etc.
*Supports the same core functionality as L-Edit - hierarchical Cell Instances, arrays, programmable Cells (PCells) etc.
*Scriptable with Python or Ruby, with decent tutorials.
*[[KLayout Design Tips|'''KLayout Design Tips''']]: important info on making "valid" CAD files, and setting up the program for efficient use.
*Univ. of Waterloo QNFCF has produced some good [https://www.youtube.com/@qnfcf6093/videos '''''video tutorials on KLayout, here'''''].

==== [https://layouteditor.com/ LayoutEditor] ====

* Free editor for GDS, OASIS, DXF etc. available on Windows, MacOS, Linux.
* Scriptable with Python, Ruby, C++

====AutoCAD====
Many photomask vendors can accept AutoCAD DWG files, but these can only be opened in AutoCAD (not KLayout or other layout programs). Although AutoCAD can produce a cross-compatible DXF file, we see many design/conversion issues with these files. This is because many shapes and line-types (Curves and Line/polyline/LWLine for example) used in AutoCAD don't convert as expected into the polygons needed for printing. Also the DXF file format itself often creates problems, such as incorrect scaling (undefined units: mm or µm?) or badly-filled/unclosed polygons.

===CAD Design Tips===

=====''Cells and Instancing''=====
All major chip layout programs support "Cells" and similar structures for hierarchical layout. It is highly recommended that you understand and use the concept of "Cells" in your design. This circumvents many problems with enormous file sizes (due to huge numbers of identical polygons), and if used properly, helps tremendously with programming the Stepper lithography machines. Links to documentation below:

*Create a new cell, and instancing that cell: [https://www.klayout.de/doc/manual/create_instance.html KLayout Docs : Creating a Cell instance]
*Viewing only some levels of the heirachy, to prevent drawing all objects: [https://www.klayout.de/doc/manual/hier.html KLayout Docs: Viewing Cell Heirarchy]

=====''File Types''=====
OASIS files tend to be much smaller than GDS files, and they also save the Layer Names (not just number). Alternatively, in KLayout the function '''File > Save Session''' will save the entire view including layer styles and window/zoom locations will be saved. You can share this file, as the entire design file is embedded within it, but it may not be as robust between KLayout versions.

DXF Files can often cause problems because the format varies widely depending on the program they are exported from. For example, DXF can lose the "scaling" causing polygons to be 1000x larger than expected, or unexpectedly cause some shares to get filled in.

=====[[KLayout Design Tips|''KLayout Design Tips'']]=====
See the above page for important info on making "valid" CAD files, and setting up KLayout for efficient use.

=====''Handling very large files''=====
If you will be generating millions of identical shapes (eg. repeating array of circles), the file size can quickly become enormous due to all the stored polygon points. You can reduce the number of polygon points stored by:

#Reduce the number of points in each shape/circle if possible.
#Use Cell instancing so that only one, or a few, polygons are defined, and that same polygon is then only referenced as a repeating Cell instance. (See above for tutorials).
#The OAS file type generates much smaller files, and most photomask vendors can accept this. Photomask vendors are used to handling large files.
#Photomask vendors are able to take multiple files and insert them into the final reticle – you just need to provide a clear schematic showing the exact insertion coordinates for each file (with respect to the origin of each file). They can also do some boolean operations (for a fee).

===Example CAD File===
Here is an example CAD file, showing the use of Layers and Cells, designed in KLayout. The device is fictional, for illustrative purposes only.

*[//wiki.nanotech.ucsb.edu/w/images/a/ae/CAD_Tutorial_for_ASML_Reticle_v1.OAS CAD_Tutorial_for_Reticle_v1.OAS] , or [[Media:CAD Tutorial for ASML Reticle v1 GDS.gds|GDS version]] (''Demis D. John'')
*Cell "'''Device_Layout'''" shows a single device, with each ''Layer'' overlaid as it would be in a fabricated device. Each Layer (eg. a "process step" such as Mesa etch, Pad Metal etc.) is placed into it's own Cell.

:[[File:CAD Tutorial for ASML Reticle v1 - screenshot Device Layout cell.png|alt=screenshot of KLayout view of Device_Layout|none|thumb|530px|"Device_Layout" Cell showing as the "top cell"]]

*Every Cell's ''Origin'' (0,0) lies on top of one another in the final ''Device_Layout''.
**One way this can be accomplished is by selecting the objects/polygons you want to make into a new Cell, then use the function '''Edit >''' '''Selection > Make Cell''', and ''uncheck'' the "''Put Origin at...''" checkbox, so the new Cell maintains the same origin as the original view.
*The Cell "'''Reticle_Layout'''" can be exported by itself (right-click the Cell name), for sending to the photomask manufacturer.
**[//wiki.nanotech.ucsb.edu/w/images/3/34/DEMISJAN2020_-_Reticle_Layout_v1.GDS Here is an example GDS file (download)] for submission to the photomask manufacturer, with all objects moved to a single Layer.
*See the [[Stepper Mask-Making Guidelines (Generic)|Stepper Mask Making Guidelines page]] for an example of how to program this Reticle into an ASML Stepper job.

==== Advanced Stepper Mask Layout ====
*[[Media:CAD Tutorial for ASML Reticle v2 DEMIS-DOE.OAS|CAD_Tutorial_for_ASML_Reticle_v2_DEMIS-DOE.OAS]] - example CAD file for reticle with many design variations.
**Cell "'''''Reticle_Layout'''''" shows the mask that would be printed by a photomask vendor. You would print '''Layers 1,2 and 3''' onto a single mask plate, with the CAD file origin at the center of the mask plate (no automatic centering).
**Cell "'''''Wafer_Layout'''''" shows an estimation/"simulation" of design variations to be exposed on the wafer. It is only a "simulation" because the real layout would be programmed on the Stepper tool itself, which may make changes (such as automatically filling to the wafer's edge).
*[[Media:ASML Reticle Programming Params - DEMIS-DOE v1.xlsx|ASML_Reticle_Programming_Params_-_DEMIS-DOE_v1.xlsx]] - stepper programming sheet for the above CAD file, for typing in the mask's '''''Images''''' into the Stepper software.

===CAD Files & Templates===

====General CAD files for Lithography====

*[[Media:Vented font DDJ.gds|Vented Font (GDS)]] - a font good for liftoff (no enclosed holes). (Designed by [[Demis D. John]])
**See [https://www.klayout.de/forum/discussion/comment/6919/#Comment_6919 this comment] for instructions on installing the font into KLayout.[[File:Vented font screnshot.jpg|alt=Screenshot of Vented_font_DDJ.gds|none|thumb|200x200px|Vented font schematic.]]
*[[Media:Vernier Template.gds|Alignment/Registration Vernier Scales (GDS)]] - used to measure the misalignment between different layers (step=0.1um). (Designed by [[Demis D. John]])
**[http://www-inst.eecs.berkeley.edu/~ee143/fa10/lab/vernier.pdf How to use a Vernier Scale (UC Berkeley)][[File:Vernier Template v2 screenshot.jpg|alt=screenshot of vernier_template.gds CAD file|none|thumb|200x200px|Vernier Template schematic.]]
*[[Resolution Test structures]] - '''''To Be Added'''''

==== Contact Aligners ====
*Alignment Marks for Contact Aligners:
*#[https://www.cnfusers.cornell.edu/contact_litho_alignment_keys#:~:text=Standard%20Contact%20Alignment%20Mark CNF Contact Marks] - designed by the Cornell Nanoscale Science & Technology Facility staff.
*#*"''Polygons are Clear''" polarity, so 2nd layer has transparent region around alignment mark.
*#Male/female alignment marks with vernier (step=0.5um): [[Media:Contact-AlignMarks Vernier DemisDJohn v5.oas|OASIS]] / [[Media:Contact-AlignMarks Vernier DemisDJohn v5.gds|GDS]] format (Designed by [[Demis D. John]])
*#*Contains 3 separate Cells, as illustrated in the image below.
*#*2nd layer has cells with both polarities (positive and negative, with window for viewing during alignment)

:::[[File:Contact-AlignMarks Vernier DemisDJohn v5 screenshot overlay.png|alt=screenshot of overlaid alignment marks|none|thumb|308x308px|Overlay of Lyr1 + Lyr2 ([[Demis D. John]])]][[File:Contact-AlignMarks Vernier DemisDJohn v3 Screenshot.png.png|alt=screenshot of Contact-AlignMarks_Vernier_DemisDJohn_v5.oas|none|thumb|Alignment Mark with Vernier, each version in it's own Cell. ([[Demis D. John]])|672x672px]]

====GCA Stepper====

* [[Stepper Mask-Making Guidelines (Generic)]]

*[[:File:GCA Stepper MaskPlate Master-DarkField 5x.gds|GCA Photomask Template]]: Dark-field (polygons/objects are clear) at 5x Magnification (GDS)
**''This template is designed to be submitted to the photomask vendor to print as-is, no scaling applied.''
**''Insert your designs into the template as Instances scaled UP by 5x.''
**''During exposure, set the blades to 90/90 to block out AutoStep200 DFAS openings''
*[[Media:GCA Global Mark.gds|GCA Global Alignment Mark CAD File (GDS)]]
*[[:File:GCA Local Alignment Mark.gds|GCA Local Alignment Mark (GDS)]]
*[[:File:GCA Local Alignment Mark Dotted.gds|GCA Local Alignment Mark Dotted (GDS)]] - helps for low-contrast topography

====ASML Stepper====

* [[Stepper Mask-Making Guidelines (Generic)]]
* [https://docs.google.com/document/d/1b9YT11RPsl-UlLvN74hrQvG01OcYDL16r6I5lPOlBEo/edit?usp=sharing ASML-specific Mask Making Guidelines] - ''Access is restricted to trained users only.''
*[[Calculators + Utilities#Example%20CAD%20File|Example Reticle/Mask CAD File]], designed in [[Calculators + Utilities#KLayout|KLayout]].
*"DEMIS_DOE" - [https://wiki.nanofab.ucsb.edu/w/images/2/23/CAD_Tutorial_for_ASML_Reticle_v2_DEMIS-DOE.OAS Example Reticle CAD File] for many design variations, and accompanying [https://wiki.nanofab.ucsb.edu/w/images/5/56/ASML_Reticle_Programming_Params_-_DEMIS-DOE_v1.xlsx stepper-programming worksheet].

====Heidelberg MLA150====

*[[MLA150 - CAD Files and Templates]]

====Other sources of lithography CAD files====

*[https://www.mems-exchange.org/users/litho-templates/ MEMS Exchange] - has some useful alignment markers, registration/alignment verniers etc.
*[https://www.epfl.ch/research/facilities/cmi/process/photolithography/layout-design/ EPFL CMi] - CMi layout template has some useful guidelines and resolution test structures.

==General Calculators==

*[https://www.anaconda.com/download/ Anaconda Python]
**A free Matlab-like IDE and GUI, using the Python language. The '''''Spyder''''' interface is modeled after Matlab.
**Includes the scientific Python libraries needed for array math (numpy), plotting (matplotlib), data science (pandas) and many others. Many open-source packages are available to extend capabilities. The [https://pyvisa.readthedocs.io/en/stable/ PyVisa] module adds equipment control capabilities for automated measurements.

*[https://www.online-utility.org/math/math_calculator.jsp Octave Online Interpreter (online-utility.org)]
**A Matlab-like command-line interface, powered by Python Octave.

*[http://www.wolframalpha.com Wolfram Alpha]
**A versatile online interpreter/calculator, allowing calculations such as "Volume of 1.5g of Silicon", "melting point of SiO2" or "520°C in Fahrenheit".

==Python Scripts==
''These scripts are best run in the [https://pythonhosted.org/spyder/installation.html Spyder IDE], which is easily installed via [https://www.anaconda.com/download/ Anaconda], [http://python-xy.github.io Python(X,Y)].''

'''If you use/modify these scripts in a publication, please consider citing the author(s).''' See our [[Frequently Asked Questions#Authorship on Publications|publication policy]] for more info.

====[https://github.com/demisjohn/Keithley-I-V-Sweep Keithley I-V Sweep]====

*Sweep voltage and plot current vs. voltage using a Keithley SMU.
*Already installed at the Probe Station in Bay 4, and on the QFI Thermal Microscope (Use '''''Spyder (Anaconda Python)''''' to run).
*Requires the [https://pyvisa.readthedocs.io/en/stable/ pyvisa] python module.

====[https://github.com/demisjohn/QFI-Scope-Thermal-Analysis QFIScope Thermal Analysis (Demis D. John)]====

*Import 2D temperature data from the [[IR Thermal Microscope (QFI)]] and plot temperature profiles at user-specified locations.
*Already installed on the QFI Infrared Microscope.

====[[Laser Etch Monitor Simulation in Python|Laser Etch Monitor Simulation in Python (Demis D. John)]]====

*Simulate your laser endpoint signal as you dry-etch through a stack of thin-film layers, using an open-source electromagnetics module.

====[https://github.com/demisjohn/nk.py Optical Constants of Nanofab Films - nk.py (Demis D. John)]====

*Python functions for returning '''''n''''' (refractive index) & '''''k''''' (extinction coefficient) of various NanoFab thin-films at a specified wavelength (aka. optical dispersion models)

Calculators + Utilities

2026-04-12T03:58:21Z

John d: /* Refractive Indices */ linked to new nk.py github repo

''This page lists a few online calculators and utilities that are useful to lab users.''

==Fabrication Processes & Converters==

*[https://trello.com/b/Oxs8nMlt/example-fabrication-jobs-board Example Fab Job tracking on Trello]
**Includes Example Travelers/Process Followers ([https://en.wikipedia.org/wiki/Manufacturing_execution_system MEC], process documentation+tracking)
**Includes Example [https://en.wikipedia.org/wiki/Design_of_experiments DOE] spreadsheets - how to organize a process development experiment according to the scientific method.

*[https://cleanroom.byu.edu/oxidetimecalc/ Thermal Oxide Calculator (BYU)]
*[http://www.lelandstanfordjunior.com/thermaloxide.html Thermal Oxide Calculator (Leland Stanford Jr.)]
**''This Thermal Ox calculator allows you to tweak the calculation using the Partial Pressure variable, to match your experimental data.''
*[http://www.calculatoredge.com/optical%20engg/pressure%20converter%20calc.htm Conversion of Pressure Units (calculatoredge.com)]
*[https://www.pfeiffer-vacuum.com/en/know-how/introduction-to-vacuum-technology/fundamentals/mean-free-path/ Mean Free Path tables (Pfeiffer Vacuum)]
*[http://www.lelandstanfordjunior.com LelandStanfordJunior.com]: Film Stress, Ion Implant, Thermal Oxidation, KOH Etching & online curve-fitting

==Material Parameters==

*[https://www.webelements.com/compounds.html WebElements: Compounds]
**''Boiling points of various compounds can tell you how volatile an etch product may be in a reactive ion etch, or whether they need to be wet-etched instead.''
*[http://www.ioffe.ru/SVA/NSM/Semicond/index.html Physical Properties of Semiconductors (Ioffe Institute)]
*[https://www.lesker.com/newweb/deposition_materials/materialdepositionchart.cfm?pgid=0 Kurt J Lesker: Material Deposition Chart]
**''Useful info about evaporating and sputtering many materials''
*[https://www.lesker.com/newweb/ped/rateuniformity.cfm Kurt J. Lesker: Sputter Rates]
**''Sputter rates of various materials, indicative or hardness and dry etching properties.''

==Wet Etching==

*[http://transene.com/etch-compatibility/ Transene Inc. Chemical Compatibility Chart]
**''This table shows common metals and which Transene etchants they are attacked by/impervious to.''
*[http://www.sciencedirect.com/science/article/pii/S0927796X00000279 A.R. Clawson, "Guide to references on III±V semiconductor chemical etching", 2001]
**''Enormous review of published wet etches of many semiconductors and alloys. The only thing it's missing is a hyperlinked table of contents.''

==Refractive Indices==
''Optical constants of many common materials. Useful for Optical thin-film analysis (ellipsometry/spectroscopic fitting), laser etch monitoring, optical filter/mirror/anti-reflection coating design, photonic devices etc.''

*[http://luxpop.com/HU_v172.cgi?OpCode=73 LuxPop.com]
*[https://refractiveindex.info RefractiveIndex.info]
*[https://filmetrics.com/refractive-index-database Filmetrics Inc.]
*[http://www.ioffe.ru/SVA/NSM/nk/index.html Ioffe Institute]

==== Refractive Indices/Dispersion Models for Python Scripts ====

* https://github.com/demisjohn/nk.py - Python functions for returning '''''n''''' (refractive index) & '''''k''''' (extinction coefficient) of various NanoFab thin-films at a specified wavelength (aka. optical dispersion models).

==Scripts + Programs==

===Analysis Programs===

*[https://www.amscope.com/software-download AmScope Software] - microscope image analysis software
**AmScope Calibration File containing calibrations for all NanoFab microscopes: [https://wiki.nanotech.ucsb.edu/wiki/Images/uploads/2020/AmScopeCalsAll.magn Download Here]
**Also available on '''''Nanofiles-SFTP / Manuals / Amscope'''''
*[https://fiji.sc FIJI] - scientific image anaylsis software
**[[FIJI - Microscope Measurement Tools|The Microscope Measurement Tools plugin]] has pre-configured calibrations for NanoFab microscopes & SEMs, and allows you to draw length measurements.
***''Calibrations in this plugin repository are out of date as of microscope upgrades in 2019''.
**There are many [https://imagej.net/Category:Plugins other useful plugins], for particle counting, [https://stackoverflow.com/questions/6230353/how-to-create-gif-animation-from-a-stack-of-jpgs/37193012#37193012 creating animations] etc.
*[http://gwyddion.net Gwyddion] - free analysis software for Atomic Force Microscopes (AFMs) and other 3D data.
**Sophisticated leveling, slicing, roughness/particulate analysis functions etc.
**Can open Bruker NanoScope files, from the [[Atomic_Force_Microscope_(Dimension_3100/Nanoscope_IVA)|AFM]]
*[https://www.profilmonline.com ProfilmOnline.com (Filmetrics)] - online analysis/storage/sharing of 3D topographical data and images.
**You can share an interactive 3D render of your [[Atomic Force Microscope (Bruker ICON)|AFM]] or [[Optical Profilometer - White-Light/Phase-Shift Interference (Filmetrics Profilm3D)|Profilm3D]] scans with this tool.
**[https://www.profilmonline.com/s/cjezAEur8mC2 Example AFM Scan], taken with NanoFab equipment, shared online for interactive analysis (slice, flatten etc.).

== CAD Layout and Mask Design ==

===CAD Layout Programs===
''Use these for designing your lithography mask plates.''

====L-Edit====
Powerful multi-layer layout program. Sophisticated object instantiation and array layout, to reduce files sizes and easily push changes to multiple cells.

*UCSB's ECE dept. provides an '''academic''' license for this software (no industrial users!), email [mailto:help@ece.ucsb.edu help@ece.ucsb.edu] to obtain the software.
*Windows only.
*See [https://wiki.nanotech.ucsb.edu/wiki/Images/uploads/2018/LEdit_GettingStarted_CherryGupta.pdf this '''L-Edit Tutorial'''] for a good starter guide. Written by [https://scholar.google.com/citations?user=qKzZc7AAAAAJ&hl=en Cherry Gupta], courtesy of [https://me.ucsb.edu/people/sumita-pennathur Prof. Sumita Pennathur].

====[https://www.klayout.de KLayout]====
A free, open-source, and fast/simple CAD tool for mask/reticle layout. Also has powerful functions, DRC, scriptiable and can handle very large files (GB's) efficiently.

Download at [https://www.klayout.de/ klayout.de].

*Available on Windows, Mac or *Nix.
*Fast viewing of layer overlay, overlay multiple files, cell hierarchy, large (>1GB) files etc.
*Supports the same core functionality as L-Edit - hierarchical Cell Instances, arrays, programmable Cells (PCells) etc.
*Scriptable with Python or Ruby, with decent tutorials.
*[[KLayout Design Tips|'''KLayout Design Tips''']]: important info on making "valid" CAD files, and setting up the program for efficient use.
*Univ. of Waterloo QNFCF has produced some good [https://www.youtube.com/@qnfcf6093/videos '''''video tutorials on KLayout, here'''''].

==== [https://layouteditor.com/ LayoutEditor] ====

* Free editor for GDS, OASIS, DXF etc. available on Windows, MacOS, Linux.
* Scriptable with Python, Ruby, C++

====AutoCAD====
Many photomask vendors can accept AutoCAD DWG files, but these can only be opened in AutoCAD (not KLayout or other layout programs). Although AutoCAD can produce a cross-compatible DXF file, we see many design/conversion issues with these files. This is because many shapes and line-types (Curves and Line/polyline/LWLine for example) used in AutoCAD don't convert as expected into the polygons needed for printing. Also the DXF file format itself often creates problems, such as incorrect scaling (undefined units: mm or µm?) or badly-filled/unclosed polygons.

===CAD Design Tips===

=====''Cells and Instancing''=====
All major chip layout programs support "Cells" and similar structures for hierarchical layout. It is highly recommended that you understand and use the concept of "Cells" in your design. This circumvents many problems with enormous file sizes (due to huge numbers of identical polygons), and if used properly, helps tremendously with programming the Stepper lithography machines. Links to documentation below:

*Create a new cell, and instancing that cell: [https://www.klayout.de/doc/manual/create_instance.html KLayout Docs : Creating a Cell instance]
*Viewing only some levels of the heirachy, to prevent drawing all objects: [https://www.klayout.de/doc/manual/hier.html KLayout Docs: Viewing Cell Heirarchy]

=====''File Types''=====
OASIS files tend to be much smaller than GDS files, and they also save the Layer Names (not just number). Alternatively, in KLayout the function '''File > Save Session''' will save the entire view including layer styles and window/zoom locations will be saved. You can share this file, as the entire design file is embedded within it, but it may not be as robust between KLayout versions.

DXF Files can often cause problems because the format varies widely depending on the program they are exported from. For example, DXF can lose the "scaling" causing polygons to be 1000x larger than expected, or unexpectedly cause some shares to get filled in.

=====[[KLayout Design Tips|''KLayout Design Tips'']]=====
See the above page for important info on making "valid" CAD files, and setting up KLayout for efficient use.

=====''Handling very large files''=====
If you will be generating millions of identical shapes (eg. repeating array of circles), the file size can quickly become enormous due to all the stored polygon points. You can reduce the number of polygon points stored by:

#Reduce the number of points in each shape/circle if possible.
#Use Cell instancing so that only one, or a few, polygons are defined, and that same polygon is then only referenced as a repeating Cell instance. (See above for tutorials).
#The OAS file type generates much smaller files, and most photomask vendors can accept this. Photomask vendors are used to handling large files.
#Photomask vendors are able to take multiple files and insert them into the final reticle – you just need to provide a clear schematic showing the exact insertion coordinates for each file (with respect to the origin of each file). They can also do some boolean operations (for a fee).

===Example CAD File===
Here is an example CAD file, showing the use of Layers and Cells, designed in KLayout. The device is fictional, for illustrative purposes only.

*[//wiki.nanotech.ucsb.edu/w/images/a/ae/CAD_Tutorial_for_ASML_Reticle_v1.OAS CAD_Tutorial_for_Reticle_v1.OAS] , or [[Media:CAD Tutorial for ASML Reticle v1 GDS.gds|GDS version]] (''Demis D. John'')
*Cell "'''Device_Layout'''" shows a single device, with each ''Layer'' overlaid as it would be in a fabricated device. Each Layer (eg. a "process step" such as Mesa etch, Pad Metal etc.) is placed into it's own Cell.

:[[File:CAD Tutorial for ASML Reticle v1 - screenshot Device Layout cell.png|alt=screenshot of KLayout view of Device_Layout|none|thumb|530px|"Device_Layout" Cell showing as the "top cell"]]

*Every Cell's ''Origin'' (0,0) lies on top of one another in the final ''Device_Layout''.
**One way this can be accomplished is by selecting the objects/polygons you want to make into a new Cell, then use the function '''Edit >''' '''Selection > Make Cell''', and ''uncheck'' the "''Put Origin at...''" checkbox, so the new Cell maintains the same origin as the original view.
*The Cell "'''Reticle_Layout'''" can be exported by itself (right-click the Cell name), for sending to the photomask manufacturer.
**[//wiki.nanotech.ucsb.edu/w/images/3/34/DEMISJAN2020_-_Reticle_Layout_v1.GDS Here is an example GDS file (download)] for submission to the photomask manufacturer, with all objects moved to a single Layer.
*See the [[Stepper Mask-Making Guidelines (Generic)|Stepper Mask Making Guidelines page]] for an example of how to program this Reticle into an ASML Stepper job.

==== Advanced Stepper Mask Layout ====
*[[Media:CAD Tutorial for ASML Reticle v2 DEMIS-DOE.OAS|CAD_Tutorial_for_ASML_Reticle_v2_DEMIS-DOE.OAS]] - example CAD file for reticle with many design variations.
**Cell "'''''Reticle_Layout'''''" shows the mask that would be printed by a photomask vendor. You would print '''Layers 1,2 and 3''' onto a single mask plate, with the CAD file origin at the center of the mask plate (no automatic centering).
**Cell "'''''Wafer_Layout'''''" shows an estimation/"simulation" of design variations to be exposed on the wafer. It is only a "simulation" because the real layout would be programmed on the Stepper tool itself, which may make changes (such as automatically filling to the wafer's edge).
*[[Media:ASML Reticle Programming Params - DEMIS-DOE v1.xlsx|ASML_Reticle_Programming_Params_-_DEMIS-DOE_v1.xlsx]] - stepper programming sheet for the above CAD file, for typing in the mask's '''''Images''''' into the Stepper software.

===CAD Files & Templates===

====General CAD files for Lithography====

*[[Media:Vented font DDJ.gds|Vented Font (GDS)]] - a font good for liftoff (no enclosed holes). (Designed by [[Demis D. John]])
**See [https://www.klayout.de/forum/discussion/comment/6919/#Comment_6919 this comment] for instructions on installing the font into KLayout.[[File:Vented font screnshot.jpg|alt=Screenshot of Vented_font_DDJ.gds|none|thumb|200x200px|Vented font schematic.]]
*[[Media:Vernier Template.gds|Alignment/Registration Vernier Scales (GDS)]] - used to measure the misalignment between different layers (step=0.1um). (Designed by [[Demis D. John]])
**[http://www-inst.eecs.berkeley.edu/~ee143/fa10/lab/vernier.pdf How to use a Vernier Scale (UC Berkeley)][[File:Vernier Template v2 screenshot.jpg|alt=screenshot of vernier_template.gds CAD file|none|thumb|200x200px|Vernier Template schematic.]]
*[[Resolution Test structures]] - '''''To Be Added'''''

==== Contact Aligners ====
*Alignment Marks for Contact Aligners:
*#[https://www.cnfusers.cornell.edu/contact_litho_alignment_keys#:~:text=Standard%20Contact%20Alignment%20Mark CNF Contact Marks] - designed by the Cornell Nanoscale Science & Technology Facility staff.
*#*"''Polygons are Clear''" polarity, so 2nd layer has transparent region around alignment mark.
*#Male/female alignment marks with vernier (step=0.5um): [[Media:Contact-AlignMarks Vernier DemisDJohn v5.oas|OASIS]] / [[Media:Contact-AlignMarks Vernier DemisDJohn v5.gds|GDS]] format (Designed by [[Demis D. John]])
*#*Contains 3 separate Cells, as illustrated in the image below.
*#*2nd layer has cells with both polarities (positive and negative, with window for viewing during alignment)

:::[[File:Contact-AlignMarks Vernier DemisDJohn v5 screenshot overlay.png|alt=screenshot of overlaid alignment marks|none|thumb|308x308px|Overlay of Lyr1 + Lyr2 ([[Demis D. John]])]][[File:Contact-AlignMarks Vernier DemisDJohn v3 Screenshot.png.png|alt=screenshot of Contact-AlignMarks_Vernier_DemisDJohn_v5.oas|none|thumb|Alignment Mark with Vernier, each version in it's own Cell. ([[Demis D. John]])|672x672px]]

====GCA Stepper====

* [[Stepper Mask-Making Guidelines (Generic)]]

*[[:File:GCA Stepper MaskPlate Master-DarkField 5x.gds|GCA Photomask Template]]: Dark-field (polygons/objects are clear) at 5x Magnification (GDS)
**''This template is designed to be submitted to the photomask vendor to print as-is, no scaling applied.''
**''Insert your designs into the template as Instances scaled UP by 5x.''
**''During exposure, set the blades to 90/90 to block out AutoStep200 DFAS openings''
*[[Media:GCA Global Mark.gds|GCA Global Alignment Mark CAD File (GDS)]]
*[[:File:GCA Local Alignment Mark.gds|GCA Local Alignment Mark (GDS)]]
*[[:File:GCA Local Alignment Mark Dotted.gds|GCA Local Alignment Mark Dotted (GDS)]] - helps for low-contrast topography

====ASML Stepper====

* [[Stepper Mask-Making Guidelines (Generic)]]
* [https://docs.google.com/document/d/1b9YT11RPsl-UlLvN74hrQvG01OcYDL16r6I5lPOlBEo/edit?usp=sharing ASML-specific Mask Making Guidelines] - ''Access is restricted to trained users only.''
*[[Calculators + Utilities#Example%20CAD%20File|Example Reticle/Mask CAD File]], designed in [[Calculators + Utilities#KLayout|KLayout]].
*"DEMIS_DOE" - [https://wiki.nanofab.ucsb.edu/w/images/2/23/CAD_Tutorial_for_ASML_Reticle_v2_DEMIS-DOE.OAS Example Reticle CAD File] for many design variations, and accompanying [https://wiki.nanofab.ucsb.edu/w/images/5/56/ASML_Reticle_Programming_Params_-_DEMIS-DOE_v1.xlsx stepper-programming worksheet].

====Heidelberg MLA150====

*[[MLA150 - CAD Files and Templates]]

====Other sources of lithography CAD files====

*[https://www.mems-exchange.org/users/litho-templates/ MEMS Exchange] - has some useful alignment markers, registration/alignment verniers etc.
*[https://www.epfl.ch/research/facilities/cmi/process/photolithography/layout-design/ EPFL CMi] - CMi layout template has some useful guidelines and resolution test structures.

==General Calculators==

*[https://www.anaconda.com/download/ Anaconda Python]
**A free Matlab-like IDE and GUI, using the Python language. The '''''Spyder''''' interface is modeled after Matlab.
**Includes the scientific Python libraries needed for array math (numpy), plotting (matplotlib), data science (pandas) and many others. Many open-source packages are available to extend capabilities. The [https://pyvisa.readthedocs.io/en/stable/ PyVisa] module adds equipment control capabilities for automated measurements.

*[https://www.online-utility.org/math/math_calculator.jsp Octave Online Interpreter (online-utility.org)]
**A Matlab-like command-line interface, powered by Python Octave.

*[http://www.wolframalpha.com Wolfram Alpha]
**A versatile online interpreter/calculator, allowing calculations such as "Volume of 1.5g of Silicon", "melting point of SiO2" or "520°C in Fahrenheit".

==Python Scripts==
''These scripts are best run in the [https://pythonhosted.org/spyder/installation.html Spyder IDE], which is easily installed via [https://www.anaconda.com/download/ Anaconda], [http://python-xy.github.io Python(X,Y)].''

'''If you use/modify these scripts in a publication, please consider citing the author(s).''' See our [[Frequently Asked Questions#Authorship on Publications|publication policy]] for more info.

====[https://github.com/demisjohn/Keithley-I-V-Sweep Keithley I-V Sweep]====

*Sweep voltage and plot current vs. voltage using a Keithley SMU.
*Already installed at the Probe Station in Bay 4, and on the QFI Thermal Microscope (Use '''''Spyder (Anaconda Python)''''' to run).
*Requires the [https://pyvisa.readthedocs.io/en/stable/ pyvisa] python module.

====[https://github.com/demisjohn/QFI-Scope-Thermal-Analysis QFIScope Thermal Analysis (Demis D. John)]====

*Import 2D temperature data from the [[IR Thermal Microscope (QFI)]] and plot temperature profiles at user-specified locations.
*Already installed on the QFI Infrared Microscope.

====[[Laser Etch Monitor Simulation in Python|Laser Etch Monitor Simulation in Python (Demis D. John)]]====

*Simulate your laser endpoint signal as you dry-etch through a stack of thin-film layers, using an open-source electromagnetics module.

====[https://github.com/demisjohn/nk.py Optical Constants of Nanofab Films - nk.py (Demis D. John)]====

*Python functions for returning '''''n''''' (refractive index) & '''''k''''' (extinction coefficient) of various NanoFab thin-films at a specified wavelength (aka. optical dispersion models)

Stepper 3 (ASML DUV)

2026-04-10T07:34:26Z

John d:

{{tool2|{{PAGENAME}}
|picture=ASML.jpg
|type = Lithography
|super= Demis D. John
|super2= Bill Millerski
|location=Bay 7
|description = Deep-UV Stepper Photolithography
|model = PAS 5500/300
|manufacturer = [http://www.asml.com ASML]
|ToolType = Lithography
|recipe = Lithography
|materials =
|toolid=51
}}
{{ToolActions
|toolid = 51
|ProcessControlURL = Stepper_3_(ASML_DUV)#Process_Control_Data
|ProceduresURL =
|TrainingURL = Stepper_3_(ASML_DUV)#Training_Procedure
}}

==About==

===General Capabilities/Overview===
The ASML 5500 stepper is a 248nm (KrF) DUV stepper for imaging dense features down to below 200nm and isolated line structures down to below 150nm (with effort). 300nm+ features are relatively "easy" to resolve. Layer-to-layer overlay accuracy is better than 30nm.

The system is configured for 4” wafers. The system is designed for high throughput, so shooting multiple 4" wafers is extremely fast, typically minutes per wafer, but any size other than 4-inch is difficult to work with (see below for more info). Additionally, exposure jobs are highly programmable, allowing for very flexible exposures of multiple aligned patterns from multiple masks/reticles in a single session, allowing for process optimization of large vs. small features in a single lithography.

The full field useable exposure area is limited to the intersection of a 31mm diameter circle and a rectangle of dimensions 22mm x 27mm. Users have stitched multiple photomasks together with success. See the [[Stepper 3 (ASML DUV)#Mask Design and CAD files|Mask Making Guidelines page]] for more info on exposure field sizes and how to order your mask plates.

==== Stepper Tutorial ====
If you are not familiar with how Stepper Litho is different from our lithography methods, please review this short tutorial:

[https://wiki.nanofab.ucsb.edu/w/images/c/cb/Demis_D_John_-_Stepper_Reticle_Layout_vs_Wafer_Layout.pdf '''Stepper Reticle Layout vs Wafer Layout (Demis D. John)'''] - Explains the following:

* That a Stepper mask layout is very different than other litho systems.
* That a Stepper mask can have ''many'' designs, and flexibly pattern the wafer with combos of designs.
[[Stepper Reticle Layout (Advanced) - Complex Experiments and Variations|'''Stepper Reticle Layout (Advanced) - Complex Experiments and Variations''']]

* If you need many design variations on your wafer, this is an efficient way to utilize stepper reticles.

===Photoresists Available===
''See [https://wiki.nanotech.ucsb.edu/w/index.php?title=Lithography_Recipes#Photolithography_Recipes PhotoLith. Recipes] for full process info & links to PR datasheets.''

*UV210-0.3 - Positive: 300nm nominal thickness
*UV6-0.8 - Positive: 800nm nominal thickness
*UV26-2.5 - Positive: 2.5um nominal thickness
*UVN2300-0.5 - Negative: 500nm nominal thickness

*DUV42P-6/DS-K101 - Bottom Anti-Reflective Coatings “BARC”
*PMGI/LOL1000/LOL2000 - Underlayers

AZ300MIF Developer for all processes

Many of these DUV PR's are also able to be exposed with [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]].

===Part Size Limits===
With staff support, mounted pieces down to 14mm in size can be exposed using a 4” wafer as a carrier. Flatness will typically be worse in this situation, so small <<500nm features will usually have bad uniformity across the mounted part due to focus variations. Edge bead on irregular pieces (eg. quarter-wafers/squares) will significantly reduce yield/uniformity.

Multi-layer Alignment on mounted parts is particularly difficult, requiring either semi-permanent mounting to the carrier (eg. BCB, SU8 etc.) or significant difficulty/effort to re-align the part to the carrier wafer on each lithography (≤100µm re-mounting accuracy needed).

At this time the maximum wafer size is 4” (100mm) wafers with SEMI standard wafer flat (not Notch).

===Service Provider===

*[http://www.asml.com ASML] - ASML performs quarterly periodic maintenance and provides on-demand support.

==Process Information==

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Lithography_Recipes#Photolithography_Recipes '''Process Recipes Page'''] '''> "Stepper 3"''' - ''Established recipes and corresponding linewidths, photoresists etc.''
*Sample size: 100 mm wafers with SEMI std. major flat
**''Piece-parts process is possible but difficult - contact supervisor for info''
*Alignment Accuracy: < 50 nm
*Minimum Feature Size: ≤150 nm isolated lines, ≤200 nm dense patterns
**''To achieve ≤200nm features with high uniformity, we recommend wafers with total thickness variation (TTV) ≤5µm, and designing your CAD with a smaller Image Size for the high-res. feature''.
*Wafer Thickness: Minimum ≈ 200µm, Maximum ≈ 1.1 mm
*Maximum Dose: ~100mJ
**''Non-chemically amplified EBL resists are not permissible due to this limit.''

===Maximum Wafer Bow===
Measured over 90mm on the [[Film Stress (Tencor Flexus)|Tencor Flexus]]

*'''Do not run wafers with bow values higher than the following values''', contact supervisor for advice if needed.
*Silicon wafers (~550µm thick): 100 µm will likely fail.
*Sapphire (less pliable), ≥60µm bow will intermittently fail - DO NOT RUN
**This applies especially for GaN-on-Sapphire, which often have high wafer bow.
*''Near these values, and you may lose the wafer inside the machine due to wafer vacuum error - DO NOT RUN if unsure.''
*''Substrate material and substrate thickness affect this limit - please contact [[Demis D. John|supervisor]] for advice.''
*You can '''stress-compensate''' wafers to reduce the wafer bow, eg. by depositing on the back side of the wafer. If your wafer is concave down, then depositing a ''compressive'' film on the back will reduce its curvature. Coat the backside of the wafer with compressive PECVD SiO2 or [[Sputtering Recipes#Si3N4 deposition .28IBD.29|IBD SiN]], or other compressive films for concave-down bow.

==Operating Procedures==
'''All procedures are access-restricted only to authorized users with a UCSB NetID (''YourNetID''@ucsb.edu), by vendor request.
Please contact [[Demis D. John|supervisor]] for access/training.

=== [https://drive.google.com/drive/folders/1U9-03qU2htQp_5x39LNq-mn5Q3vXXLDf?usp=drive_link ASML Operating Procedures] ===
* Access-restricted google drive folder of PAS 5500/300 operating procedures.

=== [https://docs.google.com/document/d/1T6Bc7A6YjxFyxMR9n35CCsmtJVRQen3m371Vd_Q9dlY/edit?usp=drive_link Troubleshooting & Error Recovery] ===
* common issues and fixes (access-restricted)

=== [[Stepper 3 (ASML DUV)#Calibrating your Lithography Process|Calibrate Your Litho Process]] ===
See this section for the basics on how to do this: [[Stepper 3 (ASML DUV)#Calibrating your Lithography Process|Stepper 3 (ASML DUV) > Recipes > Calibrating your Lithography Process]]

=== [https://docs.google.com/document/d/17jPek8P_SF1qRADS09ApoDgUiB_v0NFJsIVpkL-Kdag/edit#heading=h.fmorc9eu8hfz Stepper #3 Training/Reference Videos] ===
* The above linked videos provide bookmarked quick-reference to various tool procedures & programming.
**''To access, you must log in with your UCSB NetID, formatted like'' MyNetID''@ucsb.edu'' ''- this is a Google login!''
**''Please contact the [[Demis D. John|tool supervisor]] if you need access.''
**[[UCSB NetID Login Troubleshooting|'''''Trouble accessing?''''' ''Please click here for tips.'']]
**'''''You are NOT authorized''' to use this tool until a tool supervisor authorizes you!''

===Training Procedure===
To get access to this tool, please do the following:

#Email the [[Demis D. John|supervisor]] for access to the training materials. Please provide your UCSB NetID.
#Study the [https://docs.google.com/document/d/17jPek8P_SF1qRADS09ApoDgUiB_v0NFJsIVpkL-Kdag/edit#heading=h.fmorc9eu8hfz training videos].
##If you are a technician and will never program jobs, only Part 1 is necessary.
#"Shadow" someone in your group who uses the machine, until you are completely comfortable with (1) wafer cleaning (critical), (2) reticle load/unload and (3) running a pre-made job.
#When you are ready, request a hands-on check-off on SignupMonkey by clicking this button:{{ToolTrainingButton|toolid=51}}

==Design Tools==

===Mask Design and CAD files===

*[https://wiki.nanofab.ucsb.edu/wiki/Stepper_Mask-Making_Guidelines_(Generic) '''Stepper Mask-Making Guidelines'''] - Info needed to design and order a reticle for our Stepper systems. This is minimal unrestricted info that is viewable without additional paperwork.
*'''[https://docs.google.com/document/d/1b9YT11RPsl-UlLvN74hrQvG01OcYDL16r6I5lPOlBEo/edit?usp=sharing ASML-specific Mask Making Guidelines (Private)]''' - More detailed info to design and order a reticle for this specific ASML system.
**''Access is restricted to trained users only by ASML's requirement - please contact [[Demis D. John|tool supervisor]] for access.''
*'''Tutorial: [https://wiki.nanofab.ucsb.edu/w/images/c/cb/Demis_D_John_-_Stepper_Reticle_Layout_vs_Wafer_Layout.pdf Stepper Reticle Layout vs Wafer Layout (Demis D. John)]''' ''-'' explains how Stepper mask layout is very different than other litho systems.
*'''Tutorial: [[Stepper Reticle Layout (Advanced) - Complex Experiments and Variations]]''' - If you need many design variations on your wafer.

*See the [[Calculators + Utilities#CAD%20Files%20.26%20Templates|Calculators + Utilities > '''CAD Files & Templates''']] page for other useful CAD files, such as overlay verniers, vented fonts etc.

===[[ASML Stepper 3 - UCSB Test Reticles|UCSB Photomasks Available]]===

*Click the above link to view our available masks & images
*Photomasks available with various patterns such as
**Alignment Markers (contact, EBL)
**Resolution Testing
**Various line/space (0.150µm → 50µm),
** Alignment markers modifications (dicing lane marks, rotated marks)
** Full-field exposure,
** 1mm boxes for LaserMonitor or Filmetrics/Dektak etc.

=== Optical Proximity Correction (OPC): Going below the resolution limit ===

* [https://drive.google.com/file/d/1Ivjq8_jd_1msA7Ap7ellArTZZ3soSLPe/view?usp=sharing '''OPC General information and detailed investigation of lateral DBR patterns'''] - Detailed info and investigation of OPC, use case examples, performance comparisons, how to order etc. By [[Gopikrishnan G M|Gopikrishana G. Meena]].
* UCSB Nanofab users have access to order photomask plates with [https://en.wikipedia.org/wiki/Optical_proximity_correction OPC] corrections applied to the patterns to enable accurate lithography on high-resolution structures, with a single photomask order.
* Model-based, "feed-forward" OPC - meaning you order only one photomask, no "feed-''back''", nor 2nd mask required.
* [https://www.photronics.com/ Photronics Inc.] - OPC corrected mask plate provider for UCSB Nanofab users.
** Contact [[Demis D. John|Demis]] for quotes.
** Photronics Inc. is collaborating with the Nanofab to develop + provide OPC correction to UCSB researchers.
** Photronics' team has built a model-based OPC correction for our system, which appears to work for multiple photoresists (UV6-positive and UVN-negative tested so far).
** Current OPC rules are for: ''Conventional (circular) Illumination / NA=0.57 / sigma=0.75''
{| class="wikitable"
!OPC Mask Correction
! colspan="2" |Positive Resist: UV6-0.8 - Lateral Waveguide Gratings with/without OPC on same photomask.
Collaboration with photomask vendor [https://www.photronics.com/ Photronics Inc.]
|-
! style="text-align:center;" |[[File:ASML OPC CAD.png|191x191px]]
! style="text-align:center;" |[[File:ASML SEM DBR without OPC.png|162x162px]]
! style="text-align:center;" |[[File:ASML SEM DBR With OPC .png|166x166px]]
|-
|OPC applies serifs to your patterns.
|The ''Best'' exposure without OPC corrections; '''doesn't meet device criteria'''. Would require ordering a 2nd mask to correct.
|With OPC applied to the patterns, the '''device criteria (length and spacing) are met on 1st mask rev''', and process window is possibly wider.
|}
{| class="wikitable"
! colspan="2" |Negative PR: UVN30. ASML DUV with and without same MB-OPC, on the same photomask, applied to a Meta-optic.
Fabricated by [https://scholar.google.com/citations?user=9xqXl7sAAAAJ&hl=en Skyler Palatnik], [https://web.physics.ucsb.edu/~maxmb/ Prof. Max Millar-Blanchaer's group] in collaboration with photomask vendor [https://www.photronics.com/ Photronics Inc.]
|-
| style="text-align:center;" |[[File:ASML_OPC_-_Skyler_Palatnik_060224_PR_vtxHvP_15mJOPC_3.png|alt=SEM image of Meta-optic center|300x300px]]
| style="text-align:center;" |[[File:ASML_OPC_-_Skyler_Palatnik_060224_PR_vtxHvP_23mJ_NO_OPC_1.png|alt=SEM of No-OPC meta-optic center|300x300px]]
|-
|'''''With OPC''' applied to mask pattern. Squares and circles with small gaps+small posts are resolved in one exposure.''
|'''''Without OPC''' (standard photomask process). No combination of focus/dose can achieve desired results - "best" result shown here.''
|}

=== [[ASML Stepper 3 - Job Creator|JobCreator]]: Python Scripting ===

* Create ASML Job files using python. Click the above [[ASML Stepper 3 - Job Creator|link for more info]].

==Recipes==

* '''[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Recipes > Lithography > Stepper Recipes > Stepper #3]]''' - starting processes for various DUV photoresists, including Dose/Focus values.

=== Calibrating your Lithography Process ===
To calibrate your own Litho processes, you will need to:
* Find a starter litho close to what you need here: [[Stepper Recipes#Stepper 3 .28ASML DUV.29|Recipes > Lithography > Stepper Recipes > Stepper #3]]
* [https://docs.google.com/document/d/1_QIsYtew1uDlbUJCniApLz9_TYG2izwTxNpmoCbSuLI/edit?usp=drive_link Run your own Focus Exposure Matrix with] [https://docs.google.com/document/d/1_QIsYtew1uDlbUJCniApLz9_TYG2izwTxNpmoCbSuLI/edit?usp=drive_link this procedure] (private) - shows how to do an FEM on the ASML software
* [[Lithography Calibration - Analyzing a Focus-Exposure Matrix]] - how to analyze an FEM & choose the best process

==Process Control Data==

*''The Process Group regularly measures the lithography Critical Dimension ("CD") and Wafer-stage Particulate Contamination for this tool, using a sensitive lithography process that will reveal small changes in Dose repeatability and wafer flatness.''
*[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0 '''Data Table for CD Uniformity and Particulate Contamination''']
*[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281 '''Plots of CD Repeatability''']

{|
|[[File:ASML CD Cals - Example Table.jpg|alt=ASML CD Calibration data - Screenshot of Table|none|thumb|300x300px|''Example of Data Table with SEM's of 320nm features. [https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0 Click for full data table.]''|link=https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0]]
|[[File:ASML CD Cals - Example Plot.jpg|alt=ASML CD Calibration Data - Screenshot of SPC Plot|none|thumb|''Example SPC Chart - Measured Critical Dimension "CD" versus Date.'' ''[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281 Click for current charts.]''|link=https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281]]
|}

Stepper 3 (ASML DUV)

2026-04-10T07:33:58Z

John d: added millerski as backup super

{{tool|{{PAGENAME}}
|picture=ASML.jpg
|type = Lithography
|super= Demis D. John
|super2= Bill Millerski
|location=Bay 7
|description = Deep-UV Stepper Photolithography
|model = PAS 5500/300
|manufacturer = [http://www.asml.com ASML]
|ToolType = Lithography
|recipe = Lithography
|materials =
|toolid=51
}}
{{ToolActions
|toolid = 51
|ProcessControlURL = Stepper_3_(ASML_DUV)#Process_Control_Data
|ProceduresURL =
|TrainingURL = Stepper_3_(ASML_DUV)#Training_Procedure
}}

==About==

===General Capabilities/Overview===
The ASML 5500 stepper is a 248nm (KrF) DUV stepper for imaging dense features down to below 200nm and isolated line structures down to below 150nm (with effort). 300nm+ features are relatively "easy" to resolve. Layer-to-layer overlay accuracy is better than 30nm.

The system is configured for 4” wafers. The system is designed for high throughput, so shooting multiple 4" wafers is extremely fast, typically minutes per wafer, but any size other than 4-inch is difficult to work with (see below for more info). Additionally, exposure jobs are highly programmable, allowing for very flexible exposures of multiple aligned patterns from multiple masks/reticles in a single session, allowing for process optimization of large vs. small features in a single lithography.

The full field useable exposure area is limited to the intersection of a 31mm diameter circle and a rectangle of dimensions 22mm x 27mm. Users have stitched multiple photomasks together with success. See the [[Stepper 3 (ASML DUV)#Mask Design and CAD files|Mask Making Guidelines page]] for more info on exposure field sizes and how to order your mask plates.

==== Stepper Tutorial ====
If you are not familiar with how Stepper Litho is different from our lithography methods, please review this short tutorial:

[https://wiki.nanofab.ucsb.edu/w/images/c/cb/Demis_D_John_-_Stepper_Reticle_Layout_vs_Wafer_Layout.pdf '''Stepper Reticle Layout vs Wafer Layout (Demis D. John)'''] - Explains the following:

* That a Stepper mask layout is very different than other litho systems.
* That a Stepper mask can have ''many'' designs, and flexibly pattern the wafer with combos of designs.
[[Stepper Reticle Layout (Advanced) - Complex Experiments and Variations|'''Stepper Reticle Layout (Advanced) - Complex Experiments and Variations''']]

* If you need many design variations on your wafer, this is an efficient way to utilize stepper reticles.

===Photoresists Available===
''See [https://wiki.nanotech.ucsb.edu/w/index.php?title=Lithography_Recipes#Photolithography_Recipes PhotoLith. Recipes] for full process info & links to PR datasheets.''

*UV210-0.3 - Positive: 300nm nominal thickness
*UV6-0.8 - Positive: 800nm nominal thickness
*UV26-2.5 - Positive: 2.5um nominal thickness
*UVN2300-0.5 - Negative: 500nm nominal thickness

*DUV42P-6/DS-K101 - Bottom Anti-Reflective Coatings “BARC”
*PMGI/LOL1000/LOL2000 - Underlayers

AZ300MIF Developer for all processes

Many of these DUV PR's are also able to be exposed with [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]].

===Part Size Limits===
With staff support, mounted pieces down to 14mm in size can be exposed using a 4” wafer as a carrier. Flatness will typically be worse in this situation, so small <<500nm features will usually have bad uniformity across the mounted part due to focus variations. Edge bead on irregular pieces (eg. quarter-wafers/squares) will significantly reduce yield/uniformity.

Multi-layer Alignment on mounted parts is particularly difficult, requiring either semi-permanent mounting to the carrier (eg. BCB, SU8 etc.) or significant difficulty/effort to re-align the part to the carrier wafer on each lithography (≤100µm re-mounting accuracy needed).

At this time the maximum wafer size is 4” (100mm) wafers with SEMI standard wafer flat (not Notch).

===Service Provider===

*[http://www.asml.com ASML] - ASML performs quarterly periodic maintenance and provides on-demand support.

==Process Information==

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Lithography_Recipes#Photolithography_Recipes '''Process Recipes Page'''] '''> "Stepper 3"''' - ''Established recipes and corresponding linewidths, photoresists etc.''
*Sample size: 100 mm wafers with SEMI std. major flat
**''Piece-parts process is possible but difficult - contact supervisor for info''
*Alignment Accuracy: < 50 nm
*Minimum Feature Size: ≤150 nm isolated lines, ≤200 nm dense patterns
**''To achieve ≤200nm features with high uniformity, we recommend wafers with total thickness variation (TTV) ≤5µm, and designing your CAD with a smaller Image Size for the high-res. feature''.
*Wafer Thickness: Minimum ≈ 200µm, Maximum ≈ 1.1 mm
*Maximum Dose: ~100mJ
**''Non-chemically amplified EBL resists are not permissible due to this limit.''

===Maximum Wafer Bow===
Measured over 90mm on the [[Film Stress (Tencor Flexus)|Tencor Flexus]]

*'''Do not run wafers with bow values higher than the following values''', contact supervisor for advice if needed.
*Silicon wafers (~550µm thick): 100 µm will likely fail.
*Sapphire (less pliable), ≥60µm bow will intermittently fail - DO NOT RUN
**This applies especially for GaN-on-Sapphire, which often have high wafer bow.
*''Near these values, and you may lose the wafer inside the machine due to wafer vacuum error - DO NOT RUN if unsure.''
*''Substrate material and substrate thickness affect this limit - please contact [[Demis D. John|supervisor]] for advice.''
*You can '''stress-compensate''' wafers to reduce the wafer bow, eg. by depositing on the back side of the wafer. If your wafer is concave down, then depositing a ''compressive'' film on the back will reduce its curvature. Coat the backside of the wafer with compressive PECVD SiO2 or [[Sputtering Recipes#Si3N4 deposition .28IBD.29|IBD SiN]], or other compressive films for concave-down bow.

==Operating Procedures==
'''All procedures are access-restricted only to authorized users with a UCSB NetID (''YourNetID''@ucsb.edu), by vendor request.
Please contact [[Demis D. John|supervisor]] for access/training.

=== [https://drive.google.com/drive/folders/1U9-03qU2htQp_5x39LNq-mn5Q3vXXLDf?usp=drive_link ASML Operating Procedures] ===
* Access-restricted google drive folder of PAS 5500/300 operating procedures.

=== [https://docs.google.com/document/d/1T6Bc7A6YjxFyxMR9n35CCsmtJVRQen3m371Vd_Q9dlY/edit?usp=drive_link Troubleshooting & Error Recovery] ===
* common issues and fixes (access-restricted)

=== [[Stepper 3 (ASML DUV)#Calibrating your Lithography Process|Calibrate Your Litho Process]] ===
See this section for the basics on how to do this: [[Stepper 3 (ASML DUV)#Calibrating your Lithography Process|Stepper 3 (ASML DUV) > Recipes > Calibrating your Lithography Process]]

=== [https://docs.google.com/document/d/17jPek8P_SF1qRADS09ApoDgUiB_v0NFJsIVpkL-Kdag/edit#heading=h.fmorc9eu8hfz Stepper #3 Training/Reference Videos] ===
* The above linked videos provide bookmarked quick-reference to various tool procedures & programming.
**''To access, you must log in with your UCSB NetID, formatted like'' MyNetID''@ucsb.edu'' ''- this is a Google login!''
**''Please contact the [[Demis D. John|tool supervisor]] if you need access.''
**[[UCSB NetID Login Troubleshooting|'''''Trouble accessing?''''' ''Please click here for tips.'']]
**'''''You are NOT authorized''' to use this tool until a tool supervisor authorizes you!''

===Training Procedure===
To get access to this tool, please do the following:

#Email the [[Demis D. John|supervisor]] for access to the training materials. Please provide your UCSB NetID.
#Study the [https://docs.google.com/document/d/17jPek8P_SF1qRADS09ApoDgUiB_v0NFJsIVpkL-Kdag/edit#heading=h.fmorc9eu8hfz training videos].
##If you are a technician and will never program jobs, only Part 1 is necessary.
#"Shadow" someone in your group who uses the machine, until you are completely comfortable with (1) wafer cleaning (critical), (2) reticle load/unload and (3) running a pre-made job.
#When you are ready, request a hands-on check-off on SignupMonkey by clicking this button:{{ToolTrainingButton|toolid=51}}

==Design Tools==

===Mask Design and CAD files===

*[https://wiki.nanofab.ucsb.edu/wiki/Stepper_Mask-Making_Guidelines_(Generic) '''Stepper Mask-Making Guidelines'''] - Info needed to design and order a reticle for our Stepper systems. This is minimal unrestricted info that is viewable without additional paperwork.
*'''[https://docs.google.com/document/d/1b9YT11RPsl-UlLvN74hrQvG01OcYDL16r6I5lPOlBEo/edit?usp=sharing ASML-specific Mask Making Guidelines (Private)]''' - More detailed info to design and order a reticle for this specific ASML system.
**''Access is restricted to trained users only by ASML's requirement - please contact [[Demis D. John|tool supervisor]] for access.''
*'''Tutorial: [https://wiki.nanofab.ucsb.edu/w/images/c/cb/Demis_D_John_-_Stepper_Reticle_Layout_vs_Wafer_Layout.pdf Stepper Reticle Layout vs Wafer Layout (Demis D. John)]''' ''-'' explains how Stepper mask layout is very different than other litho systems.
*'''Tutorial: [[Stepper Reticle Layout (Advanced) - Complex Experiments and Variations]]''' - If you need many design variations on your wafer.

*See the [[Calculators + Utilities#CAD%20Files%20.26%20Templates|Calculators + Utilities > '''CAD Files & Templates''']] page for other useful CAD files, such as overlay verniers, vented fonts etc.

===[[ASML Stepper 3 - UCSB Test Reticles|UCSB Photomasks Available]]===

*Click the above link to view our available masks & images
*Photomasks available with various patterns such as
**Alignment Markers (contact, EBL)
**Resolution Testing
**Various line/space (0.150µm → 50µm),
** Alignment markers modifications (dicing lane marks, rotated marks)
** Full-field exposure,
** 1mm boxes for LaserMonitor or Filmetrics/Dektak etc.

=== Optical Proximity Correction (OPC): Going below the resolution limit ===

* [https://drive.google.com/file/d/1Ivjq8_jd_1msA7Ap7ellArTZZ3soSLPe/view?usp=sharing '''OPC General information and detailed investigation of lateral DBR patterns'''] - Detailed info and investigation of OPC, use case examples, performance comparisons, how to order etc. By [[Gopikrishnan G M|Gopikrishana G. Meena]].
* UCSB Nanofab users have access to order photomask plates with [https://en.wikipedia.org/wiki/Optical_proximity_correction OPC] corrections applied to the patterns to enable accurate lithography on high-resolution structures, with a single photomask order.
* Model-based, "feed-forward" OPC - meaning you order only one photomask, no "feed-''back''", nor 2nd mask required.
* [https://www.photronics.com/ Photronics Inc.] - OPC corrected mask plate provider for UCSB Nanofab users.
** Contact [[Demis D. John|Demis]] for quotes.
** Photronics Inc. is collaborating with the Nanofab to develop + provide OPC correction to UCSB researchers.
** Photronics' team has built a model-based OPC correction for our system, which appears to work for multiple photoresists (UV6-positive and UVN-negative tested so far).
** Current OPC rules are for: ''Conventional (circular) Illumination / NA=0.57 / sigma=0.75''
{| class="wikitable"
!OPC Mask Correction
! colspan="2" |Positive Resist: UV6-0.8 - Lateral Waveguide Gratings with/without OPC on same photomask.
Collaboration with photomask vendor [https://www.photronics.com/ Photronics Inc.]
|-
! style="text-align:center;" |[[File:ASML OPC CAD.png|191x191px]]
! style="text-align:center;" |[[File:ASML SEM DBR without OPC.png|162x162px]]
! style="text-align:center;" |[[File:ASML SEM DBR With OPC .png|166x166px]]
|-
|OPC applies serifs to your patterns.
|The ''Best'' exposure without OPC corrections; '''doesn't meet device criteria'''. Would require ordering a 2nd mask to correct.
|With OPC applied to the patterns, the '''device criteria (length and spacing) are met on 1st mask rev''', and process window is possibly wider.
|}
{| class="wikitable"
! colspan="2" |Negative PR: UVN30. ASML DUV with and without same MB-OPC, on the same photomask, applied to a Meta-optic.
Fabricated by [https://scholar.google.com/citations?user=9xqXl7sAAAAJ&hl=en Skyler Palatnik], [https://web.physics.ucsb.edu/~maxmb/ Prof. Max Millar-Blanchaer's group] in collaboration with photomask vendor [https://www.photronics.com/ Photronics Inc.]
|-
| style="text-align:center;" |[[File:ASML_OPC_-_Skyler_Palatnik_060224_PR_vtxHvP_15mJOPC_3.png|alt=SEM image of Meta-optic center|300x300px]]
| style="text-align:center;" |[[File:ASML_OPC_-_Skyler_Palatnik_060224_PR_vtxHvP_23mJ_NO_OPC_1.png|alt=SEM of No-OPC meta-optic center|300x300px]]
|-
|'''''With OPC''' applied to mask pattern. Squares and circles with small gaps+small posts are resolved in one exposure.''
|'''''Without OPC''' (standard photomask process). No combination of focus/dose can achieve desired results - "best" result shown here.''
|}

=== [[ASML Stepper 3 - Job Creator|JobCreator]]: Python Scripting ===

* Create ASML Job files using python. Click the above [[ASML Stepper 3 - Job Creator|link for more info]].

==Recipes==

* '''[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Recipes > Lithography > Stepper Recipes > Stepper #3]]''' - starting processes for various DUV photoresists, including Dose/Focus values.

=== Calibrating your Lithography Process ===
To calibrate your own Litho processes, you will need to:
* Find a starter litho close to what you need here: [[Stepper Recipes#Stepper 3 .28ASML DUV.29|Recipes > Lithography > Stepper Recipes > Stepper #3]]
* [https://docs.google.com/document/d/1_QIsYtew1uDlbUJCniApLz9_TYG2izwTxNpmoCbSuLI/edit?usp=drive_link Run your own Focus Exposure Matrix with] [https://docs.google.com/document/d/1_QIsYtew1uDlbUJCniApLz9_TYG2izwTxNpmoCbSuLI/edit?usp=drive_link this procedure] (private) - shows how to do an FEM on the ASML software
* [[Lithography Calibration - Analyzing a Focus-Exposure Matrix]] - how to analyze an FEM & choose the best process

==Process Control Data==

*''The Process Group regularly measures the lithography Critical Dimension ("CD") and Wafer-stage Particulate Contamination for this tool, using a sensitive lithography process that will reveal small changes in Dose repeatability and wafer flatness.''
*[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0 '''Data Table for CD Uniformity and Particulate Contamination''']
*[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281 '''Plots of CD Repeatability''']

{|
|[[File:ASML CD Cals - Example Table.jpg|alt=ASML CD Calibration data - Screenshot of Table|none|thumb|300x300px|''Example of Data Table with SEM's of 320nm features. [https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0 Click for full data table.]''|link=https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0]]
|[[File:ASML CD Cals - Example Plot.jpg|alt=ASML CD Calibration Data - Screenshot of SPC Plot|none|thumb|''Example SPC Chart - Measured Critical Dimension "CD" versus Date.'' ''[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281 Click for current charts.]''|link=https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281]]
|}

Stocked Chemical List

2026-04-07T23:44:51Z

John d: added crystalbond 509 wax

''You can sort the following table using the ↑ / ↓ buttons in the title row. Your browser's "Find" ⌘-F function also works.''
{| class="wikitable sortable"
!'''CHEMICAL'''
!'''DESCRIPTION'''
!'''VENDOR'''
!Other Names/Notes
|-
|Acetone, 4L, 4 bt = 1 cs
|ACETONE ACS SAFE-COTE 4L Percent Purity ≥99.5%
|FISHER SCIENTIFIC
|ACE
|-
|Propanol, 4L, 4 bt = 1 cs
|2-PROPANOL OPTIM AGRADE Percent Purity ≥99.9%
|FISHER SCIENTIFIC
|ISO, IPA, Isopropanol
|-
|Ethanol
|DEHYDRATED ALCOHOL, 200 PROOF, UNDENATURED, USP GRADE- 4LGLASS
|SPECTRUM CHEMICALS & LAB
|
|-
|Methanol, 4L, 4 bt = 1 cs
|METHANOL OPTIMA GRADE 4L Percent Purity ≥99.9%
|FISHER SCIENTIFIC
|
|-
|Toluene, 4 L
|TOLUENE OPTIMA GRADE 4L Percent Purity ≥99.8%
|FISHER SCIENTIFIC
|
|-
|Ethylene Glycol
|ETHYLENE GLYCOL LABORATORY GRADE
|FISHER SCIENTIFIC
|
|-
|Amyl Acetate, 4L bottle
|AMYL ACETATE LABORATORY GRADE 4L
|FISHER SCIENTIFIC
|
|-
|MIBK, 4L bottle
|Methyl iso-Butyl Ketone (Certified ACS), Grade Certified ACS Reagent
|FISHER SCIENTIFIC
|
|-
|Chloroform, 2.5 L
|Chloroform, 99+%, Acros Organics
|FISHER SCIENTIFIC
|
|-
|Xylenes, 1 liter
|XYLENES ACS 4L Percent Purity ≥98.5%
|FISHER SCIENTIFIC
|
|-
|T1100 BCB rinse solvent
|RINSE T1100 4 LITER GLASS BOTTLE
|MICROCHEM CORP.
|
|-
|Nitric, 500ml.
|NITRIC ACID IND SAFECOTE 2,5L, Assay Percent Range 70%
|FISHER SCIENTIFIC
|
|-
|Sulfuric, 2.5 L
|SULFURIC AC 21/2L IND SAFECOTE Assay Percent Range 95.0 to 98.0 w/w %
|FISHER SCIENTIFIC
|H2SO4
|-
|O-Phosphoric, 2.5 L
|O-PHOSPHORIC ACID Percent Purity ≥85.0% (w/w)
|FISHER SCIENTIFIC
|H3PO4
|-
|Citric acid, liquid, 1.0 M, 1L
|CITRIC ACID, 1.00 Molar
|FISHER SCIENTIFIC
|C6H8O7, solution
|-
|50/50 w/w Citric Acid Monohydrate in Water
|PREMIX CITRIC ACID CAW 1:1
|TRANSENE COMPANY, INC.
|C6H8O7, solution
|-
|Citric acid, granular, monohydrate, 3 kg
|CITRIC ACID GRAN CERT ACS 3KG Percent Purity 99.0 to 102.0%
|FISHER SCIENTIFIC
|C6H8O7, powder
|-
|Acetic, 2.5L
|ACETIC ACID GLACIAL ACS 2.5L IND SAF-CT Assay Percent Range: ≥99.7% w/w
|FISHER SCIENTIFIC
|
|-
|Hydrochloric, 2.5L
|HYDROCHLORIC ACID Percent Purity 36.5 to 38.0% (w/w)
|FISHER SCIENTIFIC
|HCl
|-
|Hydrofluoric, 49%, 500 Ml
|HYDROFLUORIC ACID RGT 500ML Assay (HF) 48 - 51%
|VWR INTERNATIONAL
|HF
|-
|Hydrofluoric, Buffered HF, 1 gal
|BUFFER-HF
|TRANSENE COMPANY, INC.
|BHF, "Buffered oxide etch"
4-8% HF
|-
|Hydrobromic, 500 mL
|HYDROBROMIC ACID 48% CERT ACS 500ML Percent Purity 47.0 to 49.0%
|FISHER SCIENTIFIC
|HBr
|-
|Chrome mask etchant, 1 qt
|CHROMIUM ETCHANT 1020
|TRANSENE COMPANY, INC.
|
|-
|Aluminum etchant, A, 1 qt
|ALUMINUM ETCHANT TYPE A
|TRANSENE COMPANY, INC.
|
|-
|Aluminum etchant, D, 1 qt
|ALUMINUM ETCHANT TYPE D
|TRANSENE COMPANY, INC.
|
|-
|Gold etchant, TFA, 1 qt
|GOLD ETCHANT TFA
|TRANSENE COMPANY, INC.
|
|-
|Nickel etchant, TFB, 1 qt.
|NICKEL ETCH TFB
|TRANSENE COMPANY, INC.
|
|-
|Titanium etchant, TFTN
|TITANIUM ETCHANT TFTN
|TRANSENE COMPANY, INC.
|
|-
|Nanostrip
|KMG-Nanostrip
|INTEGRATED MICRO MATERIALS
|
|-
|Oxalic Acid
|OXALIC ACID CERTIF ACS 500G Percent Purity 99.5 to 102.5%
|FISHER SCIENTIFIC
|
|-
|Formic Acid
|FORMIC ACID 2.5LT 98% (ACS)
|FISHER SCIENTIFIC
|
|-
|Chromic Acid (Chromium Trioxide)
|Chromium Trioxide (Crystalline/Certified ACS) Percent Purity ≥98.0%
|FISHER SCIENTIFIC
|CrO3
|-
|Ammonium hydroxide, 2.5 L
|AMMONIUM HYDROXIDE ACS Assay Percent Range: 28.0 to 30.0 w/w %
|FISHER SCIENTIFIC
|NH4OH
|-
|Ammonium sulfide, 500 mL
|AMMONIUM SULFIDE SOLUTION Assay Percent Range 20 to 24% (aqueous)
|FISHER SCIENTIFIC
|(NH4)2S
|-
|Sodium hydroxide, 1L
|SODIUM HYDROX SOL 50% CERT 1L Percent Purity Inclusive between 50%
|FISHER SCIENTIFIC
|NaOH
|-
|Potassium hydroxide, 43.
|POT HYDROX SOL 45% CERT 4L Concentration or Composition (by Analyte or Components) 45%
|FISHER SCIENTIFIC
|KOH
|-
|Hydrogen peroxide, 500 mL
|HYDROGEN PEROXIDE 30% Percent Purity 30.0 to 32.0%
|FISHER SCIENTIFIC
|H2O2
|-
|Hydrogen peroxide, 1 gal
|HYDROGEN PEROXIDE 30% Percent Purity 30.0 to 32.0%
|FISHER SCIENTIFIC
|H2O2
|-
|TMAH, 25%, per liter
|TETRAMETHYLAMMONIUM HYDROXIDE, 25%
|TRANSENE COMPANY, INC.
|
|-
|Saturated Bromine Water (SBW), 1L
|BROMINE WATER RGT 500ML Percent Purity ≥99.5%
|FISHER SCIENTIFIC
|Br2 : H2O
|-
|AZ400k developer, concentrated, 1 gal
|AZ 400K CONCENTRATE PHOTORESIST DEVELOPER
|INTEGRATED MICRO MATERIALS
|
|-
|AZ400k developer, 1:4 diluted, 1 gal
|AZ 400k 1:4 PHOTORESIST DEVELOPER
|INTEGRATED MICRO MATERIALS
|Pre-diluted
|-
|AZ 726 MIF developer, 1 gal
|AZ 726 MIF DEVELOPER
|INTEGRATED MICRO MATERIALS
|
|-
|AZ NMP Rinse & Photoresist Stripper
|AZ® NMP Rinse & Photoresist Stripper
|INTEGRATED MICRO MATERIALS
|
|-
|AZ 300 T, stripper, 1 gal.
|AZ 300T STRIPPER
|INTEGRATED MICRO MATERIALS
|
|-
|MicroChem 101A Developer, 1 gal
|101A DEVELOPER
|MICROCHEM CORP.
|SAL 101A, XP 101A
|-
|AZ 300 MIF Developer
|AZ 300 MIF DEVELOPER
|INTEGRATED MICRO MATERIALS
|
|-
|SU-8 Developer
|SU-8 DEVELOPER - 4 X 4L
|MICROCHEM CORP.
|
|-
|DS2100 BCB Developer
|DEVELOPER DS2100
|MICROCHEM CORP.
|BCB Developer
|-
|EC 11
|EC SOLVENT 11 - 4 GL CS
|MICROCHEM CORP.
|
|-
|AZ EBR
|AZ EBR EDGE BEAD REMOVER
|INTEGRATED MICRO MATERIALS
|
|-
|KwikStrip, gallon size
|AZ KWIK STRIP PHOTORESIST STRIPPER
|INTEGRATED MICRO MATERIALS
|
|-
|Remover PG, SU-8 stripper
|REMOVER PG - 4 X 4L
|MICROCHEM CORP.
|
|-
|SPR 955 CM-0.9, 1 Gal.
|SPR 955CM-0.9 - 1 GL
|MICROCHEM CORP.
|Photoresist, PR
|-
|SPR 955 CM-1.8, 1 Gal.
|SPR 955CM-1.8 - 1 GL
|MICROCHEM CORP.
|Photoresist, PR
|-
|SPR 220-3.0, 1 gal.
|SPR 220-3.0 P.R. 1GL
|MICROCHEM CORP.
|Photoresist, PR
|-
|SPR 220-7.0, 1 GAL,
|SPR 220-7.0 P.R. 1GL
|MICROCHEM CORP.
|Photoresist, PR
|-
|CEM-365 IS, for stepper, 1 pint.
|CEM365IS-QT
|SHIN-ETSU MICROSI, INC.
|Photoresist, PR contrast enhancer
|-
|OCG 825-35CS
|OCG 825 35CS 1X1 GALLON GLASS
|GALLADE CHEMICAL
|Photoresist, PR
|-
|AZ P4110 1Qt.
|AZ P4110 PHOTORESIST
|INTEGRATED MICRO MATERIALS
|Photoresist, PR
|-
|AZ P4210 1Qt.
|AZ P4210 G-LINE/BROADBAND PHOTORESIST
|INTEGRATED MICRO MATERIALS
|Photoresist, PR
|-
|AZ P4330 RS 1QT.
|AZ P4330-RS
|INTEGRATED MICRO MATERIALS
|Photoresist, PR
|-
|AZ 5214-EIR 1QT.
|AZ 5214-E IR PHOTORESIST
|INTEGRATED MICRO MATERIALS
|Photoresist, PR
|-
|AZ P4620 1QT
|AZP4620-1Q
|INTEGRATED MICRO MATERIALS
|Photoresist, PR
|-
|AZ P9260 1gal.
|AZ® 9260 i-line / Broadband Photoresist
|INTEGRATED MICRO MATERIALS
|Photoresist, PR
|-
|AZnLOF 2020, 1 gal.
|AZ nLoF 2020 NEGATIVE TONE LIFT-OFF PHOTORESIST
|INTEGRATED MICRO MATERIALS
|Photoresist, PR
|-
|AZnLOF 2035, 1 qt.
|AZ Nlof 2035 NEGATIVE TONE LIFT-OFF PHOTORESIST
|INTEGRATED MICRO MATERIALS
|Photoresist, PR
|-
|AZnLOF 2070, 1 qt
|AZ NLOF2070 NEGATIVE TONE LIFT-OFF PHOTORESIST
|INTEGRATED MICRO MATERIALS
|Photoresist, PR
|-
|NR9-1000PY
|Negative Resist NR9-1000PY
|Futurrex, Inc.
|Photoresist, PR
|-
|NR9-3000PY
|Negative Resist NR9-3000PY
|Futurrex, Inc.
|Photoresist, PR
|-
|NR9-6000PY
|Negative Resist NR9-6000PY
|Futurrex, Inc.
|Photoresist, PR
|-
|LOL 2000, 1 qt.
|LOL 2000 -1 QT
|MICROCHEM CORP.
|Photoresist, PR Underlayer
|-
|AZ nLOF P5510 photoresist, 1 gallon
|AZ nLoF 5510 NEGATIVE TONE LIFT-OFF PHOTORESIST.
|INTEGRATED MICRO MATERIALS
|Photoresist, PR
|-
|THMR-IP3600 HP D
|THMR-IP3600 HP
|TOK AMERICA, INC.
|Photoresist, PR
|-
|XHRIC-11 1 LITER
|XHRIC-11 1 LITER
|BREWER SCIENCE, INC.
|Photoresist, PR, BARC
|-
|PMGI, SF 3, 500 ml
|PMGI SF 3 - 500ml Glass
|MICROCHEM CORP.
|Photoresist, PR
|-
|PMGI, SF 5, 500 ml
|PMGI SF 5 - 500ml Glass
|MICROCHEM CORP.
|Photoresist, PR
|-
|PMGI, SF 8, 500 ml
|PMGI SF-8, glass 500ml
|MICROCHEM CORP.
|Photoresist, PR
|-
|PMGI, SF11, 500 ml
|PMGI SF 11 - 500ML GLASS
|MICROCHEM CORP.
|Photoresist, PR
|-
|PMGI, SF15, 500 ml
|PMGI SF 15 - 500ML GLASS
|MICROCHEM CORP.
|Photoresist, PR
|-
|Dow Advanced Electronic, 4024-40, photo BCB
|CYCLOTENE* 4024 - 40 / 0.95 LITERS (BCB)
|MICROCHEM CORP.
|Photo-BCB
|-
|Cyclotene 3022-46
|CYCLOTENE* 3022-46
|MICROCHEM CORP.
|BCB
|-
|AP3000 BCB Adhesion Promoter, gall.
|ADHESION PROMOTER AP3000
|MICROCHEM CORP.
|BCB Adhesion Promoter
|-
|Omnicoat, adhesion promoter for SU-8
|OMNICOAT - 500ML GLASS
|MICROCHEM CORP.
|Resist
|-
|HMDS, (Fineline adhes.), 1 bt.
|MPHP-PT MICROPRIMER HIGH PURITY
|SHIN-ETSU MICROSI, INC.
|Photoresist Adhesion Promoter
|-
|Tergitol
|Spectrum Chemical Manufacturing Corporation TERGITOL NP-10 SURFCTNT 500ML T1273500ML
|FISHER SCIENTIFIC
|Detergent
|-
|SU-8 2005 Photoresist
|SU-8 2005 - 500ml GLASS
|MICROCHEM CORP.
|Photoresist, PR
|-
|SU-8 2010 Photoresist
|SU-8 2010 - 500ml GLASS
|MICROCHEM CORP.
|Photoresist, PR
|-
|SU-8 2015 Photoresist
|SU-8 2015 - 500ml GLASS
|MICROCHEM CORP.
|Photoresist, PR
|-
|SU-8 2075 Photoresist
|SU-8 2075 - 500ml Glass Resist
|MICROCHEM CORP.
|Photoresist, PR
|-
|UV-6 0.8 Photoresist
|UV6-0.8
|MICROCHEM CORP.
|Photoresist, PR
|-
|DUV42P-6
|DUV42P-6
|BREWER SCIENCE, INC
|Photoresist, PR, BARC
|-
|Honeywell 512B spin-on-glass, 125 ml.
|ACCUGLASS 512B SPIN-ON GLASS
|HONEYWELL ANALYTICS INC.
|SOG
|-
|UVN 30-0.8L (UVN 2300-0.5)
|UVN 30-0.8L-1 GL NOWPAK
|MICROCHEM CORP.
|Photoresist, PR
|-
|Brewer Science DS-K101-304, 1 gal bt.
|ARC DS-K101-304, 1 LITER
|BREWER SCIENCE, INC.
|Photoresist, PR, BARC
|-
|UV 210GS-0.3, 1 gal. bt.
|UV 210GS-0.3 - 1 GL NOWPAK
|MICROCHEM CORP.
|Photoresist, PR
|-
|mr-UV Cur 21 100 nm, 100ml.
|MRT-mr-UV Cur 21, 100nm - 100ml Glass
|MICROCHEM CORP.
|Nanoimprint Resist
|-
|Santovac 5P
|Santovac 5P Ultra Polyphenyl Ether Pump Fluid
|KURT J LESKER
|Oil
|-
|SF1 Polishing Fluid
|SF1 Polishing Fluid
|LOGITECH LIMITED
|CMP Slurry
|-
|CrystalBond Wax
|Crystalbond 509 (Clear Color) Mounting Adhesive, Stick (round shape)
|
|Mounting wax, ~135°C melting point, acetone soluble.
|}

ASML Stepper 3 - UCSB Test Reticles

2026-04-03T12:56:58Z

John d: Added Raith AlMk description

== Other Masks and Images ==
We have various patterns on other plates, such as:

* various line/space,
* alignment markers modifications,
* full-field exposure,
* 1mm boxes

See this document for programming info:

[https://docs.google.com/document/d/1sNfphnUfw0k9v7HkZGNpgm5siRxQiU6SCPqIY13mD2w/edit?tab=t.0 '''<big>UCSB Masks and Images for ASML</big>''']

* These are inside the Secure Google Drive folder, you will need to login with your UCSBNetID to access. Ask the [[Demis D. John|Supervisor]] for access.
* Remember your UCSB NetID is a Google Login, formatted as '''''MyNetID'''@ucsb.edu''. If you are trained on the tool, you already have access using this UCSB NetID login.

== Alignment Marks for other systems, other patterns ==

=== Reticle ID: "'''UCSBMARKS26'''" ===
This reticle is always installed in the system, in the "System Reticles" Box #1.

Contains many alignment marks, for as many litho systems in the Nanofab as possible. Also edge-bead removal 1cm field, dicing guides, 1mm "boxes" for Laser Monitoring, verniers etc.

See the GDS File & Programming Params in the [https://drive.google.com/drive/folders/1nZhD1lcizLurOxHx1gKKNvAy05SUGXOo?usp=drive_link UCSB Masks Google Drive] (login via UCSB NetID)
{| class="wikitable"
!Image ID
! colspan="2" |Image Size
(Wafer, mm)
! colspan="2" |Image Shift
(Wafer, mm)
!Notes/Description
!Schematics
|-
!
!X
!Y
!X
!Y
!
!
|-
| colspan="7" |
==== Alignment Markers ====
|-
|Square_30p5
|0.030500
|0.030500
| -4.000000
| -1.000000
|30.5µm square
|
|-
|RaithMark_20um
|0.020000
|0.020000
| -4.000000
| -4.000000
|20µm square
|
|-
|MLA_Align
|0.700000
|0.700000
| -4.000000
|10.500000
|Cross for MLA
|
|-
|GCA_Align
|0.350000
|0.150000
| -4.000000
|9.000000
|Coord is center to GCA mark. Center of DFAS mark is +0.200mm to the right.
|White is Chrome, Pattern is Clear[[File:Stepper align - Screen Shot 2018-07-23 at 11.24.31 AM.png|frameless|213x213px]]
[[Media:GCA stepper align.gds|CAD File (GDS):GCA_stepper_align.gds]]
|-
|Contact_AlignLyr2
|0.300000
|0.300000
| -4.000000
| -5.500000
|
|
|-
| colspan="7" |
==== Open Squares of various sizes ====
|-
|Square_100um
|0.100000
|0.100000
|7.500000
|12.000000
|
|
|-
|Square_200um
|0.200000
|0.200000
|6.000000
|12.000000
|
|
|-
|Square_500um
|0.500000
|0.500000
|4.500000
|12.000000
|Good for Laser Monitor openings
|
|-
|Square_1mm
|1.000000
|1.000000
|2.500000
|12.000000
|Preferred for Laser Monitor openings
|
|-
|Square_2mm
|2.000000
|2.000000
|0.000000
|12.000000
|
|
|-
|Square_5mm
|5.000000
|5.000000
|8.500000
|8.000000
|
|
|-
|Square_10mm
|10.000000
|10.000000
|6.000000
| -5.000000
|Good for Edge-Bead Exposure
|
|}

==== Other available Images ====
More patterns can be found on the OAS file and the Excel Sheet of ASML Programming Parameters

([https://drive.google.com/drive/folders/1nZhD1lcizLurOxHx1gKKNvAy05SUGXOo?usp=drive_link see gDrive folder here] - requires UCSB NetID), such as:

* Same alignment marks as above, but with X/Y Vernier alignment measurements
* Layer-2 Vernier (to match the above verniers)
* Dicing guides in X & Y
* ASML PM Marks rotated by 90°, 180° and 270°
* Calibration patterns used in Nanofab LithoCals and EtchCals, such as
** Hex array of holes at 250nm diam / 250nm gap
** Hex array of holes at 400nm diam / 300nm gap (ASML LithoCals)
** 10µm, 1µm, 0.50µm Line/Space (DSE EtchCals)
* Complementary (Layer-2) Alignment Marks for Contact, Inverted marks

=== Reticle ID: "'''UCSB-OPC1'''" ===
This reticle is always installed in the system, in the "System Reticles" Box #1.

The reticle contains alignment markers for various NanoFab lithography systems, along with resolution test structures and patterns for calibrating [https://en.wikipedia.org/wiki/Optical_proximity_correction optical proximity correction] on the system. Some patterns are proprietary to the mask designer, so we can not share the full GDS CAD file.

==== Alignment Markers ====
{| class="wikitable"
!Image ID
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X , Y

(Wafer, mm)
!Notes/Description
!Schematics
|-
|GCA_Align
|0.530000 , 0.140000
| -6.750000 , 9.450000
|ImageShift references the center of the -X- "global" mark.
The <nowiki>==|||</nowiki> "Local" mark is X+200µm to the right

has 1.1mm margin on all sides
|White is Chrome, Pattern is Clear[[File:Stepper align - Screen Shot 2018-07-23 at 11.24.31 AM.png|frameless|213x213px]]
[[Media:GCA stepper align.gds|CAD File (GDS):GCA_stepper_align.gds]]
|-
|JEOL E-Beam Litho Alignment Mark - Positive
|0.900000 , 0.900000
| -6.750000 , -9.450000
|ImageShift is the center coords of the larger "+" mark
Smaller "+" mark is (0.225,-0.225)mm down-right

0.925mm margin on all sides
|White is Chrome, Pattern is Clear
[[File:GlobalMulti POS - Screen Shot 2018-07-23 at 11.17.23 AM.png|frameless|145x145px]]

[[Media:EBL-GlobalMulti POS.gds|CAD File (GDS): EBL-GlobalMulti_POS.gds]]
|-
|JEOL E-Beam Litho Alignment Mark - Negative
|0.710000 , 0.710000
|6.750000 , -9.450000
|ImageShift is the center coords of the larger "+" mark
Smaller "+" mark is (0.225,-0.225)mm down-right

Blank (masked) space on left+top sides

1.0mm margin on all sides
|Striped area is Clear
[[File:GlobalMulti NEG - Screen Shot 2018-07-23 at 11.22.19 AM.png|frameless|115x115px]]

[[Media:EBL-GlobalMulti NEG.gds|CAD File (GDS): EBL-GlobalMulti_NEG.gds]]
|-
|Contact Mark
|0.564000 , 0.564000
|6.750000 , 9.450000
|ImageShift references the center of the contact alignment mark "+"

with 1.1mm margin on all sides

Note the Polarity - will ''expose'' a ~550µm area.
|White is Chrome, Striped area is Clear
[[File:Align Front - Screen Shot 2018-07-23 at 11.32.16 AM.png|frameless|146x146px]]

[[Media:Contact-AlignFront.gds|CAD File (GDS): Contact-AlignFront.gds]]

[[Media:MA6-FrontBack AlignMarks only.gds|Corresponding male/female alignment marks (GDS): MA6-FrontBack_AlignMarks_only.gds]]
|}

==== Resolution Test Charts ====
The Resolution test charts are repeated all across the reticle, in order to test for lens aberrations. You can have the system expose only a single resolution chart, but since they are placed closely together on the reticle, it's very likely that partial shots of adjacent charts will also be exposed.

In addition, the repeating cells allow us to test for the proper [https://en.wikipedia.org/wiki/Optical_proximity_correction optical proximity correction] (OPC) algorithm. The Five <code>Dense_...</code> patterns are for calibrating the OPC algorithm, and are not for user analysis.

'''''Patterned area is CLEAR/transparent.'''''

===== Calibration Chart Layout =====

Cell name is "''UCSB_Cal''", with coordinates below pointing to center of this cell.[[File:UCSB cal - Screen Shot 2018-07-23 at 12.06.58 PM.png|alt=Layout of the repeating calibration charts|none|thumb|512x512px|Layout of the repeating calibration charts]]

===== Resolution Chart =====
"resolution_chart_ORIG" cell in the above. '''''Blue/patterned area is CLEAR/transparent.'''''
[[File:Resolution Chart - Screen Shot 2018-07-23 at 1.36.31 PM.png|alt=Resolution Chart Layout schematic|none|thumb|400x400px|'''"resolution_chart_ORIG":''' Resolution Chart Layout, with res. test from 2.00µm to 0.130µm]]

The ""resolution_chart_OPC" version has an optical proximity correction algorithm applied:
[[File:Resolution chart OPC - Screen Shot 2018-07-23 at 1.40.48 PM.png|alt=OPC'd Resolution Chart Layout schematic|none|thumb|395x395px|'''"resolution_chart_OPC":''' OPC'd Resolution Chart Layout, with res. test from 2.0µm to 0.130µm]]

===== Coords for "resolution_chart" Calibration patterns =====
''Image coords for each of the "resolution_chart_ORIG" cells. You can pick just one of these for shooting a resolution test structure. The purpose of the many different locations is to check for variations due to lens aberrations. You could just choose one near the center of the plate to test your process, or you could choose a chart that is in a similar location as the pattern you're shooting on your mask plate.''

''Note that some portion of the adjacent patterns will likely be exposed as well, due to the patterns not being surrounded by 1mm of chrome. Make sure you set your Cell Size large enough to make sure the bleed-over doesn't overlap with adjacent die.''
{| class="wikitable"
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X

(Wafer, mm)
!Image Shift
Y

(Wafer, mm)
|-
| colspan="3" |Use this for a single Resolution Chart:
|-
|0.605 , 1.005
|0.685000
|1.350000
|-
| colspan="3" |
|-
| colspan="3" |The following are Res Charts across the exposure field:
|-
|0.605 , 1.005
| -10.115000
|12.150000
|-
|same for each
| -7.415000
|12.150000
|-
|" "
| -4.715000
|12.150000
|-
|" "
| -2.015000
|12.150000
|-
|" "
|0.685000
|12.150000
|-
|" "
|3.385000
|12.150000
|-
|" "
|6.085000
|12.150000
|-
|" "
|8.785000
|12.150000
|-
!
!
!
|-
|
| -10.115000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.715000
|9.450000
|-
|
| -2.015000
|9.450000
|-
|
|0.685000
|9.450000
|-
|
|3.385000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|8.785000
|9.450000
|-
!
!
!
|-
|
| -10.115000
|6.750000
|-
|
| -7.415000
|6.750000
|-
|
| -4.715000
|6.750000
|-
|
| -2.015000
|6.750000
|-
|
|0.685000
|6.750000
|-
|
|3.385000
|6.750000
|-
|
|6.085000
|6.750000
|-
|
|8.785000
|6.750000
|-
!
!
!
|-
|
| -10.115000
|4.050000
|-
|
| -7.415000
|4.050000
|-
|
| -4.715000
|4.050000
|-
|
| -2.015000
|4.050000
|-
|
|0.685000
|4.050000
|-
|
|3.385000
|4.050000
|-
|
|6.085000
|4.050000
|-
|
|8.785000
|4.050000
|-
!
!
!
|-
|
| -10.115000
|1.350000
|-
|
| -7.415000
|1.350000
|-
|
| -4.715000
|1.350000
|-
|
| -2.015000
|1.350000
|-
|
|0.685000
|1.350000
|-
|
|3.385000
|1.350000
|-
|
|6.085000
|1.350000
|-
|
|8.785000
|1.350000
|-
!
!
!
|-
|
| -10.115000
| -1.350000
|-
|
| -7.415000
| -1.350000
|-
|
| -4.715000
| -1.350000
|-
|
| -2.015000
| -1.350000
|-
|
|0.685000
| -1.350000
|-
|
|3.385000
| -1.350000
|-
|
|6.085000
| -1.350000
|-
|
|8.785000
| -1.350000
|-
!
!
!
|-
|
| -10.115000
| -4.050000
|-
|
| -7.415000
| -4.050000
|-
|
| -4.715000
| -4.050000
|-
|
| -2.015000
| -4.050000
|-
|
|0.685000
| -4.050000
|-
|
|3.385000
| -4.050000
|-
|
|6.085000
| -4.050000
|-
|
|8.785000
| -4.050000
|-
!
!
!
|-
|
| -10.115000
| -6.750000
|-
|
| -7.415000
| -6.750000
|-
|
| -4.715000
| -6.750000
|-
|
| -2.015000
| -6.750000
|-
|
|0.685000
| -6.750000
|-
|
|3.385000
| -6.750000
|-
|
|6.085000
| -6.750000
|-
|
|8.785000
| -6.750000
|-
!
!
!
|-
|
| -10.115000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.715000
| -9.450000
|-
|
| -2.015000
| -9.450000
|-
|
|0.685000
| -9.450000
|-
|
|3.385000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|8.785000
| -9.450000
|-
!
!
!
|-
|
| -10.115000
| -12.150000
|-
|
| -7.415000
| -12.150000
|-
|
| -4.715000
| -12.150000
|-
|
| -2.015000
| -12.150000
|-
|
|0.685000
| -12.150000
|-
|
|3.385000
| -12.150000
|-
|
|6.085000
| -12.150000
|-
|
|8.785000
| -12.150000
|}

===== Coords for "UCSB_Cal" Calibration Patterns =====
Each of the above "''UCSB_Cal''" cells, including all 7 patterns, is repeated on the following coordinates across the plate (coords are to the center of the "''UCSB_Cal''" cell):
{| class="wikitable"
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X

(Wafer, mm)
!Image Shift
Y

(Wafer, mm)
|-
|2.610000 , 2.610000
| -9.450000
|12.150000
|-
|same as above
| -6.750000
|12.150000
|-
|" "
| -4.050000
|12.150000
|-
|" "
| -1.350000
|12.150000
|-
|" "
|1.350000
|12.150000
|-
|" "
|4.050000
|12.150000
|-
|" "
|6.750000
|12.150000
|-
|" "
|9.450000
|12.150000
|-
! colspan="3" |
|-
|
| -9.450000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.050000
|9.450000
|-
|
| -1.350000
|9.450000
|-
|
|1.350000
|9.450000
|-
|
|4.050000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|9.450000
|9.450000
|-
! colspan="3" |
|-
|
| -9.450000
|6.750000
|-
|
| -6.750000
|6.750000
|-
|
| -4.050000
|6.750000
|-
|
| -1.350000
|6.750000
|-
|
|1.350000
|6.750000
|-
|
|4.050000
|6.750000
|-
|
|6.750000
|6.750000
|-
|
|9.450000
|6.750000
|-
! colspan="3" |
|-
|
| -9.450000
|4.050000
|-
|
| -6.750000
|4.050000
|-
|
| -4.050000
|4.050000
|-
|
| -1.350000
|4.050000
|-
|
|1.350000
|4.050000
|-
|
|4.050000
|4.050000
|-
|
|6.750000
|4.050000
|-
|
|9.450000
|4.050000
|-
! colspan="3" |
|-
|
| -9.450000
|1.350000
|-
|
| -6.750000
|1.350000
|-
|
| -4.050000
|1.350000
|-
|
| -1.350000
|1.350000
|-
|
|1.350000
|1.350000
|-
|
|4.050000
|1.350000
|-
|
|6.750000
|1.350000
|-
|
|9.450000
|1.350000
|-
! colspan="3" |
|-
|
| -9.450000
| -1.350000
|-
|
| -6.750000
| -1.350000
|-
|
| -4.050000
| -1.350000
|-
|
| -1.350000
| -1.350000
|-
|
|1.350000
| -1.350000
|-
|
|4.050000
| -1.350000
|-
|
|6.750000
| -1.350000
|-
|
|9.450000
| -1.350000
|-
! colspan="3" |
|-
|
| -9.450000
| -4.050000
|-
|
| -6.750000
| -4.050000
|-
|
| -4.050000
| -4.050000
|-
|
| -1.350000
| -4.050000
|-
|
|1.350000
| -4.050000
|-
|
|4.050000
| -4.050000
|-
|
|6.750000
| -4.050000
|-
|
|9.450000
| -4.050000
|-
! colspan="3" |
|-
|
| -9.450000
| -6.750000
|-
|
| -6.750000
| -6.750000
|-
|
| -4.050000
| -6.750000
|-
|
| -1.350000
| -6.750000
|-
|
|1.350000
| -6.750000
|-
|
|4.050000
| -6.750000
|-
|
|6.750000
| -6.750000
|-
|
|9.450000
| -6.750000
|-
! colspan="3" |
|-
|
| -9.450000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.050000
| -9.450000
|-
|
| -1.350000
| -9.450000
|-
|
|1.350000
| -9.450000
|-
|
|4.050000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|9.450000
| -9.450000
|-
! colspan="3" |
|-
|
| -9.450000
| -12.150000
|-
|
| -6.750000
| -12.150000
|-
|
| -4.050000
| -12.150000
|-
|
| -1.350000
| -12.150000
|-
|
|1.350000
| -12.150000
|-
|
|4.050000
| -12.150000
|-
|
|6.750000
| -12.150000
|-
|
|9.450000
| -12.150000
|}

File:RaithEBPG 2026-03.png

2026-04-01T00:23:40Z

John d: John d uploaded a new version of File:RaithEBPG 2026-03.png

== Summary ==
Photo of Raith EBPG 5150 with user, 2026-03-31 Demis D. John.

E-Beam Lithography System (Raith EBPG 5150+)

2026-04-01T00:15:36Z

John d: added photo

File:RaithEBPG 2026-03.png

2026-04-01T00:15:21Z

John d: Photo of Raith EBPG 5150 with user, 2026-03-31 Demis D. John.

== Summary ==
Photo of Raith EBPG 5150 with user, 2026-03-31 Demis D. John.

Digital Microscope (Olympus DSX1000)

2026-03-31T23:39:37Z

John d: SOP TBA

{{tool2|{{PAGENAME}}
|picture=OlympusDSX1000.jpg
|type = Inspection, Test and Characterization
|super= Tony Bosch
|super2= Demis D. John
|location=Bay 4
|description = Digital Optical Microscope
|manufacturer = [https://www.olympus-ims.com/en/microscope/dsx/ Olympus]
|materials =
|model=DSX1000}}
=About=
The Olympus DSX1000 is a high-resolution digital microscope with full electronic control, multiple imaging modes and sophisticated analysis software built-in.

The built-in optical magnification allows for high-resolution imaging without changing objectives. The system has applies Digital image stabilization and software image enhancement.

Users must be very careful to '''avoid crashing the 50x objective''', because it does not rotate out of the way like our other microscopes.

===Technique & Capabilities===

* Digital only (view through computer)
* Optical Magnification 5–500X + Digital Zoom
* Objectives: 5x, 50x & Long-Working Dist. 10x, 40x
* Imaging Modes:
** Bright Field
** Dark Field
** DIC (Nomarski w/ varying polarization)
** Oblique Illumination (varying illum. angle)
** Polarized Illumination (varying pol.)
* Top Reflected Illumination (Episcopic)
* Camera Capture: 2.35 million pixel color CMOS
* Max Capture Resolution: 5760 × 3600 px

==Operating Procedures==
[[Olympus DSX1000 - Quick Start|Olympus DSX1000 Quick Start.pdf]] - ''to be added''

== Other Info ==
'''''Equip > Characterization > [[Microscopes]]''''' - ''see a list of all our microscopes''

Digital Microscope (Olympus DSX1000)

2026-03-31T23:39:08Z

John d: updated scope specs

{{tool2|{{PAGENAME}}
|picture=OlympusDSX1000.jpg
|type = Inspection, Test and Characterization
|super= Tony Bosch
|super2= Demis D. John
|location=Bay 4
|description = Digital Optical Microscope
|manufacturer = [https://www.olympus-ims.com/en/microscope/dsx/ Olympus]
|materials =
|model=DSX1000}}
=About=
The Olympus DSX1000 is a high-resolution digital microscope with full electronic control, multiple imaging modes and sophisticated analysis software built-in.

The built-in optical magnification allows for high-resolution imaging without changing objectives. The system has applies Digital image stabilization and software image enhancement.

Users must be very careful to '''avoid crashing the 50x objective''', because it does not rotate out of the way like our other microscopes.

===Technique & Capabilities===

* Digital only (view through computer)
* Optical Magnification 5–500X + Digital Zoom
* Objectives: 5x, 50x & Long-Working Dist. 10x, 40x
* Imaging Modes:
** Bright Field
** Dark Field
** DIC (Nomarski w/ varying polarization)
** Oblique Illumination (varying illum. angle)
** Polarized Illumination (varying pol.)
* Top Reflected Illumination (Episcopic)
* Camera Capture: 2.35 million pixel color CMOS
* Max Capture Resolution: 5760 × 3600 px

==Operating Procedures==
[[Olympus DSX1000 - Quick Start|Olympus DSX1000 Quick Start.pdf]]

===Offline software===
[[Olympus Stream Desktop Offline Software (TEMP)]]

== Other Info ==
'''''Equip > Characterization > [[Microscopes]]''''' - ''see a list of all our microscopes''

Oxygen Plasma System Recipes

2026-03-11T01:18:14Z

John d: /* Ashers (Technics PEII) */ deleted Gasonics section

{{recipes|Dry Etching}}
==[[Ashers (Technics PEII)]]==

===CF4/O2 PEii===
Gas is CF4 / O2 (88%/12%)

====SiN Etching====

*Pressure = 300mT–350mT
*Power = 100W
*Etch Rate ≈ 50-100 nm/min. Varies.
*Process notes: If the back or edges of the SiN-coated wafer is important to keep SiN coated, you need to make sure to PR-protect the wafer underside, ''and'' the bevel/wafer edge, as the SiN can be removed in those areas as well if not covered by PR. You can coat the wafer bevel/edge using a swab, manually "painting" the bevel while the wafer is on a PR spinner vacuum chuck, and then the Brewer Lift-pin hotplate (Bay 7) to bake at ~100-110degC.

====Chamber Clean after CF4 Etching====

*Pressure = 300mT–350mT
*Power = 100W
*Time = 10min

===O2 Ashing===
O2; 300mT / 100W - on either Technics asher.

~15sec to make a surface hydrophilic, eg. before wet etching or applying HMDS/photoresist.

~30sec-3min to improve wirebonding pad metal prior to deposition of liftoff metal.

~1-5min to remove polymerized photoresist/scum after dry etching

~5-10min to strip ~0.5-1.0µm photoresist. Rotate wafer 180° halfway through etch. Optionally increase to 200W for faster etching.

Use glass slides to prevent wafers from sliding on platen.

==[[Plasma Clean (YES EcoClean)]]==
Some negative photoresists (eg. UVN) do not strip well without ion bombardment (requiring Technics PEii or RIE/ICP instead). We believe that the UV exposure from plasma may increase hardening via crosslinking.

Recipe Temperature control is by the lift-pins , with hotplate at 200°C

===N2/O2 Recipes===

====Recipe Names:====

*"'''STD-N2-O2-180C-3kW-3min'''"
**These recipes used to be named “180C-3kW-3min”, prior to 2023-09-15.
**The new, Renamed recipes are identical, except have a 1x pump/purge added to the start of the cycle to improve repeatability.
*Variations: (underlined portion of filename above)
**Temperature: 100C, 130C, 150C,180C
***NOTE: some wafers will get hotter than the indicated temperature, due to optical absorption. See below for alternative recipes that avoid this.
**Power: 3kW, 0.7kW
***3kW is very fast for full PR strip, but often increases substrate temperature significantly.
***0.7kW reduces substrate temperature, although exact values are not known.
**Time: Various times are available, with strings such as "30sec", "1min", "3min" etc.
*[[YES Recipe Screenshots: STD-N2-O2|Recipe screenshots]]

====Recipe Characterization:====

*[[YES-150C-Various-Resists|Various Resists Etched at 150C-3kW]]
*[[YES-SPR220-Various-Temps|SPR220-7 at 3kW various Temps with N2/O2 recipes]]

3kW recipes appear to gradually heat wafers beyond the hotplate temperature, and also expose the underside of the wafer. Very efficient cleaning of positive photoresists, but exact temperature is unknown and may increase with time.

====N2/O2 effect on Gold contacts & Substrate Temperature====
These Nitrogen-containing recipes, at both 3kW and 0.7kW, have a tendency to oxidize Gold, turning Gold contacts brown. We found that the optical emission of the N2 plasma emits strongly in the visible, which is absorbed especially by Gold (especially Blue/UV optical absorption, that's why Gold looks yellow), causing additional heating of the surface, perhaps as much as 100°C hotter. If your devices contain gold contacts, or are very temperature sensitive, consider using our O2-only recipes below.

===O2-Only Recipes===
O2-only recipes do not oxidize gold contacts, and have been found to have stable/repeatable temperatures, and lower PR etch rates than N2-O2 recipes. See below for PR etch rates.

NOTE: The O2 plasma does not emit much light, because the plasma is remote. The tool is etching even if the porthole does not look brightly lit.

*Recipe Names: "'''STD-O2-100C-3kW-3min'''"
*Variations: (underlined portion of filename above)
**Temperature: 100C, 130C, 150C, 180C
**Power: 3kW
**Time: Various times are available, with strings such as "30sec", "1min", "3min" up to "15min"
*[[YES Recipe Screenshots: STD-O2|Recipe Screenshots]]

====O2 Recipe Characterization====

*[[SPR220-7 at 3kW various temperature without N2 gas|O2 only recipes without N2 gas: SPR220-7 at 3kW various temperature]]
*[[Comparison of ash rate for different gas mixtures, especially between O2 only vs O2/N2 mixture.|Comparison of ash rate for O2-only vs O2/N2 mixture]]
*Refernce paper: [[Influence of Additive N2 on O2 Plasma Ashing Process in Inductively Coupled Plasma.pdf]]
*[[Gold surface oxidation (darkening) due to O2/N2 plasma; the need for O2 only recipe.|Gold surface oxidation (darkening) due to O2/N2 plasma; the need for O2 only recipes]]
*Note: Ruthenium layers will likely partially oxidize in these recipes, possibly turning brown.

'''Internal To Add:'''
• PR Etch rates for each recipe

==[[UV Ozone Reactor]]==
The UV Ozone Reactor is used for two purposes:

*Etch away organic residue with no ion bombardment
*Oxidize surface (monolayers) of a substrate, which has been used for
**Providing a wet-etchable sacrifical surface layer which is removed prior to deposition or regrowth
**Controlled digital etching, by wet etching the oxide and then repeating the oxidation/etch cycle.

==[[Plasma Activation (EVG 810)]]==
O2 and N2 plasma activation recipes are available on this tool.

These are the qualified recipes provided by EVG and will not require adjustment of the RF Match:

*[https://signupmonkey.ece.ucsb.edu/wiki/images/a/a6/ExSitu_0.4mbar.JPG ExSitu_0.4mbar – 0.4mbar, N2, 100/75W]
*[https://signupmonkey.ece.ucsb.edu/wiki/images/0/0a/ExSitu_0.4mbar_Line2.JPG ExSitu_0.4mbar_Line2 – 0.4mbar, O2, 100/75W]
*[https://signupmonkey.ece.ucsb.edu/wiki/images/c/c7/ExSitu_0.8mbar.JPG ExSitu_0.8mbar – 0.8mbar, N2, 100/75W]
*[https://signupmonkey.ece.ucsb.edu/wiki/images/e/ec/ExSitu_0.8mbar_Line2.JPG ExSitu_0.8mbar_Line2 – 0.8mbar, O2 100/75W]
*[https://signupmonkey.ece.ucsb.edu/wiki/images/0/02/Dis_0.2mbar_Line2.JPG Dis 0.2mbar_Line2 – 0.2mbar, O2, 125/75W]

== ICP-RIE Systems for O2 Plasma cleaning ==
Many of our RIE and ICP etchers have O2 plasma recipes for either PR strip or BARC etching.

We have found that ''in situ'' photoresist strip is usually the best process - running the PR strip without the wafer having left the vacuum chamber. Many etching tools allow you to chain sequential recipes together to make this faster.

Here is a list of those recipes, also found on those tool's recipe pages:

* [[RIE Etching Recipes#Photoresist and ARC (RIE 5)|RIE#5]] - PR and BARC etching
* [[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|Fluorine ICP Etcher]] - PR Strip & BARC etching
* [[ICP Etching Recipes#Photoresist and ARC etching (Panasonic 2)|Panasonic ICP #2]] - PR Strip & BARC etching

Oxygen Plasma System Recipes

2026-03-11T01:16:15Z

John d: /* Ashers (Technics PEII) */

{{recipes|Dry Etching}}
==[[Ashers (Technics PEII)]]==

===CF4/O2 PEii===
Gas is CF4 / O2 (88%/12%)

====SiN Etching====

*Pressure = 300mT–350mT
*Power = 100W
*Etch Rate ≈ 50-100 nm/min. Varies.
*Process notes: If the back or edges of the SiN-coated wafer is important to keep SiN coated, you need to make sure to PR-protect the wafer underside, ''and'' the bevel/wafer edge, as the SiN can be removed in those areas as well if not covered by PR. You can coat the wafer bevel/edge using a swab, manually "painting" the bevel while the wafer is on a PR spinner vacuum chuck, and then the Brewer Lift-pin hotplate (Bay 7) to bake at ~100-110degC.

====Chamber Clean after CF4 Etching====

*Pressure = 300mT–350mT
*Power = 100W
*Time = 10min

===O2 Ashing===
O2; 300mT / 100W - on either Technics asher.

~15sec to make a surface hydrophilic, eg. before wet etching or applying HMDS/photoresist.

~30sec-3min to improve wirebonding pad metal prior to deposition of liftoff metal.

~1-5min to remove polymerized photoresist/scum after dry etching

~5-10min to strip ~0.5-1.0µm photoresist. Rotate wafer 180° halfway through etch. Optionally increase to 200W for faster etching.

Use glass slides to prevent wafers from sliding on platen.

==[[Plasma Clean (Gasonics 2000)]]==
Recipes are posted at the tool, with photoresist etch rates.

==[[Plasma Clean (YES EcoClean)]]==
Some negative photoresists (eg. UVN) do not strip well without ion bombardment (requiring Technics PEii or RIE/ICP instead). We believe that the UV exposure from plasma may increase hardening via crosslinking.

Recipe Temperature control is by the lift-pins , with hotplate at 200°C

===N2/O2 Recipes===

====Recipe Names:====

*"'''STD-N2-O2-180C-3kW-3min'''"
**These recipes used to be named “180C-3kW-3min”, prior to 2023-09-15.
**The new, Renamed recipes are identical, except have a 1x pump/purge added to the start of the cycle to improve repeatability.
*Variations: (underlined portion of filename above)
**Temperature: 100C, 130C, 150C,180C
***NOTE: some wafers will get hotter than the indicated temperature, due to optical absorption. See below for alternative recipes that avoid this.
**Power: 3kW, 0.7kW
***3kW is very fast for full PR strip, but often increases substrate temperature significantly.
***0.7kW reduces substrate temperature, although exact values are not known.
**Time: Various times are available, with strings such as "30sec", "1min", "3min" etc.
*[[YES Recipe Screenshots: STD-N2-O2|Recipe screenshots]]

====Recipe Characterization:====

*[[YES-150C-Various-Resists|Various Resists Etched at 150C-3kW]]
*[[YES-SPR220-Various-Temps|SPR220-7 at 3kW various Temps with N2/O2 recipes]]

3kW recipes appear to gradually heat wafers beyond the hotplate temperature, and also expose the underside of the wafer. Very efficient cleaning of positive photoresists, but exact temperature is unknown and may increase with time.

====N2/O2 effect on Gold contacts & Substrate Temperature====
These Nitrogen-containing recipes, at both 3kW and 0.7kW, have a tendency to oxidize Gold, turning Gold contacts brown. We found that the optical emission of the N2 plasma emits strongly in the visible, which is absorbed especially by Gold (especially Blue/UV optical absorption, that's why Gold looks yellow), causing additional heating of the surface, perhaps as much as 100°C hotter. If your devices contain gold contacts, or are very temperature sensitive, consider using our O2-only recipes below.

===O2-Only Recipes===
O2-only recipes do not oxidize gold contacts, and have been found to have stable/repeatable temperatures, and lower PR etch rates than N2-O2 recipes. See below for PR etch rates.

NOTE: The O2 plasma does not emit much light, because the plasma is remote. The tool is etching even if the porthole does not look brightly lit.

*Recipe Names: "'''STD-O2-100C-3kW-3min'''"
*Variations: (underlined portion of filename above)
**Temperature: 100C, 130C, 150C, 180C
**Power: 3kW
**Time: Various times are available, with strings such as "30sec", "1min", "3min" up to "15min"
*[[YES Recipe Screenshots: STD-O2|Recipe Screenshots]]

====O2 Recipe Characterization====

*[[SPR220-7 at 3kW various temperature without N2 gas|O2 only recipes without N2 gas: SPR220-7 at 3kW various temperature]]
*[[Comparison of ash rate for different gas mixtures, especially between O2 only vs O2/N2 mixture.|Comparison of ash rate for O2-only vs O2/N2 mixture]]
*Refernce paper: [[Influence of Additive N2 on O2 Plasma Ashing Process in Inductively Coupled Plasma.pdf]]
*[[Gold surface oxidation (darkening) due to O2/N2 plasma; the need for O2 only recipe.|Gold surface oxidation (darkening) due to O2/N2 plasma; the need for O2 only recipes]]
*Note: Ruthenium layers will likely partially oxidize in these recipes, possibly turning brown.

'''Internal To Add:'''
• PR Etch rates for each recipe

==[[UV Ozone Reactor]]==
The UV Ozone Reactor is used for two purposes:

*Etch away organic residue with no ion bombardment
*Oxidize surface (monolayers) of a substrate, which has been used for
**Providing a wet-etchable sacrifical surface layer which is removed prior to deposition or regrowth
**Controlled digital etching, by wet etching the oxide and then repeating the oxidation/etch cycle.

==[[Plasma Activation (EVG 810)]]==
O2 and N2 plasma activation recipes are available on this tool.

These are the qualified recipes provided by EVG and will not require adjustment of the RF Match:

*[https://signupmonkey.ece.ucsb.edu/wiki/images/a/a6/ExSitu_0.4mbar.JPG ExSitu_0.4mbar – 0.4mbar, N2, 100/75W]
*[https://signupmonkey.ece.ucsb.edu/wiki/images/0/0a/ExSitu_0.4mbar_Line2.JPG ExSitu_0.4mbar_Line2 – 0.4mbar, O2, 100/75W]
*[https://signupmonkey.ece.ucsb.edu/wiki/images/c/c7/ExSitu_0.8mbar.JPG ExSitu_0.8mbar – 0.8mbar, N2, 100/75W]
*[https://signupmonkey.ece.ucsb.edu/wiki/images/e/ec/ExSitu_0.8mbar_Line2.JPG ExSitu_0.8mbar_Line2 – 0.8mbar, O2 100/75W]
*[https://signupmonkey.ece.ucsb.edu/wiki/images/0/02/Dis_0.2mbar_Line2.JPG Dis 0.2mbar_Line2 – 0.2mbar, O2, 125/75W]

== ICP-RIE Systems for O2 Plasma cleaning ==
Many of our RIE and ICP etchers have O2 plasma recipes for either PR strip or BARC etching.

We have found that ''in situ'' photoresist strip is usually the best process - running the PR strip without the wafer having left the vacuum chamber. Many etching tools allow you to chain sequential recipes together to make this faster.

Here is a list of those recipes, also found on those tool's recipe pages:

* [[RIE Etching Recipes#Photoresist and ARC (RIE 5)|RIE#5]] - PR and BARC etching
* [[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|Fluorine ICP Etcher]] - PR Strip & BARC etching
* [[ICP Etching Recipes#Photoresist and ARC etching (Panasonic 2)|Panasonic ICP #2]] - PR Strip & BARC etching

MLA150 - Troubleshooting

2026-03-09T01:57:39Z

John d: /* Misalignment */

Look below for the issue you're experiencing, to see if we have a workaround or solution.

Make sure you '''record your problem and solution in the log book'''! This is very important for allowing us to improve system stability and make repairs.

__TOC__

==Unexpected Behavior==

*If the software is acting unusual (eg. black screen), or stage is moving to an incorrect location, or ''Convert'' software unable to launch, it could be due to the computer running out of RAM memory.
**A computer restart typically resolves this. Run the [[MLA150 - Troubleshooting#Rebooting the Computer|'''restart procedure''']] further down this page to resolve.
*If you're seeing unexpected stopping of the exposure, either right at the beginning of the exposure, or in the middle (after clicking ''[Start Exposure]''), then the Design file may have become corrupted. Designs are prone to corruption if aborted partway through an exposure/conversion.
**Re-import your original GDS/BMP/DXF file in the ''[Convert Design]'' screen to try to resolve this.

==Out Of Focus Exposures==
After developing, you find that some of all of your pattern is extremely out of focus. Small features (less than ~100µm) don't show up at all, and large features are extremely rounded, sometimes with rainbows at the PR edges indicating extremely slanted photoresist.
[[File:Out of Focus Exposures - Carl Peterson (Krisnamoorthy Group, 2021-12).png|alt=Image showing CAD and corresponding Microscope image. Microscope features are severely rounded.|none|thumb|460x460px|Example of an out-of-focus exposure. Features <100µm do not resolve. (Courtesy Carl Peterson, Dec. 2021)]]

===Causes===
There are multiple possible causes for this issue:, all of which have to do with the Optical Autofocus' confocal surface detection:

#The Optical AutoFocus laser is starting the write on an extremely non-uniform part of the photoresist spin (eg. corner of quarter-wafer), which causes it to drive out of focus before the write starts.
#The Optical Autofocus driving off/onto a round wafer can also cause it to go out of focus during the write, with no warnings (it'll keep exposing).
#Very dark (low reflection) areas of the wafer can also cause the OptAF surface detection to lose signal, and lose the feedback signal needed to maintain focus during a write.

===Solutions for all substrate types===
For Samples that are less than ~1 or 2 inches, try the following methods (listed with most effective first):

#Before starting the exposure: '''Enable the Low/High Mag microscope''' (NOT Overview camera), and '''move the scope to a “good”/uniform region''' of the sample before hitting [Start Exposure]. Make sure the sample features (or dirt/defects) are in-focus, indicating that the OptAF is correctly tracking the surface. The system will perform an initial re-focus in this location right before beginning the exposure.
#Make sure the High/Low Res (not overview) camera is on a uniform area of the sample before hitting [Start Exposure].
#Make sure the ORIGIN (0,0) coordinate of your CAD file is placed in a relatively uniform area of your sample. Do not place the Origin at the corner or on PR edge-bead, as the Optical AF laser may do an initial measurement at this location. If you are trying to align your die to a corner, use [[MLA150 - Troubleshooting#Aligning to a quarter-wafer|this technique instead]].
#Remove thick photoresist edge-bead prior to exposure (eg. with razor blade, or a little EBR100 on a cotton swab). Some edge-bead removal techniques: [[Photolithography - Manual Edge-Bead Removal Techniques]]

===Solution for 3-4 inch wafers===

*Adjust your design/CAD file so the design is about ≥10mm from the edges of the wafer (in the Y direction especially) has been reported to help. The write-head overtravels past the CAD design by ~8-9mm, so this can prevent the head from hitting the PR edge-bead/wafer-edge (the cause of focus-loss).
*Try removing the edge-bead of your PR: [[Photolithography - Manual Edge-Bead Removal Techniques]]
*For large substrates, switching to Pneumatic Autofocus works well (although focus repeatabiity is less stable, eg. focus shifts by ±5 over a few weeks). PneuAF causes a few-mm of edge-bead area to expose out-of-focus, which is acceptable for full-wafers, but often too large exclusion for smaller samples.
**Contact the supervisor for info on switching to Pneumatic AF. '''Do NOT use PneuAF without first asking Staff!''' There is significant '''crash''' potential if performed incorrectly.
**PneuAF will usually have a slightly different defocus offset compared to OptAF. You should run a new FEM/Series with PneAF.
**PneuAF will require Focus/Exposure calibration (in Series mode) more often than OptAF.

===Debugging===
After exposure, open the logfile for your Job (see [[MLA150 - Troubleshooting#Exposure Logs .2F Reports|this tip for logfile location]]) and search for the word "''piezo''". This records the Z-height Piezo position - the physical autofocus position - at the end/start of each stripe (when the optical head changes direction, off the substrate). Since the piezo freezes motion off the substrate, this value indicates the autofocus piezo height at the edge of your substrate.

When in-focus on your substrate this should be in the range ~28,000 to 51,000 or so. If you see a value significantly outside of this range, then this usually means the autofocus drove to it's limit, because it was not tracking the substrate surface. Sometimes the first one or two stripes are in-focus, and then the rest are out of focus. Other times, the system is out of focus from the start, and stays this way for the entire exposure.

You can see the optical autofocus laser position in the camera, it is about 6µm up-left from the central crosshair. It is a confocal surface detection, which continuously tracks the surface – even while manually driving around the substrate before exposure. When this laser hits a bad point (eg. black /dark no reflection, or particle, or steep slope) it can lose surface tracking. During substrate load, the system attempts to land on the surface using this system.

Before exposure, if you see your surface is far out of focus, then your exposure will likely also be out of focus (the same continuous AutoFocus is active during microscope imaging).

*Try un/re-loading the substrate, and alter the substrate position
*Make sure there are no black/very dark spots on the substrate which would cause the system to be unable to optically detect the surface
*For transparent, thin substrates, try switching to blanket deposition and etching (instead of liftoff), to provide an opaque surface
*If nothing else works, use contact alignment with a photomask.

== "Autofocus is not working properly" ==

=== Symptom ===
When you click "Start Exposure", the system pops an error saying "'''''The Optical Autofocus is not Working Properly: [OK] [Cancel]'''''"

In addition, right before exposure you might see the substrate is out of focus, of the Optical Autofocus Spot is not visible (possibly indicating the substrate is out of focus).

=== Remedies ===

# The most common issue is that you did not measure and type in your substrate's thickness into the Substrate Template.
## If you "guessed' on the substrate thickness, your guess was not close enough
## Use the drop gauge by the tool to more accurately measure the thickness of your substrate - possibly measuring a few points, and type in the average into the Substrate Template.
# Something on the back of your wafer is significantly altering the focus on the top surface.
## For example, very thick photoresist can cause this, if it gets on the back of your wafer.
## Use a razor blade or AZ EBR to remove photoresist on the back of the wafer.
## Check for Particles on the wafer stage and the back of your wafer.

You may also optionally [[Photolithography - Manual Edge-Bead Removal Techniques#EBR100 Swabbing|remove the edge-bead (link to procedure)]] around the edge of the wafer to reduce focus issues.

==Exposure Logs / Reports==

**You can find a detailed log file of each exposure in the folder <code>C:\HIMT\LogFiles\ExposureLogs</code>. At the end of this file you can find final statistics from Field (Local) Alignment. You can copy the appropriate log file into your Nanofiles user folder to make it accessible via FTP.
**If you run into an unusual error, please let us know the Job Name, so that we can locate this log file if needed.

==Stitching==
The system raster scans the ~12x20µm exposure fields across the wafer, and there will be stitching errors at the boundaries.

The "fast-scan" axis is in ±Y, which causes the largest stitching errors to show up as Y-oriented stripes, ridges or bumps, every ~20µm in X. We estimate that these ridges indicate about 4-7% lower dose at the stitching boundary.

When you are fully-exposing your PR (typically with a bit of over-exposure, eg. ~20% overdose), these stitching boundaries are barely visible, if at all, and typically correspond to a ~50nm bump in the feature.

However for partially-exposed PR (such as in grey-scale exposure), these ridges will clearly manifest as Y-oriented ridges of ~4-7% lower exposure dose, and reduced underexposed PR.
[[File:MLA150 - 160D0F15 stitching notch - 01.jpg|alt=SEM of horizontal/vertical 400nm line/space|none|thumb|MLA150 stitching example - ~500nm line/space in positive PR, showing 50nm bumps oriented in Y-direction due stitching.]]
 Overexposing the design can reduce the size of these stitching bumps. Since that will also alter your feature size on-wafer, you can us the ''Convert'' correction "CD Bias" to correct your feature sizes accordingly, see [[MLA150 - Design Guidelines#High-Resolution Writing|this page]] for more info on using that option. Or just adjust your exposure CAD file feature sizes accordingly.

==Stage not centered during [Substrate Load]==
When the system moves the stage to place your sample under the lens, the center of the stage is '''not under the lens!'''

'''''WARNING''''': '''''Do NOT continue''''' if this occurs - there is significant danger of crashing the lens into a sample.

*'''''Cancel''''' the substrate load process.

===Workaround===

*In the software Menu, choose '''Tools > Initialize Stage''', then retry your Job.
*If that does not solve the problem, please [[MLA150 - Troubleshooting#Rebooting the Computer|'''reboot the computer (instructions below)''']], which will also reinitialize all motor controllers.

Note: if you chose a “Small” substrate template, the system always moves the sample under the '''overview camera''' at first, which is the the Left of the main write head. You’ll see the yellow microscope illumination around your sample. This is normal behavior.

==Defocus: unable to enter ±25 full range==
In the Setup screen, Editors for Resist or Series templates, you are limited to only ±10 defocus, even though the system is capable of ±25.

===Workaround===

#During Job Setup, make sure to choose "'''''_General-Focus'''''". User-made Resist templates usually won't have the setting correctly applied, unless they copied a Staff resist.
#In the Exposure screen - after wafer load etc. - you may still edit the defocus range, and in this screen you are able to type in the full range ±25. For a Series exposure (focus-exposure matrix, FEM), you can choose the "_Manual" template during Setup, and on the Expose screen you can edit the Series array to your needs with full defocus range.

==Convert software is unable to launch==

#Check whether the XWindows software is available in the Windows Start bar - sometimes the window lands behind the MLAMenu software.
#If an error window is indicating some error with launching convert, then perform the [[MLA150 - Troubleshooting#Rebooting the Computer|'''computer reboot procedure''']] below.

==Focus Depth Motor Not Initialized==
After an exposure has been initiated, but before exposure has actually begun, you get an error window stating the the "Focal Depth Motor is not initialized."

'''Notify staff'''

We can reinitialize that motor remotely, which will allow you to start your exposure.

==Nanofiles folder not showing up on SFTP==
'''Problem:''' When you log into the Nanofiles FTP server, you don't see an "MLA_Heidelberg" folder to upload your CAD files.

'''Reason:''' After your user's folder is created in the Users_Nanofiles folder on the MLA computer, our FTP server only creates the corresponding folder on the Nanofiles FTP site once per day around 00:00 midnight.

Wait until the next morning and your folder should be available. If you need immediate access, please email the tool supervisors, and one of us can upload your file into our Staff folder on the tool.

You can find more troubleshooting info about the Nanofiles FTP at the corresponding [[Frequently Asked Questions#How do I get my files from the NanoFab computers.3F|Frequently Asked Questions section]].

==Aligning to a quarter-wafer/irregular piece==
For alignment of your die to a quarter-wafer, one accurate method for accounting for both rotation and die placement is to

use 2nd Layer / Manual Alignment with 2 coordinates to align to the wafer's flat edge.
[[File:MLA Quarter-Wafer Alignment.jpg|alt=schematic of aligning to a quarter-wafer, using manual alignment|thumb|Using Manual Alignment to align your CAD file to a quarter-wafer.|none|500x500px]]
Detailed procedure is as follows:

#'''Set up your''' '''CAD file''' with a mock-up of the quarter wafer on a construction Layer, and align your die (on a production Layer) to this. The quarter-wafer should have a ''flat'' edge "down" (negative Y).
#Make sure the '''Origin (0,0)''' of your CAD file is in a uniform region of your quarter wafer- ie. ''not'' on the edge/edge-bead/non-uniform photoresist.
#Determine '''coordinates''' to two points along the the Bottom edge of the quarter-wafer.
#On the MLA, use '''"2nd layer" exposure''', enabling alignment.
#Use the '''"Rectangular" substrate template''' (Usually "'''''_Rectangular_OptAF'''''")
#'''Load''' your quarter-wafer according to your CAD file, with a flat-edge "down" (–Y).
#Type in the '''two''' '''coordinates''' to the pretend alignment marks along the wafer bottom.
#On the '''[Alignment]''' screen, click '''[Move to First Mark]'''
#If you need to move the stage to see the wafer edge, move ''only'' in Y (up/down), don't move left/right. If you make a mistake, click '''[Move to First Mark]''' again.
#Change the Alignment dropdown list from "CrossAlignment" --> "'''Manual'''"
#Choose '''High''' or '''Low''' magnification on the microscope. (High will be more accurate.)
#Click '''[Measure]''', and the system will ask you to click on the alignment mark on the video window.
#'''Click on the wafer edge''', but directly above/below the screen's central crosshair - so we're only correcting the Y-coordinate. The mouse crosshair's Y-axis should line up with the screen's central crosshair.
#Click '''[Accept]''', and the system will move to the 2nd mark coordinate.
#'''Repeat''' with the second location on the wafer edge, correcting only the Y-position.
#On the '''[Exposure]''' screen, '''Disable''' "Scaling" and "Shearing", and '''Enable "Rotation"'''. The CAD file's origin should be accurately placed in the center of the schematic, and aligned to the wafer edge.
#Proceed with exposure as normal (setting Dose/Defocus and [Expose]).
''Developed+Written by [[Demis D. John]], 2023''

== Misalignment ==
Inadequate alignment between previous and current lithography layers requires some additional investigation.

First, pay attention to the calculated alignment corrections.

After alignment, the ''[Exposure]'' screen will show calculated values for:

* Rotation : [√] enabled by default.
* Scaling [_]: '''dis'''abled by default
* Shearing [_]: '''dis'''abled by default

Observe the calculated values of Scaling and Shearing (angle between X & Y axes) after aligning.

* Scaling (aka. magnification) errors will manifest as a walk-off as you get further away from some point (eg. substrate center).
** If Scaling shows a value far away from 1.000, but you left the checkbox disabled, the magnification was ''not'' corrected during exposure. You may try '''En'''abling the Scaling correction prior to exposure, so the MLA will adjust the exposed patterns accordingly.
** The walk-off will be larger for larger substrates/patterns.
** You can calculate how much misalignment you will get for some magnification error, for example:
** 1.000 100 (aka. 100 [https://en.wikipedia.org/wiki/Parts-per_notation ppm]) scaling error over a 4-inch wafer, assuming the wafer center is perfectly aligned, will result in 1.000100 * 20mm = 2µm of misalignment 2cm away from wafer center.
** Typical scaling that does not require correction will be within ~10ppm (0.999 990 to 1.000 010).
* Shearing (angle between X & Y axes) will manifest as an angle-based walk-off. We have never yet seen this issue when matching between our tools.

Adding more alignment marks, spaced further apart, allows for better curve-fitting and statistics when the software calculates these values in Global alignment modes.

=== Alignment Matching between Litho Tools ===
Note that it is common and ''expected'' that different lithography systems will have some mismatch between their scaling & orthogonality calibrations - but those can be corrected out by enabling the above checkboxes and measuring more high-quality marks. This is called "matching" the alignment between different machines.

=== Analyzing misalignment ===
It is recommended that you include [[Calculators + Utilities#General CAD files for Lithography|Vernier alignment]] patterns between layers to measure misalignment using the microscopes.

To understand the origin/mechanism of misalignment you are experiencing, it is recommended to plot the '''misalignment versus wafer location''' - this often elucidates the solution;

Draw a small arrow indicating the direction of misalignment. For example, if 2nd layer is misaligned by (-2µm , 0µm) then you draw an arrow pointing left ← at that wafer location.

For example:
[[File:MLA150 Alignment versus Wafer Location v1.jpg|alt=screenshot showing misalignment versus wafer location, with arrows indicating misalignment direction|none|thumb|Example of misalignment analysis. Arrows indicate direction of misalignment at each ensured location. In this case the arrows clearly indicate the misalignment is due to '''Magnification/Scaling''', not X/Y shift.]]

=== Die-to-Die Alignment ===
If analyzing the misalignment doesn't fix your alignment issue (or you can't figure out what is causing it), then you can run "die-to-die" alignment, aka. "local alignment" (GCA parlance), referred to as "Field alignment" on the MLA software.

This requires that every die has an automatic alignment mark (typically a cross), and that your CAD file is of a single die.

The system will still perform global alignment to the wafer to get "close" to each die, but after that, will re-align each die right before exposure, and will expose only a single die at a time.

This significantly increases exposure time.

Please see the "Field alignment" section of the [[Maskless Aligner (Heidelberg MLA150)#Operating Procedures|Operating procedure]] for detailed instructions.

''Written by [[Demis D. John]], 2024-10''

==Greyscale Lithography Limitations==
The MLA150 does have grey-scale patterning capabilities, but has some limitations & workarounds that we have identified. Please see this page for the [[MLA150 - Design Guidelines#Limitations .26 Workarounds|Greyscale limitations and design guidelines.]]

==Rebooting the Computer==
Restarting the computer can resolve errors due to the system running out of memory (RAM), force the reinitialization & homing of motors, and reinitialize the ''convert'' virtual machine.

====Restart Procedure====

*In the MLAMenu (main) software, go to File > Exit.
**It takes a minute or so to close everything. It will also close the camera viewer (SharkVision).
*Reboot the computer via Windows Start > Power > Restart
**It takes a few mins for the computer to reboot.
*On the Windows login screen (Looks like "Heidelberg instruments" background), start typing to log in. Login info is written at the computer.
*After logging back in, wait ~1 min until the 2 icons appear next to the Time in the start bar. (SiiPlus and XMing)
*Then launch MLAMenu.exe, wait ~1 min until it has completed initializing.
*Make sure the "Hardware" section of the software shows all components as "OK" or "Initialized"

System is ready to run exposure jobs.

IBD: Calibrating Optical Thickness

2026-03-07T00:32:18Z

John d:

'''''Tool: [[Ion Beam Deposition (Veeco NEXUS)|Ion Beam Deposition (Veeco Nexus IBD-O)]]'''''

Basic method for calibrating optical thickness, for [https://en.wikipedia.org/wiki/Distributed_Bragg_reflector DBR]/multi-layer optical coatings (2 alternating films only). Commonly used for SiO2/TaO DBR mirrors/filters.

*Get dep rate & refractive index (RIX) of individual SiO and TaO films, using single-deps and [[Ellipsometer (Woollam)|J.A. Woolam Ellipsometer]] or equivalent tool. Approx. rate from previous user is also acceptable.

:*Get RIX at the target wavelength, using "Derived Params" on JAW or Cauchy equation A/B/C params. For example, if targeting a DBR centered at 1550nm (target λ=1550nm), you will want to know the RIX at 1550nm specifically.

*Calculate approximate dep. time to achieve a 1/4-wave thickness at the target wavelength, for each film (SiO and TaO).

:*For example, if the dep. rate of SiO2 measured at 5.2nm/min and RIX is n1550 = 1.494, then
::::''SiO 1/4λ thickness: d1/4λ = 1550nm / 4 / 1.494 = 259.4nm''
::::'''''SiO 1/4λ time''': t1/4λ = 259.4nm ÷ 5.2nm/min = 49.88min = '''2993.077 sec'''''
::::(and then do the same for TaO)

*Deposit a fabry-perot 1/2-λ of one film (SiO or TaO) cavity onto a Silicon piece, using the above 1/4-λ deposition times (aka. "SiO/4" or "TaO/4" in the following), to calibrate that film's optical-thickness.

:*eg. for SiO Fabry-Perot cavity (aka. SiO-FP):
::::''SiO/4 + TaO/4 + SiO/4 + TaO/4 + SiO/4 + TaO/4 + ('''SiO/4 + SiO/4''') + TaO/4 + SiO/4 + TaO/4 + SiO/4 + TaO/4''
::*Here we used only 3 periods of DBR on either side of the 1/2-λ cavity, to speed up the deposition.

*Measure the reflectivity on [[Optical Film Spectra + Optical Properties (Filmetrics F10-RT-UVX)|Filmetrics F10-RT]].
*Locate the wavelength of the minimum (dip) in the optical spectrum. Spectrum will typically be very broad, due to omitting many of the surrounding DBR layers for speed.

:*For example, the trough might show a minimum at 1600nm instead of the targeted 1550nm.

*Correct the film's optical thickness as so:

:::t1/4λ * λtarget / λmeasured = ''corrected'' t1/4λ
:::2993.077 sec * (1550nm / 1600nm) = '''2899.543 sec''' for SiO/4 layers
::*Use this corrected time for all SiO/4 layers.
::*You only need to edit the One "SiO2_dep" step in the IBD recipe, which will also change all "SiO2_dep" steps in the recipe.
:*Here is an example of a Fabry-Perot cavity that was targeting a 1050nm center-wavelength, but measured a 1100nm trough:[[File:IBD SiO-FP - long 1100nm - Reflectivity Spectrum (EMpy).png|alt=Simulated plot of SiO-FP reflectivity, for a 1050nm target but measured trough at 1100nm|none|thumb|Example: Targeting a 1050nm SiO-FP, the measured trough location is at 1100nm. ]]In this case, one would apply a correction to the ''SiO/4 time'' by multiplying by (''1050÷1100)''.

*Do the same Fabry-Perot correction for the other film, in this case do an "TaO-FP", and apply the new TaO/4 time to the recipe.
*Perform a test-DBR deposition onto Silicon, eg. 9 periods (less than full, which could be 15 periods or more), and measure on [[Optical Film Spectra + Optical Properties (Filmetrics F10-RT-UVX)|Filmetrics F10-RT]], to confirm that center wavelength is in the right spot. An example DBR test-dep targeting 1050nm looks like this:[[File:IBD 9-period DBR - Reflectivity Spectrum (EMpy).png|alt=Example reflectivity spectra of the 9-period DBR test-dep, showing 1050nm center-wavelength in the middle of the DBR high-reflectivity spectrum.|none|thumb|Example reflectivity spectra of the 9-period DBR test-dep.]]
*Perform full-DBR deposition onto production parts. Include a flat Silicon witness for measuring the final DBR reflectivity spectrum. 

*Sources of error: thick, stressy films exhibit the stress-optic effect, in which compressed films (closer to the substrate) will often show a reduction in RIX. In going from a 9-period DBR to a 18-period DBR, you might see a ~10-20nm blue-shift. Some users for whom such a shift is outside the device tolerance will do a full DBR dep, then apply a % reduction to all dep times to further dial in the DBR reflectivity band.
*The same method can be used to calibrate optical-thickness for arbitrary multi-layer optical filters.

Note, you can verify/better understand the above method using any electromagnetic thin-film simulator. For example, [https://github.com/lbolla/EMpy EMpy] has a simple transfer-matrix example for doing this, along with RIX models contributed by [[Demis D. John|Demis]]. Demis created the above simulations using EMpy.

 
Developed by Demis D. John, Bob Farrell, Dustin Kleckner, ~2008-2010. This is the same method used by UCSB VCSEL groups years earlier, for calibrating VCSEL MOCVD/MBE growths. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you publish papers using this information.
[[category:Process]]

Dry Etching Recipes

2026-03-03T00:20:58Z

John d: fixed DSEiii recipe llinks (changed heading titles.

===[[Process Group - Process Control Data#Etching .28Process Control Data.29|Process Control Data]]===
''See above [[Process Group - Process Control Data#Etching .28Process Control Data.29|linked page]] for [https://en.wikipedia.org/wiki/Statistical_process_control process control data] (dep rate/stress etc. over time), for a selection of often-used dry etches''

===Dry Etching Tools/Materials Table===

==== Process Maturity Ranking ====

* <code>'''R6'''</code> - most mature process with regular calibrations recorded on SPC charts.
* …
* <code>'''R1'''</code> - least mature - only run once ever.

''The Key/Legend for this table's <code>A...R6</code> values is at the [[Dry Etching Recipes#Process Ranking Table|bottom of the page]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center; font-size: 95%" border="1"
|-
! colspan="15" width="725" height="45" |<div style="font-size: 150%;">Dry Etching Recipes</div>
|- bgcolor="#d0e7ff"
| bgcolor="#eaecf0" |
! colspan="2" |'''[[RIE Etching Recipes|RIE Etching]]'''
! colspan="5" |'''[[ICP Etching Recipes|ICP Etching]]'''
! colspan="4" bgcolor="#d0e7ff" align="center" |'''[[Oxygen Plasma System Recipes|Oxygen Plasma Systems]]'''
! colspan="3" bgcolor="#d0e7ff" align="center" |'''[[Other Dry Etching Recipes|Other Dry Etchers]]'''
|- bgcolor="#d0e7ff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E646V)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ag
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|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Al Etch (Panasonic 1)|R1}}
|[[ICP Etching Recipes#Al Etch .28Panasonic 2.29|R2]]
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Au
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|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Cr
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|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Cr Etch (Panasonic 1)}}
|R1
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Cu
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ge
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|A
|R1
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|[[Other Dry Etching Recipes|R2]]
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Mo
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|R1
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!Nb
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|A
|R1
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|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ni
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|[[Other Dry Etching Recipes|R3]]
|-
!Os
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|A
|R1
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|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Pt
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|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ru
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|A
|[[ICP Etching Recipes#Ru .28Ruthenium.29 Etch .28Panasonic 2.29|R3]]
|
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Si
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|
|[[ICP Etching Recipes#High Rate Bosch Etch (DSEIII)|R6]], [[ICP Etching Recipes#Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)|R3]]
|[[ICP Etching Recipes#Si Etch Recipes (Fluorine ICP Etcher)|R6]]
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|R1
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|[[Other Dry Etching Recipes|R3]]
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ta
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|A
|R1
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ti
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|{{rl|ICP Etching Recipes|Ti Etch (Panasonic 1)}}
|R1
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |W
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|R3
|{{rl|ICP Etching Recipes|W-TiW Etch (Panasonic 1)}}
|R1
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|R1
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!TiW
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|R3
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|R1
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|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al2O3
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|A
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Al2O3 (Sapphire)
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|{{rl|ICP Etching Recipes|Sapphire Etch (Panasonic 1)}}
|R1
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlGaAs
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|[[RIE Etching Recipes|R3]]
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|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
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|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |AlGaN
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|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R2]]
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlN
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|R1
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!BCB
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|A
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|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |CdZnTe
|[[RIE Etching Recipes|R3]]
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaAs
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|[[RIE Etching Recipes|R3]]
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|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|[[ICP Etching Recipes#GaAs Etch .28Panasonic 2.29|R6]]
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |GaN
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|[[RIE Etching Recipes|R3]]
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|{{rl|ICP Etching Recipes|GaN Etch (Panasonic 1)}}
|R1
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R6]]
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaSb
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|A
|R1
|R1
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |HfO2
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InGaAlAs
|[[RIE Etching Recipes|R3]]
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|R1
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |InGaAsP
|[[RIE Etching Recipes|R3]]
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|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R3]]
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InP
|[[RIE Etching Recipes|R3]]
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|A
|R1
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R6]]
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|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ITO
|[[RIE Etching Recipes|R3]]
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|R1
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!LiNbO3
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|R1
|- bgcolor="#ffffff"
!Photoresist & Organics
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|[[RIE Etching Recipes#Photoresist and ARC (RIE 5)|R3]]
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|[https://wiki.nanotech.ucsb.edu/wiki/ICP_Etching_Recipes#Photoresist_and_ARC_Etching_.28Panasonic_1.29 R3]
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|R3
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
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|R1
|-
!ARC (Anti Reflective Coating)
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|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
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|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiC
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|{{rl|ICP Etching Recipes|SiC Etch (Panasonic 1)}}
|R1
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiN
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|[[ICP Etching Recipes#Si3N4 Etching .28Fluorine ICP Etcher.29|R3]]
|{{rl|ICP Etching Recipes|SiNx Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiNx Etching .28Panasonic 2.29|R3]]
|
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiO2
|
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|[[ICP Etching Recipes#SiO2 Etch (DSEiii)|R3]]
|[[ICP Etching Recipes#SiO2 Etch Recipes (Fluorine ICP Etcher)|R6]]
|{{rl|ICP Etching Recipes|SiO2 Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiO2 Etching .28Panasonic 2.29|R6]]
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|[[Other Dry Etching Recipes|R3]]
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiOxNy
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|A
|R1
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|R1
|-
!SU8
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|A
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|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ta2O5
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|A
|R1
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |TiN
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |TiO2
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnO2
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZnS
|[[RIE Etching Recipes|R3]]
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnSe
|[[RIE Etching Recipes|R2]]
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZrO2
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E640)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|}

===Process Ranking Table===
Processes in the table above are ranked by their "''Process Maturity Level''" as follows:
{| class="wikitable"
!Process Level
! colspan="11" |Description of Process Level Ranking
|-
|A
| colspan="11" |Process '''A'''llowed and materials available but never done
|-
|R1
| colspan="11" |Process has been ran at least once
|-
|R2
| colspan="11" |Process has been ran and procedure is documented
|-
|R3
| colspan="11" |Process has been ran, procedure is documented, and data is available
|-
|R4
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''no''' in-Situ control available
|-
|R5
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''and''' in-Situ control available
|-
|R6
| colspan="11" |Process has a documented procedure and control charts/limits available. Controlled process.
|}
[[Category:Processing]]

ICP Etching Recipes

2026-03-03T00:18:17Z

John d: /* DSEIII_(PlasmaTherm/Deep_Silicon_Etcher) */ FICP backup recipes to bottom, renamed "low etch rate" to "Silicon..."

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''[[ICP Etching Recipes#Process Control Data (DSEiii)|Process Control Data below]]''' - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==
*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with Al2O3 hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}

=== '''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)''' ===
[[File:DSE plot.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281|232x232px]]
* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots''']

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
We have a new wafer-mounting process for through-silicon etching, using the UV-Release Dicing tape. Contact [[Demis D. John|staff]] for more info.
-- [[Demis D. John|Demis]] 2026-02-10

'''NOTE''':
'''DO NOT RUN''' the wax-mounting process without discussing with staff first. The wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer!
''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11

{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
with wax-mounting (small pieces only)
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)==

*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
**Smooth, Vertical, E.R. uniformity is within 5% on wafer
**Tested with 4" wafers that are ~50% open with UV6 PR
*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Older, alternate Si "shallow/smooth" etch recipe.
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

== SiO2 Etch (DSEiii) ==
These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].
*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
**Vertical/Smooth
**Tested by mounting 1cmx1cm piece with oil on 4" Si

==F-ICP Backup Recipes (DSEiii)==
These recipes were developed to serve as backup processes for the calibrated [[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|'''Fluorine-ICP''']] SiO2 and Si etches [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]].

[https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing FICP to DSE etch processes].

*'''[[ICP Etching Recipes#Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)|Si Etch v1 (⭐️Production)]]'''
*'''[[ICP Etching Recipes#SiO2 Etch (DSEiii)|SiO2 Etch v1 (⭐️Production)]]'''

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the [[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|'''Process Control Data below''']] - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

=== Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
[[File:FICP-Si.png|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots''']

==SiO2 Etch Recipes (Fluorine ICP Etcher)==
[[File:FL-ICP_50W_SiO2_etch_with_Ru_Hard_Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|thumb|266x266px|50W SiO2 Etch w/ Ru Hardmask]]
[[File:FL-ICP_200W_SiO2_Etch_with_Ru_Hardmask_-_Ning_Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|thumb|266x266px|200W SiO2 Etch w/ Ru Hardmask (Ning Cao)]]
*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.

=== [//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] ===

* Click above for [http://wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf Full Process Traveler]
** Process written for Sputtered Ru & I-Line GCA Stepper litho
** Can be transferred to ALD Ru or DUV/EBL Litho.

*''Ning Cao & Bill Mitchell, 2019-06''
*''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
*''Etch also works well with PR masking''
*''Chemistry: CHF3/CF4''
*''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
*Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
*50W Bias: ('''recommended''')
**Selectivity to photoresist: 1.10–1.20
**SiO2 selectivity to Ru: 36
**SiO2 etch rate: 263nm/min
**''Smoothest vertical etch for SiO2.''
*200W Bias: (higher etch rate)
**SiO2 selectivity to Ru: 38
**SiO2 etch rate: 471nm/min
*This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
*Updates: Many users have found that SiO2-masking the Ru hardmask results in vastly improved photoresist selectivity, making litho+etch of small features much better.
**Layer stack looks like: SiO2 (or other dielectric target layer to etch) / Ru hardmask / SiO2 hardmask (thin) / Photoresist.
**Typically strip the masks+PR with all dry etching. That means the entire etch process (all etches and strips) can be run ''in situ'' on the Panasonic ICP in a rapid single-tool etch process.
===Process Control: SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
[[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots''']

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===
[[File:SEM Image.png|thumb|New PR Strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Old PR strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**45sec-1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=
'''Panasonic ICP#1 is currently down -''' Use Panasonic ICP#2 instead. Most processes directly transfer with only small change in etch rate. Data kept here for historical purposes only.

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure & Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get on the ''back'' of the carrier wafer or you will get Helium cooling errors.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch, and see their SEM's.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
**''This etch is used in our Process Control weekly cals run by [[Process Group Interns|NanoFab Interns]]. Very stable over time ±5%.''
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

===Process Control: SiO2 Etch with CHF3/CF4 (Panasonic 2)===
[[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|thumb|269x269px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts] for SiO2 etching.|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]''Weekly cal etches of the CF4/CHF3 SiO2 etch, run by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots''']

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*GaAs Etch Cal - ''Noah Dutra & Fatt Foong, 2025-02-12''
**Etch Rates ~1um/min, Selectivity to SiO2 ~ 27:1, Sidewalls ~ 90°
**Etch Rate/Selectivity [https://wiki.nanofab.ucsb.edu/w/images/7/76/GaAs_pressure_experiment.png highly sensitive to pressure] (image credit: Terry Guerrero)
**Cal Sample: ~1cm sample etched mounted with oil onto 150mm Si carrier
**Recipe: 0.5Pa, 100/900W, N2/Cl2=10/20sccm
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf Non-Calibration GaAs Etch Recipes - Panasonic 2 - Cl2N2]

===Process Control: GaAs Etch with N2/Cl2 (Panasonic 2)===
[[File:GaAs Etch ICP2 SPC.png|alt=example ICP2 process control chart|thumb|249x249px|[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for GaAs etching.|link=https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281]]
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=0#gid=0 GaAs Etch with N2/Cl2 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 GaAs Etch with N2/Cl2 - '''Plots''']

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

=== Process Tips ===
* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* InP requires fairly high temperatures for making the Indium products volatile - so going to full-wafers (which are cooler) may requiring the table temperature. We have found that temperatures of ~150⁰C minimum may be required for preventing grassing etc.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==InP Ridge Etch (Oxford ICP Etcher)==
===High-Temp (200°C) InP Etch Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
[[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|thumb|218x218px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for 200°C InP Etch|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

===Low-Temp (60°C) InP Etch Process===
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: Low-Temp (60°C) InP Etch ====
[[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts] for 60°C InP Etch|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots''']

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''OLD 4" configuration: [https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: GaN Etch ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''

* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.

* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]

[[File:GaN SPC.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279|219x219px]]OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]
==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning
*''[https://wiki.nanofab.ucsb.edu/w/images/d/d1/GaAs_Etch_Ver3_Recipe_Finalized_120925.pdf Std GaAs Etch - Cl2/N2 - 30C Etch Characterization] - F. Foong, 2025-12-10''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

ICP Etching Recipes

2026-03-03T00:16:58Z

John d: linked to recipe sections on this page.

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''[[ICP Etching Recipes#Process Control Data (DSEiii)|Process Control Data below]]''' - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==Analogous FICP Recipes (DSEiii)==
These recipes were developed to serve as backup processes for the calibrated [[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|'''Fluorine-ICP''']] SiO2 and Si etches [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]].

[https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing FICP to DSE etch processes].

*'''[[ICP Etching Recipes#Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)|Si Etch v1 (⭐️Production)]]'''
*'''[[ICP Etching Recipes#SiO2 Etch (DSEiii)|SiO2 Etch v1 (⭐️Production)]]'''

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with Al2O3 hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}

=== '''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)''' ===
[[File:DSE plot.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281|232x232px]]
* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots''']

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
We have a new wafer-mounting process for through-silicon etching, using the UV-Release Dicing tape. Contact [[Demis D. John|staff]] for more info.
-- [[Demis D. John|Demis]] 2026-02-10

'''NOTE''':
'''DO NOT RUN''' the wax-mounting process without discussing with staff first. The wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer!
''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11

{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
with wax-mounting (small pieces only)
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
**Smooth, Vertical, E.R. uniformity is within 5% on wafer
**Tested with 4" wafers that are ~50% open with UV6 PR
*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Older, alternate Si "shallow/smooth" etch recipe.
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

== SiO2 Etch (DSEiii) ==
These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].
*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
**Vertical/Smooth
**Tested by mounting 1cmx1cm piece with oil on 4" Si

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the [[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|'''Process Control Data below''']] - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

=== Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
[[File:FICP-Si.png|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots''']

==SiO2 Etch Recipes (Fluorine ICP Etcher)==
[[File:FL-ICP_50W_SiO2_etch_with_Ru_Hard_Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|thumb|266x266px|50W SiO2 Etch w/ Ru Hardmask]]
[[File:FL-ICP_200W_SiO2_Etch_with_Ru_Hardmask_-_Ning_Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|thumb|266x266px|200W SiO2 Etch w/ Ru Hardmask (Ning Cao)]]
*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.

=== [//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] ===

* Click above for [http://wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf Full Process Traveler]
** Process written for Sputtered Ru & I-Line GCA Stepper litho
** Can be transferred to ALD Ru or DUV/EBL Litho.

*''Ning Cao & Bill Mitchell, 2019-06''
*''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
*''Etch also works well with PR masking''
*''Chemistry: CHF3/CF4''
*''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
*Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
*50W Bias: ('''recommended''')
**Selectivity to photoresist: 1.10–1.20
**SiO2 selectivity to Ru: 36
**SiO2 etch rate: 263nm/min
**''Smoothest vertical etch for SiO2.''
*200W Bias: (higher etch rate)
**SiO2 selectivity to Ru: 38
**SiO2 etch rate: 471nm/min
*This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
*Updates: Many users have found that SiO2-masking the Ru hardmask results in vastly improved photoresist selectivity, making litho+etch of small features much better.
**Layer stack looks like: SiO2 (or other dielectric target layer to etch) / Ru hardmask / SiO2 hardmask (thin) / Photoresist.
**Typically strip the masks+PR with all dry etching. That means the entire etch process (all etches and strips) can be run ''in situ'' on the Panasonic ICP in a rapid single-tool etch process.
===Process Control: SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
[[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots''']

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===
[[File:SEM Image.png|thumb|New PR Strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Old PR strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**45sec-1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=
'''Panasonic ICP#1 is currently down -''' Use Panasonic ICP#2 instead. Most processes directly transfer with only small change in etch rate. Data kept here for historical purposes only.

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure & Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get on the ''back'' of the carrier wafer or you will get Helium cooling errors.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch, and see their SEM's.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
**''This etch is used in our Process Control weekly cals run by [[Process Group Interns|NanoFab Interns]]. Very stable over time ±5%.''
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

===Process Control: SiO2 Etch with CHF3/CF4 (Panasonic 2)===
[[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|thumb|269x269px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts] for SiO2 etching.|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]''Weekly cal etches of the CF4/CHF3 SiO2 etch, run by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots''']

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*GaAs Etch Cal - ''Noah Dutra & Fatt Foong, 2025-02-12''
**Etch Rates ~1um/min, Selectivity to SiO2 ~ 27:1, Sidewalls ~ 90°
**Etch Rate/Selectivity [https://wiki.nanofab.ucsb.edu/w/images/7/76/GaAs_pressure_experiment.png highly sensitive to pressure] (image credit: Terry Guerrero)
**Cal Sample: ~1cm sample etched mounted with oil onto 150mm Si carrier
**Recipe: 0.5Pa, 100/900W, N2/Cl2=10/20sccm
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf Non-Calibration GaAs Etch Recipes - Panasonic 2 - Cl2N2]

===Process Control: GaAs Etch with N2/Cl2 (Panasonic 2)===
[[File:GaAs Etch ICP2 SPC.png|alt=example ICP2 process control chart|thumb|249x249px|[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for GaAs etching.|link=https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281]]
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=0#gid=0 GaAs Etch with N2/Cl2 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 GaAs Etch with N2/Cl2 - '''Plots''']

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

=== Process Tips ===
* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* InP requires fairly high temperatures for making the Indium products volatile - so going to full-wafers (which are cooler) may requiring the table temperature. We have found that temperatures of ~150⁰C minimum may be required for preventing grassing etc.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==InP Ridge Etch (Oxford ICP Etcher)==
===High-Temp (200°C) InP Etch Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
[[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|thumb|218x218px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for 200°C InP Etch|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

===Low-Temp (60°C) InP Etch Process===
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: Low-Temp (60°C) InP Etch ====
[[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts] for 60°C InP Etch|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots''']

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''OLD 4" configuration: [https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: GaN Etch ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''

* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.

* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]

[[File:GaN SPC.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279|219x219px]]OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]
==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning
*''[https://wiki.nanofab.ucsb.edu/w/images/d/d1/GaAs_Etch_Ver3_Recipe_Finalized_120925.pdf Std GaAs Etch - Cl2/N2 - 30C Etch Characterization] - F. Foong, 2025-12-10''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

ICP Etching Recipes

2026-03-03T00:14:21Z

John d: /* DSEIII_(PlasmaTherm/Deep_Silicon_Etcher) */ copied into new Sio2 and Si recipes sections

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''[[ICP Etching Recipes#Process Control Data (DSEiii)|Process Control Data below]]''' - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==Analogous FICP Recipes (DSEiii)==
Make sure to remove photoresist from edges of wafer. These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].

*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01
**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
**Smooth, Vertical, E.R. uniformity is within 5% on wafer
**Tested with 4" wafers that are ~50% open with UV6 PR
*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01
**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
**Vertical/Smooth
**Tested by mounting 1cmx1cm piece with oil on 4" Si

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with Al2O3 hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}

=== '''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)''' ===
[[File:DSE plot.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281|232x232px]]
* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots''']

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
We have a new wafer-mounting process for through-silicon etching, using the UV-Release Dicing tape. Contact [[Demis D. John|staff]] for more info.
-- [[Demis D. John|Demis]] 2026-02-10

'''NOTE''':
'''DO NOT RUN''' the wax-mounting process without discussing with staff first. The wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer!
''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11

{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
with wax-mounting (small pieces only)
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
**Smooth, Vertical, E.R. uniformity is within 5% on wafer
**Tested with 4" wafers that are ~50% open with UV6 PR
*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Older, alternate Si "shallow/smooth" etch recipe.
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

== SiO2 Etch (DSEiii) ==
These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].
*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
**Vertical/Smooth
**Tested by mounting 1cmx1cm piece with oil on 4" Si

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the [[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|'''Process Control Data below''']] - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

=== Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
[[File:FICP-Si.png|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots''']

==SiO2 Etch Recipes (Fluorine ICP Etcher)==
[[File:FL-ICP_50W_SiO2_etch_with_Ru_Hard_Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|thumb|266x266px|50W SiO2 Etch w/ Ru Hardmask]]
[[File:FL-ICP_200W_SiO2_Etch_with_Ru_Hardmask_-_Ning_Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|thumb|266x266px|200W SiO2 Etch w/ Ru Hardmask (Ning Cao)]]
*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.

=== [//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] ===

* Click above for [http://wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf Full Process Traveler]
** Process written for Sputtered Ru & I-Line GCA Stepper litho
** Can be transferred to ALD Ru or DUV/EBL Litho.

*''Ning Cao & Bill Mitchell, 2019-06''
*''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
*''Etch also works well with PR masking''
*''Chemistry: CHF3/CF4''
*''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
*Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
*50W Bias: ('''recommended''')
**Selectivity to photoresist: 1.10–1.20
**SiO2 selectivity to Ru: 36
**SiO2 etch rate: 263nm/min
**''Smoothest vertical etch for SiO2.''
*200W Bias: (higher etch rate)
**SiO2 selectivity to Ru: 38
**SiO2 etch rate: 471nm/min
*This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
*Updates: Many users have found that SiO2-masking the Ru hardmask results in vastly improved photoresist selectivity, making litho+etch of small features much better.
**Layer stack looks like: SiO2 (or other dielectric target layer to etch) / Ru hardmask / SiO2 hardmask (thin) / Photoresist.
**Typically strip the masks+PR with all dry etching. That means the entire etch process (all etches and strips) can be run ''in situ'' on the Panasonic ICP in a rapid single-tool etch process.
===Process Control: SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
[[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots''']

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===
[[File:SEM Image.png|thumb|New PR Strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Old PR strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**45sec-1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=
'''Panasonic ICP#1 is currently down -''' Use Panasonic ICP#2 instead. Most processes directly transfer with only small change in etch rate. Data kept here for historical purposes only.

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure & Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get on the ''back'' of the carrier wafer or you will get Helium cooling errors.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch, and see their SEM's.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
**''This etch is used in our Process Control weekly cals run by [[Process Group Interns|NanoFab Interns]]. Very stable over time ±5%.''
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

===Process Control: SiO2 Etch with CHF3/CF4 (Panasonic 2)===
[[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|thumb|269x269px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts] for SiO2 etching.|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]''Weekly cal etches of the CF4/CHF3 SiO2 etch, run by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots''']

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*GaAs Etch Cal - ''Noah Dutra & Fatt Foong, 2025-02-12''
**Etch Rates ~1um/min, Selectivity to SiO2 ~ 27:1, Sidewalls ~ 90°
**Etch Rate/Selectivity [https://wiki.nanofab.ucsb.edu/w/images/7/76/GaAs_pressure_experiment.png highly sensitive to pressure] (image credit: Terry Guerrero)
**Cal Sample: ~1cm sample etched mounted with oil onto 150mm Si carrier
**Recipe: 0.5Pa, 100/900W, N2/Cl2=10/20sccm
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf Non-Calibration GaAs Etch Recipes - Panasonic 2 - Cl2N2]

===Process Control: GaAs Etch with N2/Cl2 (Panasonic 2)===
[[File:GaAs Etch ICP2 SPC.png|alt=example ICP2 process control chart|thumb|249x249px|[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for GaAs etching.|link=https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281]]
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=0#gid=0 GaAs Etch with N2/Cl2 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 GaAs Etch with N2/Cl2 - '''Plots''']

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

=== Process Tips ===
* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* InP requires fairly high temperatures for making the Indium products volatile - so going to full-wafers (which are cooler) may requiring the table temperature. We have found that temperatures of ~150⁰C minimum may be required for preventing grassing etc.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==InP Ridge Etch (Oxford ICP Etcher)==
===High-Temp (200°C) InP Etch Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
[[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|thumb|218x218px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for 200°C InP Etch|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

===Low-Temp (60°C) InP Etch Process===
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: Low-Temp (60°C) InP Etch ====
[[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts] for 60°C InP Etch|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots''']

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''OLD 4" configuration: [https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: GaN Etch ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''

* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.

* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]

[[File:GaN SPC.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279|219x219px]]OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]
==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning
*''[https://wiki.nanofab.ucsb.edu/w/images/d/d1/GaAs_Etch_Ver3_Recipe_Finalized_120925.pdf Std GaAs Etch - Cl2/N2 - 30C Etch Characterization] - F. Foong, 2025-12-10''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

Stepper 3 (ASML DUV)

2026-02-27T23:01:58Z

John d: /* Operating Procedures */ link to calibrate lithoj rpocess

{{tool|{{PAGENAME}}
|picture=ASML.jpg
|type = Lithography
|super= Demis D. John
|location=Bay 7
|description = Deep-UV Stepper Photolithography
|model = PAS 5500/300
|manufacturer = [http://www.asml.com ASML]
|ToolType = Lithography
|recipe = Lithography
|materials =
|toolid=51
}}
{{ToolActions
|toolid = 51
|ProcessControlURL = Stepper_3_(ASML_DUV)#Process_Control_Data
|ProceduresURL =
|TrainingURL = Stepper_3_(ASML_DUV)#Training_Procedure
}}

==About==

===General Capabilities/Overview===
The ASML 5500 stepper is a 248nm (KrF) DUV stepper for imaging dense features down to below 200nm and isolated line structures down to below 150nm (with effort). 300nm+ features are relatively "easy" to resolve. Layer-to-layer overlay accuracy is better than 30nm.

The system is configured for 4” wafers. The system is designed for high throughput, so shooting multiple 4" wafers is extremely fast, typically minutes per wafer, but any size other than 4-inch is difficult to work with (see below for more info). Additionally, exposure jobs are highly programmable, allowing for very flexible exposures of multiple aligned patterns from multiple masks/reticles in a single session, allowing for process optimization of large vs. small features in a single lithography.

The full field useable exposure area is limited to the intersection of a 31mm diameter circle and a rectangle of dimensions 22mm x 27mm. Users have stitched multiple photomasks together with success. See the [[Stepper 3 (ASML DUV)#Mask Design and CAD files|Mask Making Guidelines page]] for more info on exposure field sizes and how to order your mask plates.

==== Stepper Tutorial ====
If you are not familiar with how Stepper Litho is different from our lithography methods, please review this short tutorial:

[https://wiki.nanofab.ucsb.edu/w/images/c/cb/Demis_D_John_-_Stepper_Reticle_Layout_vs_Wafer_Layout.pdf '''Stepper Reticle Layout vs Wafer Layout (Demis D. John)'''] - Explains the following:

* That a Stepper mask layout is very different than other litho systems.
* That a Stepper mask can have ''many'' designs, and flexibly pattern the wafer with combos of designs.
[[Stepper Reticle Layout (Advanced) - Complex Experiments and Variations|'''Stepper Reticle Layout (Advanced) - Complex Experiments and Variations''']]

* If you need many design variations on your wafer, this is an efficient way to utilize stepper reticles.

===Photoresists Available===
''See [https://wiki.nanotech.ucsb.edu/w/index.php?title=Lithography_Recipes#Photolithography_Recipes PhotoLith. Recipes] for full process info & links to PR datasheets.''

*UV210-0.3 - Positive: 300nm nominal thickness
*UV6-0.8 - Positive: 800nm nominal thickness
*UV26-2.5 - Positive: 2.5um nominal thickness
*UVN2300-0.5 - Negative: 500nm nominal thickness

*DUV42P-6/DS-K101 - Bottom Anti-Reflective Coatings “BARC”
*PMGI/LOL1000/LOL2000 - Underlayers

AZ300MIF Developer for all processes

Many of these DUV PR's are also able to be exposed with [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]].

===Part Size Limits===
With staff support, mounted pieces down to 14mm in size can be exposed using a 4” wafer as a carrier. Flatness will typically be worse in this situation, so small <<500nm features will usually have bad uniformity across the mounted part due to focus variations. Edge bead on irregular pieces (eg. quarter-wafers/squares) will significantly reduce yield/uniformity.

Multi-layer Alignment on mounted parts is particularly difficult, requiring either semi-permanent mounting to the carrier (eg. BCB, SU8 etc.) or significant difficulty/effort to re-align the part to the carrier wafer on each lithography (≤100µm re-mounting accuracy needed).

At this time the maximum wafer size is 4” (100mm) wafers with SEMI standard wafer flat (not Notch).

===Service Provider===

*[http://www.asml.com ASML] - ASML performs quarterly periodic maintenance and provides on-demand support.

==Process Information==

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Lithography_Recipes#Photolithography_Recipes '''Process Recipes Page'''] '''> "Stepper 3"''' - ''Established recipes and corresponding linewidths, photoresists etc.''
*Sample size: 100 mm wafers with SEMI std. major flat
**''Piece-parts process is possible but difficult - contact supervisor for info''
*Alignment Accuracy: < 50 nm
*Minimum Feature Size: ≤150 nm isolated lines, ≤200 nm dense patterns
**''To achieve ≤200nm features with high uniformity, we recommend wafers with total thickness variation (TTV) ≤5µm, and designing your CAD with a smaller Image Size for the high-res. feature''.
*Wafer Thickness: Minimum ≈ 200µm, Maximum ≈ 1.1 mm
*Maximum Dose: ~100mJ
**''Non-chemically amplified EBL resists are not permissible due to this limit.''

===Maximum Wafer Bow===
Measured over 90mm on the [[Film Stress (Tencor Flexus)|Tencor Flexus]]

*'''Do not run wafers with bow values higher than the following values''', contact supervisor for advice if needed.
*Silicon wafers (~550µm thick): 100 µm will likely fail.
*Sapphire (less pliable), ≥60µm bow will intermittently fail - DO NOT RUN
**This applies especially for GaN-on-Sapphire, which often have high wafer bow.
*''Near these values, and you may lose the wafer inside the machine due to wafer vacuum error - DO NOT RUN if unsure.''
*''Substrate material and substrate thickness affect this limit - please contact [[Demis D. John|supervisor]] for advice.''
*You can '''stress-compensate''' wafers to reduce the wafer bow, eg. by depositing on the back side of the wafer. If your wafer is concave down, then depositing a ''compressive'' film on the back will reduce its curvature. Coat the backside of the wafer with compressive PECVD SiO2 or [[Sputtering Recipes#Si3N4 deposition .28IBD.29|IBD SiN]], or other compressive films for concave-down bow.

==Operating Procedures==
'''All procedures are access-restricted only to authorized users with a UCSB NetID (''YourNetID''@ucsb.edu), by vendor request.
Please contact [[Demis D. John|supervisor]] for access/training.

=== [https://drive.google.com/drive/folders/1U9-03qU2htQp_5x39LNq-mn5Q3vXXLDf?usp=drive_link ASML Operating Procedures] ===
* Access-restricted google drive folder of PAS 5500/300 operating procedures.

=== [https://docs.google.com/document/d/1T6Bc7A6YjxFyxMR9n35CCsmtJVRQen3m371Vd_Q9dlY/edit?usp=drive_link Troubleshooting & Error Recovery] ===
* common issues and fixes (access-restricted)

=== [[Stepper 3 (ASML DUV)#Calibrating your Lithography Process|Calibrate Your Litho Process]] ===
See this section for the basics on how to do this: [[Stepper 3 (ASML DUV)#Calibrating your Lithography Process|Stepper 3 (ASML DUV) > Recipes > Calibrating your Lithography Process]]

=== [https://docs.google.com/document/d/17jPek8P_SF1qRADS09ApoDgUiB_v0NFJsIVpkL-Kdag/edit#heading=h.fmorc9eu8hfz Stepper #3 Training/Reference Videos] ===
* The above linked videos provide bookmarked quick-reference to various tool procedures & programming.
**''To access, you must log in with your UCSB NetID, formatted like'' MyNetID''@ucsb.edu'' ''- this is a Google login!''
**''Please contact the [[Demis D. John|tool supervisor]] if you need access.''
**[[UCSB NetID Login Troubleshooting|'''''Trouble accessing?''''' ''Please click here for tips.'']]
**'''''You are NOT authorized''' to use this tool until a tool supervisor authorizes you!''

===Training Procedure===
To get access to this tool, please do the following:

#Email the [[Demis D. John|supervisor]] for access to the training materials. Please provide your UCSB NetID.
#Study the [https://docs.google.com/document/d/17jPek8P_SF1qRADS09ApoDgUiB_v0NFJsIVpkL-Kdag/edit#heading=h.fmorc9eu8hfz training videos].
##If you are a technician and will never program jobs, only Part 1 is necessary.
#"Shadow" someone in your group who uses the machine, until you are completely comfortable with (1) wafer cleaning (critical), (2) reticle load/unload and (3) running a pre-made job.
#When you are ready, request a hands-on check-off on SignupMonkey by clicking this button:{{ToolTrainingButton|toolid=51}}

==Design Tools==

===Mask Design and CAD files===

*[https://wiki.nanofab.ucsb.edu/wiki/Stepper_Mask-Making_Guidelines_(Generic) '''Stepper Mask-Making Guidelines'''] - Info needed to design and order a reticle for our Stepper systems. This is minimal unrestricted info that is viewable without additional paperwork.
*'''[https://docs.google.com/document/d/1b9YT11RPsl-UlLvN74hrQvG01OcYDL16r6I5lPOlBEo/edit?usp=sharing ASML-specific Mask Making Guidelines (Private)]''' - More detailed info to design and order a reticle for this specific ASML system.
**''Access is restricted to trained users only by ASML's requirement - please contact [[Demis D. John|tool supervisor]] for access.''
*'''Tutorial: [https://wiki.nanofab.ucsb.edu/w/images/c/cb/Demis_D_John_-_Stepper_Reticle_Layout_vs_Wafer_Layout.pdf Stepper Reticle Layout vs Wafer Layout (Demis D. John)]''' ''-'' explains how Stepper mask layout is very different than other litho systems.
*'''Tutorial: [[Stepper Reticle Layout (Advanced) - Complex Experiments and Variations]]''' - If you need many design variations on your wafer.

*See the [[Calculators + Utilities#CAD%20Files%20.26%20Templates|Calculators + Utilities > '''CAD Files & Templates''']] page for other useful CAD files, such as overlay verniers, vented fonts etc.

===[[ASML Stepper 3 - UCSB Test Reticles|UCSB Photomasks Available]]===

*Click the above link to view our available masks & images
*Photomasks available with various patterns such as
**Alignment Markers (contact, EBL)
**Resolution Testing
**Various line/space (0.150µm → 50µm),
** Alignment markers modifications (dicing lane marks, rotated marks)
** Full-field exposure,
** 1mm boxes for LaserMonitor or Filmetrics/Dektak etc.

=== Optical Proximity Correction (OPC): Going below the resolution limit ===

* [https://drive.google.com/file/d/1Ivjq8_jd_1msA7Ap7ellArTZZ3soSLPe/view?usp=sharing '''OPC General information and detailed investigation of lateral DBR patterns'''] - Detailed info and investigation of OPC, use case examples, performance comparisons, how to order etc. By [[Gopikrishnan G M|Gopikrishana G. Meena]].
* UCSB Nanofab users have access to order photomask plates with [https://en.wikipedia.org/wiki/Optical_proximity_correction OPC] corrections applied to the patterns to enable accurate lithography on high-resolution structures, with a single photomask order.
* Model-based, "feed-forward" OPC - meaning you order only one photomask, no "feed-''back''", nor 2nd mask required.
* [https://www.photronics.com/ Photronics Inc.] - OPC corrected mask plate provider for UCSB Nanofab users.
** Contact [[Demis D. John|Demis]] for quotes.
** Photronics Inc. is collaborating with the Nanofab to develop + provide OPC correction to UCSB researchers.
** Photronics' team has built a model-based OPC correction for our system, which appears to work for multiple photoresists (UV6-positive and UVN-negative tested so far).
** Current OPC rules are for: ''Conventional (circular) Illumination / NA=0.57 / sigma=0.75''
{| class="wikitable"
!OPC Mask Correction
! colspan="2" |Positive Resist: UV6-0.8 - Lateral Waveguide Gratings with/without OPC on same photomask.
Collaboration with photomask vendor [https://www.photronics.com/ Photronics Inc.]
|-
! style="text-align:center;" |[[File:ASML OPC CAD.png|191x191px]]
! style="text-align:center;" |[[File:ASML SEM DBR without OPC.png|162x162px]]
! style="text-align:center;" |[[File:ASML SEM DBR With OPC .png|166x166px]]
|-
|OPC applies serifs to your patterns.
|The ''Best'' exposure without OPC corrections; '''doesn't meet device criteria'''. Would require ordering a 2nd mask to correct.
|With OPC applied to the patterns, the '''device criteria (length and spacing) are met on 1st mask rev''', and process window is possibly wider.
|}
{| class="wikitable"
! colspan="2" |Negative PR: UVN30. ASML DUV with and without same MB-OPC, on the same photomask, applied to a Meta-optic.
Fabricated by [https://scholar.google.com/citations?user=9xqXl7sAAAAJ&hl=en Skyler Palatnik], [https://web.physics.ucsb.edu/~maxmb/ Prof. Max Millar-Blanchaer's group] in collaboration with photomask vendor [https://www.photronics.com/ Photronics Inc.]
|-
| style="text-align:center;" |[[File:ASML_OPC_-_Skyler_Palatnik_060224_PR_vtxHvP_15mJOPC_3.png|alt=SEM image of Meta-optic center|300x300px]]
| style="text-align:center;" |[[File:ASML_OPC_-_Skyler_Palatnik_060224_PR_vtxHvP_23mJ_NO_OPC_1.png|alt=SEM of No-OPC meta-optic center|300x300px]]
|-
|'''''With OPC''' applied to mask pattern. Squares and circles with small gaps+small posts are resolved in one exposure.''
|'''''Without OPC''' (standard photomask process). No combination of focus/dose can achieve desired results - "best" result shown here.''
|}

=== [[ASML Stepper 3 - Job Creator|JobCreator]]: Python Scripting ===

* Create ASML Job files using python. Click the above [[ASML Stepper 3 - Job Creator|link for more info]].

==Recipes==

* '''[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Recipes > Lithography > Stepper Recipes > Stepper #3]]''' - starting processes for various DUV photoresists, including Dose/Focus values.

=== Calibrating your Lithography Process ===
To calibrate your own Litho processes, you will need to:
* Find a starter litho close to what you need here: [[Stepper Recipes#Stepper 3 .28ASML DUV.29|Recipes > Lithography > Stepper Recipes > Stepper #3]]
* [https://docs.google.com/document/d/1_QIsYtew1uDlbUJCniApLz9_TYG2izwTxNpmoCbSuLI/edit?usp=drive_link Run your own Focus Exposure Matrix with] [https://docs.google.com/document/d/1_QIsYtew1uDlbUJCniApLz9_TYG2izwTxNpmoCbSuLI/edit?usp=drive_link this procedure] (private) - shows how to do an FEM on the ASML software
* [[Lithography Calibration - Analyzing a Focus-Exposure Matrix]] - how to analyze an FEM & choose the best process

==Process Control Data==

*''The Process Group regularly measures the lithography Critical Dimension ("CD") and Wafer-stage Particulate Contamination for this tool, using a sensitive lithography process that will reveal small changes in Dose repeatability and wafer flatness.''
*[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0 '''Data Table for CD Uniformity and Particulate Contamination''']
*[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281 '''Plots of CD Repeatability''']

{|
|[[File:ASML CD Cals - Example Table.jpg|alt=ASML CD Calibration data - Screenshot of Table|none|thumb|300x300px|''Example of Data Table with SEM's of 320nm features. [https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0 Click for full data table.]''|link=https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0]]
|[[File:ASML CD Cals - Example Plot.jpg|alt=ASML CD Calibration Data - Screenshot of SPC Plot|none|thumb|''Example SPC Chart - Measured Critical Dimension "CD" versus Date.'' ''[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281 Click for current charts.]''|link=https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281]]
|}

Stepper 3 (ASML DUV)

2026-02-27T23:00:16Z

John d: /* Operating Procedures */ moved calibrate litho process to recipes

{{tool|{{PAGENAME}}
|picture=ASML.jpg
|type = Lithography
|super= Demis D. John
|location=Bay 7
|description = Deep-UV Stepper Photolithography
|model = PAS 5500/300
|manufacturer = [http://www.asml.com ASML]
|ToolType = Lithography
|recipe = Lithography
|materials =
|toolid=51
}}
{{ToolActions
|toolid = 51
|ProcessControlURL = Stepper_3_(ASML_DUV)#Process_Control_Data
|ProceduresURL =
|TrainingURL = Stepper_3_(ASML_DUV)#Training_Procedure
}}

==About==

===General Capabilities/Overview===
The ASML 5500 stepper is a 248nm (KrF) DUV stepper for imaging dense features down to below 200nm and isolated line structures down to below 150nm (with effort). 300nm+ features are relatively "easy" to resolve. Layer-to-layer overlay accuracy is better than 30nm.

The system is configured for 4” wafers. The system is designed for high throughput, so shooting multiple 4" wafers is extremely fast, typically minutes per wafer, but any size other than 4-inch is difficult to work with (see below for more info). Additionally, exposure jobs are highly programmable, allowing for very flexible exposures of multiple aligned patterns from multiple masks/reticles in a single session, allowing for process optimization of large vs. small features in a single lithography.

The full field useable exposure area is limited to the intersection of a 31mm diameter circle and a rectangle of dimensions 22mm x 27mm. Users have stitched multiple photomasks together with success. See the [[Stepper 3 (ASML DUV)#Mask Design and CAD files|Mask Making Guidelines page]] for more info on exposure field sizes and how to order your mask plates.

==== Stepper Tutorial ====
If you are not familiar with how Stepper Litho is different from our lithography methods, please review this short tutorial:

[https://wiki.nanofab.ucsb.edu/w/images/c/cb/Demis_D_John_-_Stepper_Reticle_Layout_vs_Wafer_Layout.pdf '''Stepper Reticle Layout vs Wafer Layout (Demis D. John)'''] - Explains the following:

* That a Stepper mask layout is very different than other litho systems.
* That a Stepper mask can have ''many'' designs, and flexibly pattern the wafer with combos of designs.
[[Stepper Reticle Layout (Advanced) - Complex Experiments and Variations|'''Stepper Reticle Layout (Advanced) - Complex Experiments and Variations''']]

* If you need many design variations on your wafer, this is an efficient way to utilize stepper reticles.

===Photoresists Available===
''See [https://wiki.nanotech.ucsb.edu/w/index.php?title=Lithography_Recipes#Photolithography_Recipes PhotoLith. Recipes] for full process info & links to PR datasheets.''

*UV210-0.3 - Positive: 300nm nominal thickness
*UV6-0.8 - Positive: 800nm nominal thickness
*UV26-2.5 - Positive: 2.5um nominal thickness
*UVN2300-0.5 - Negative: 500nm nominal thickness

*DUV42P-6/DS-K101 - Bottom Anti-Reflective Coatings “BARC”
*PMGI/LOL1000/LOL2000 - Underlayers

AZ300MIF Developer for all processes

Many of these DUV PR's are also able to be exposed with [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]].

===Part Size Limits===
With staff support, mounted pieces down to 14mm in size can be exposed using a 4” wafer as a carrier. Flatness will typically be worse in this situation, so small <<500nm features will usually have bad uniformity across the mounted part due to focus variations. Edge bead on irregular pieces (eg. quarter-wafers/squares) will significantly reduce yield/uniformity.

Multi-layer Alignment on mounted parts is particularly difficult, requiring either semi-permanent mounting to the carrier (eg. BCB, SU8 etc.) or significant difficulty/effort to re-align the part to the carrier wafer on each lithography (≤100µm re-mounting accuracy needed).

At this time the maximum wafer size is 4” (100mm) wafers with SEMI standard wafer flat (not Notch).

===Service Provider===

*[http://www.asml.com ASML] - ASML performs quarterly periodic maintenance and provides on-demand support.

==Process Information==

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Lithography_Recipes#Photolithography_Recipes '''Process Recipes Page'''] '''> "Stepper 3"''' - ''Established recipes and corresponding linewidths, photoresists etc.''
*Sample size: 100 mm wafers with SEMI std. major flat
**''Piece-parts process is possible but difficult - contact supervisor for info''
*Alignment Accuracy: < 50 nm
*Minimum Feature Size: ≤150 nm isolated lines, ≤200 nm dense patterns
**''To achieve ≤200nm features with high uniformity, we recommend wafers with total thickness variation (TTV) ≤5µm, and designing your CAD with a smaller Image Size for the high-res. feature''.
*Wafer Thickness: Minimum ≈ 200µm, Maximum ≈ 1.1 mm
*Maximum Dose: ~100mJ
**''Non-chemically amplified EBL resists are not permissible due to this limit.''

===Maximum Wafer Bow===
Measured over 90mm on the [[Film Stress (Tencor Flexus)|Tencor Flexus]]

*'''Do not run wafers with bow values higher than the following values''', contact supervisor for advice if needed.
*Silicon wafers (~550µm thick): 100 µm will likely fail.
*Sapphire (less pliable), ≥60µm bow will intermittently fail - DO NOT RUN
**This applies especially for GaN-on-Sapphire, which often have high wafer bow.
*''Near these values, and you may lose the wafer inside the machine due to wafer vacuum error - DO NOT RUN if unsure.''
*''Substrate material and substrate thickness affect this limit - please contact [[Demis D. John|supervisor]] for advice.''
*You can '''stress-compensate''' wafers to reduce the wafer bow, eg. by depositing on the back side of the wafer. If your wafer is concave down, then depositing a ''compressive'' film on the back will reduce its curvature. Coat the backside of the wafer with compressive PECVD SiO2 or [[Sputtering Recipes#Si3N4 deposition .28IBD.29|IBD SiN]], or other compressive films for concave-down bow.

==Operating Procedures==
'''All procedures are access-restricted only to authorized users with a UCSB NetID (''YourNetID''@ucsb.edu), by vendor request.
Please contact [[Demis D. John|supervisor]] for access/training.

=== [https://drive.google.com/drive/folders/1U9-03qU2htQp_5x39LNq-mn5Q3vXXLDf?usp=drive_link ASML Operating Procedures] ===
* Access-restricted google drive folder of PAS 5500/300 operating procedures.

=== [https://docs.google.com/document/d/1T6Bc7A6YjxFyxMR9n35CCsmtJVRQen3m371Vd_Q9dlY/edit?usp=drive_link Troubleshooting & Error Recovery] ===
* common issues and fixes (access-restricted)

=== [https://docs.google.com/document/d/17jPek8P_SF1qRADS09ApoDgUiB_v0NFJsIVpkL-Kdag/edit#heading=h.fmorc9eu8hfz Stepper #3 Training/Reference Videos] ===
* The above linked videos provide bookmarked quick-reference to various tool procedures & programming.
**''To access, you must log in with your UCSB NetID, formatted like'' MyNetID''@ucsb.edu'' ''- this is a Google login!''
**''Please contact the [[Demis D. John|tool supervisor]] if you need access.''
**[[UCSB NetID Login Troubleshooting|'''''Trouble accessing?''''' ''Please click here for tips.'']]
**'''''You are NOT authorized''' to use this tool until a tool supervisor authorizes you!''

===Training Procedure===
To get access to this tool, please do the following:

#Email the [[Demis D. John|supervisor]] for access to the training materials. Please provide your UCSB NetID.
#Study the [https://docs.google.com/document/d/17jPek8P_SF1qRADS09ApoDgUiB_v0NFJsIVpkL-Kdag/edit#heading=h.fmorc9eu8hfz training videos].
##If you are a technician and will never program jobs, only Part 1 is necessary.
#"Shadow" someone in your group who uses the machine, until you are completely comfortable with (1) wafer cleaning (critical), (2) reticle load/unload and (3) running a pre-made job.
#When you are ready, request a hands-on check-off on SignupMonkey by clicking this button:{{ToolTrainingButton|toolid=51}}

==Design Tools==

===Mask Design and CAD files===

*[https://wiki.nanofab.ucsb.edu/wiki/Stepper_Mask-Making_Guidelines_(Generic) '''Stepper Mask-Making Guidelines'''] - Info needed to design and order a reticle for our Stepper systems. This is minimal unrestricted info that is viewable without additional paperwork.
*'''[https://docs.google.com/document/d/1b9YT11RPsl-UlLvN74hrQvG01OcYDL16r6I5lPOlBEo/edit?usp=sharing ASML-specific Mask Making Guidelines (Private)]''' - More detailed info to design and order a reticle for this specific ASML system.
**''Access is restricted to trained users only by ASML's requirement - please contact [[Demis D. John|tool supervisor]] for access.''
*'''Tutorial: [https://wiki.nanofab.ucsb.edu/w/images/c/cb/Demis_D_John_-_Stepper_Reticle_Layout_vs_Wafer_Layout.pdf Stepper Reticle Layout vs Wafer Layout (Demis D. John)]''' ''-'' explains how Stepper mask layout is very different than other litho systems.
*'''Tutorial: [[Stepper Reticle Layout (Advanced) - Complex Experiments and Variations]]''' - If you need many design variations on your wafer.

*See the [[Calculators + Utilities#CAD%20Files%20.26%20Templates|Calculators + Utilities > '''CAD Files & Templates''']] page for other useful CAD files, such as overlay verniers, vented fonts etc.

===[[ASML Stepper 3 - UCSB Test Reticles|UCSB Photomasks Available]]===

*Click the above link to view our available masks & images
*Photomasks available with various patterns such as
**Alignment Markers (contact, EBL)
**Resolution Testing
**Various line/space (0.150µm → 50µm),
** Alignment markers modifications (dicing lane marks, rotated marks)
** Full-field exposure,
** 1mm boxes for LaserMonitor or Filmetrics/Dektak etc.

=== Optical Proximity Correction (OPC): Going below the resolution limit ===

* [https://drive.google.com/file/d/1Ivjq8_jd_1msA7Ap7ellArTZZ3soSLPe/view?usp=sharing '''OPC General information and detailed investigation of lateral DBR patterns'''] - Detailed info and investigation of OPC, use case examples, performance comparisons, how to order etc. By [[Gopikrishnan G M|Gopikrishana G. Meena]].
* UCSB Nanofab users have access to order photomask plates with [https://en.wikipedia.org/wiki/Optical_proximity_correction OPC] corrections applied to the patterns to enable accurate lithography on high-resolution structures, with a single photomask order.
* Model-based, "feed-forward" OPC - meaning you order only one photomask, no "feed-''back''", nor 2nd mask required.
* [https://www.photronics.com/ Photronics Inc.] - OPC corrected mask plate provider for UCSB Nanofab users.
** Contact [[Demis D. John|Demis]] for quotes.
** Photronics Inc. is collaborating with the Nanofab to develop + provide OPC correction to UCSB researchers.
** Photronics' team has built a model-based OPC correction for our system, which appears to work for multiple photoresists (UV6-positive and UVN-negative tested so far).
** Current OPC rules are for: ''Conventional (circular) Illumination / NA=0.57 / sigma=0.75''
{| class="wikitable"
!OPC Mask Correction
! colspan="2" |Positive Resist: UV6-0.8 - Lateral Waveguide Gratings with/without OPC on same photomask.
Collaboration with photomask vendor [https://www.photronics.com/ Photronics Inc.]
|-
! style="text-align:center;" |[[File:ASML OPC CAD.png|191x191px]]
! style="text-align:center;" |[[File:ASML SEM DBR without OPC.png|162x162px]]
! style="text-align:center;" |[[File:ASML SEM DBR With OPC .png|166x166px]]
|-
|OPC applies serifs to your patterns.
|The ''Best'' exposure without OPC corrections; '''doesn't meet device criteria'''. Would require ordering a 2nd mask to correct.
|With OPC applied to the patterns, the '''device criteria (length and spacing) are met on 1st mask rev''', and process window is possibly wider.
|}
{| class="wikitable"
! colspan="2" |Negative PR: UVN30. ASML DUV with and without same MB-OPC, on the same photomask, applied to a Meta-optic.
Fabricated by [https://scholar.google.com/citations?user=9xqXl7sAAAAJ&hl=en Skyler Palatnik], [https://web.physics.ucsb.edu/~maxmb/ Prof. Max Millar-Blanchaer's group] in collaboration with photomask vendor [https://www.photronics.com/ Photronics Inc.]
|-
| style="text-align:center;" |[[File:ASML_OPC_-_Skyler_Palatnik_060224_PR_vtxHvP_15mJOPC_3.png|alt=SEM image of Meta-optic center|300x300px]]
| style="text-align:center;" |[[File:ASML_OPC_-_Skyler_Palatnik_060224_PR_vtxHvP_23mJ_NO_OPC_1.png|alt=SEM of No-OPC meta-optic center|300x300px]]
|-
|'''''With OPC''' applied to mask pattern. Squares and circles with small gaps+small posts are resolved in one exposure.''
|'''''Without OPC''' (standard photomask process). No combination of focus/dose can achieve desired results - "best" result shown here.''
|}

=== [[ASML Stepper 3 - Job Creator|JobCreator]]: Python Scripting ===

* Create ASML Job files using python. Click the above [[ASML Stepper 3 - Job Creator|link for more info]].

==Recipes==

* '''[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Recipes > Lithography > Stepper Recipes > Stepper #3]]''' - starting processes for various DUV photoresists, including Dose/Focus values.

=== Calibrating your Lithography Process ===
To calibrate your own Litho processes, you will need to:
* Find a starter litho close to what you need here: [[Stepper Recipes#Stepper 3 .28ASML DUV.29|Recipes > Lithography > Stepper Recipes > Stepper #3]]
* [https://docs.google.com/document/d/1_QIsYtew1uDlbUJCniApLz9_TYG2izwTxNpmoCbSuLI/edit?usp=drive_link Run your own Focus Exposure Matrix with] [https://docs.google.com/document/d/1_QIsYtew1uDlbUJCniApLz9_TYG2izwTxNpmoCbSuLI/edit?usp=drive_link this procedure] (private) - shows how to do an FEM on the ASML software
* [[Lithography Calibration - Analyzing a Focus-Exposure Matrix]] - how to analyze an FEM & choose the best process

==Process Control Data==

*''The Process Group regularly measures the lithography Critical Dimension ("CD") and Wafer-stage Particulate Contamination for this tool, using a sensitive lithography process that will reveal small changes in Dose repeatability and wafer flatness.''
*[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0 '''Data Table for CD Uniformity and Particulate Contamination''']
*[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281 '''Plots of CD Repeatability''']

{|
|[[File:ASML CD Cals - Example Table.jpg|alt=ASML CD Calibration data - Screenshot of Table|none|thumb|300x300px|''Example of Data Table with SEM's of 320nm features. [https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0 Click for full data table.]''|link=https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0]]
|[[File:ASML CD Cals - Example Plot.jpg|alt=ASML CD Calibration Data - Screenshot of SPC Plot|none|thumb|''Example SPC Chart - Measured Critical Dimension "CD" versus Date.'' ''[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281 Click for current charts.]''|link=https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281]]
|}

ASML Stepper 3 - UCSB Test Reticles

2026-02-26T06:15:16Z

John d:

== Other Masks and Images ==
We have various patterns on other plates, such as:

* various line/space,
* alignment markers modifications,
* full-field exposure,
* 1mm boxes

See this document for programming info:

[https://docs.google.com/document/d/1sNfphnUfw0k9v7HkZGNpgm5siRxQiU6SCPqIY13mD2w/edit?tab=t.0 '''<big>UCSB Masks and Images for ASML</big>''']

* These are inside the Secure Google Drive folder, you will need to login with your UCSBNetID to access. Ask the [[Demis D. John|Supervisor]] for access.
* Remember your UCSB NetID is a Google Login, formatted as '''''MyNetID'''@ucsb.edu''. If you are trained on the tool, you already have access using this UCSB NetID login.

== Alignment Marks for other systems, other patterns ==

=== Reticle ID: "'''UCSBMARKS26'''" ===
This reticle is always installed in the system, in the "System Reticles" Box #1.

Contains many alignment marks, for as many litho systems in the Nanofab as possible. Also edge-bead removal 1cm field, dicing guides, 1mm "boxes" for Laser Monitoring, verniers etc.

See the GDS File & Programming Params in the [https://drive.google.com/drive/folders/1nZhD1lcizLurOxHx1gKKNvAy05SUGXOo?usp=drive_link UCSB Masks Google Drive] (login via UCSB NetID)
{| class="wikitable"
!Image ID
! colspan="2" |Image Size
(Wafer, mm)
! colspan="2" |Image Shift
(Wafer, mm)
!Notes/Description
!Schematics
|-
!
!X
!Y
!X
!Y
!
!
|-
| colspan="7" |
==== Alignment Markers ====
|-
|Square_30p5
|0.030500
|0.030500
| -4.000000
| -1.000000
|
|
|-
|RaithMark_20um
|0.020000
|0.020000
| -4.000000
| -4.000000
|
|
|-
|MLA_Align
|0.700000
|0.700000
| -4.000000
|10.500000
|
|
|-
|GCA_Align
|0.350000
|0.150000
| -4.000000
|9.000000
|Coord is center to GCA mark. Center of DFAS mark is +0.200mm to the right.
|White is Chrome, Pattern is Clear[[File:Stepper align - Screen Shot 2018-07-23 at 11.24.31 AM.png|frameless|213x213px]]
[[Media:GCA stepper align.gds|CAD File (GDS):GCA_stepper_align.gds]]
|-
|Contact_AlignLyr2
|0.300000
|0.300000
| -4.000000
| -5.500000
|
|
|-
| colspan="7" |
==== Open Squares of various sizes ====
|-
|Square_100um
|0.100000
|0.100000
|7.500000
|12.000000
|
|
|-
|Square_200um
|0.200000
|0.200000
|6.000000
|12.000000
|
|
|-
|Square_500um
|0.500000
|0.500000
|4.500000
|12.000000
|Good for Laser Monitor openings
|
|-
|Square_1mm
|1.000000
|1.000000
|2.500000
|12.000000
|Preferred for Laser Monitor openings
|
|-
|Square_2mm
|2.000000
|2.000000
|0.000000
|12.000000
|
|
|-
|Square_5mm
|5.000000
|5.000000
|8.500000
|8.000000
|
|
|-
|Square_10mm
|10.000000
|10.000000
|6.000000
| -5.000000
|Good for Edge-Bead Exposure
|
|}

==== Other available Images ====
More patterns can be found on the OAS file and the Excel Sheet of ASML Programming Parameters

([https://drive.google.com/drive/folders/1nZhD1lcizLurOxHx1gKKNvAy05SUGXOo?usp=drive_link see gDrive folder here] - requires UCSB NetID), such as:

* Same alignment marks as above, but with X/Y Vernier alignment measurements
* Layer-2 Vernier (to match the above verniers)
* Dicing guides in X & Y
* ASML PM Marks rotated by 90°, 180° and 270°
* Calibration patterns used in Nanofab LithoCals and EtchCals, such as
** Hex array of holes at 250nm diam / 250nm gap
** Hex array of holes at 400nm diam / 300nm gap (ASML LithoCals)
** 10µm, 1µm, 0.50µm Line/Space (DSE EtchCals)
* Complementary (Layer-2) Alignment Marks for Contact, Inverted marks

=== Reticle ID: "'''UCSB-OPC1'''" ===
This reticle is always installed in the system, in the "System Reticles" Box #1.

The reticle contains alignment markers for various NanoFab lithography systems, along with resolution test structures and patterns for calibrating [https://en.wikipedia.org/wiki/Optical_proximity_correction optical proximity correction] on the system. Some patterns are proprietary to the mask designer, so we can not share the full GDS CAD file.

==== Alignment Markers ====
{| class="wikitable"
!Image ID
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X , Y

(Wafer, mm)
!Notes/Description
!Schematics
|-
|GCA_Align
|0.530000 , 0.140000
| -6.750000 , 9.450000
|ImageShift references the center of the -X- "global" mark.
The <nowiki>==|||</nowiki> "Local" mark is X+200µm to the right

has 1.1mm margin on all sides
|White is Chrome, Pattern is Clear[[File:Stepper align - Screen Shot 2018-07-23 at 11.24.31 AM.png|frameless|213x213px]]
[[Media:GCA stepper align.gds|CAD File (GDS):GCA_stepper_align.gds]]
|-
|JEOL E-Beam Litho Alignment Mark - Positive
|0.900000 , 0.900000
| -6.750000 , -9.450000
|ImageShift is the center coords of the larger "+" mark
Smaller "+" mark is (0.225,-0.225)mm down-right

0.925mm margin on all sides
|White is Chrome, Pattern is Clear
[[File:GlobalMulti POS - Screen Shot 2018-07-23 at 11.17.23 AM.png|frameless|145x145px]]

[[Media:EBL-GlobalMulti POS.gds|CAD File (GDS): EBL-GlobalMulti_POS.gds]]
|-
|JEOL E-Beam Litho Alignment Mark - Negative
|0.710000 , 0.710000
|6.750000 , -9.450000
|ImageShift is the center coords of the larger "+" mark
Smaller "+" mark is (0.225,-0.225)mm down-right

Blank (masked) space on left+top sides

1.0mm margin on all sides
|Striped area is Clear
[[File:GlobalMulti NEG - Screen Shot 2018-07-23 at 11.22.19 AM.png|frameless|115x115px]]

[[Media:EBL-GlobalMulti NEG.gds|CAD File (GDS): EBL-GlobalMulti_NEG.gds]]
|-
|Contact Mark
|0.564000 , 0.564000
|6.750000 , 9.450000
|ImageShift references the center of the contact alignment mark "+"

with 1.1mm margin on all sides

Note the Polarity - will ''expose'' a ~550µm area.
|White is Chrome, Striped area is Clear
[[File:Align Front - Screen Shot 2018-07-23 at 11.32.16 AM.png|frameless|146x146px]]

[[Media:Contact-AlignFront.gds|CAD File (GDS): Contact-AlignFront.gds]]

[[Media:MA6-FrontBack AlignMarks only.gds|Corresponding male/female alignment marks (GDS): MA6-FrontBack_AlignMarks_only.gds]]
|}

==== Resolution Test Charts ====
The Resolution test charts are repeated all across the reticle, in order to test for lens aberrations. You can have the system expose only a single resolution chart, but since they are placed closely together on the reticle, it's very likely that partial shots of adjacent charts will also be exposed.

In addition, the repeating cells allow us to test for the proper [https://en.wikipedia.org/wiki/Optical_proximity_correction optical proximity correction] (OPC) algorithm. The Five <code>Dense_...</code> patterns are for calibrating the OPC algorithm, and are not for user analysis.

'''''Patterned area is CLEAR/transparent.'''''

===== Calibration Chart Layout =====

Cell name is "''UCSB_Cal''", with coordinates below pointing to center of this cell.[[File:UCSB cal - Screen Shot 2018-07-23 at 12.06.58 PM.png|alt=Layout of the repeating calibration charts|none|thumb|512x512px|Layout of the repeating calibration charts]]

===== Resolution Chart =====
"resolution_chart_ORIG" cell in the above. '''''Blue/patterned area is CLEAR/transparent.'''''
[[File:Resolution Chart - Screen Shot 2018-07-23 at 1.36.31 PM.png|alt=Resolution Chart Layout schematic|none|thumb|400x400px|'''"resolution_chart_ORIG":''' Resolution Chart Layout, with res. test from 2.00µm to 0.130µm]]

The ""resolution_chart_OPC" version has an optical proximity correction algorithm applied:
[[File:Resolution chart OPC - Screen Shot 2018-07-23 at 1.40.48 PM.png|alt=OPC'd Resolution Chart Layout schematic|none|thumb|395x395px|'''"resolution_chart_OPC":''' OPC'd Resolution Chart Layout, with res. test from 2.0µm to 0.130µm]]

===== Coords for "resolution_chart" Calibration patterns =====
''Image coords for each of the "resolution_chart_ORIG" cells. You can pick just one of these for shooting a resolution test structure. The purpose of the many different locations is to check for variations due to lens aberrations. You could just choose one near the center of the plate to test your process, or you could choose a chart that is in a similar location as the pattern you're shooting on your mask plate.''

''Note that some portion of the adjacent patterns will likely be exposed as well, due to the patterns not being surrounded by 1mm of chrome. Make sure you set your Cell Size large enough to make sure the bleed-over doesn't overlap with adjacent die.''
{| class="wikitable"
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X

(Wafer, mm)
!Image Shift
Y

(Wafer, mm)
|-
| colspan="3" |Use this for a single Resolution Chart:
|-
|0.605 , 1.005
|0.685000
|1.350000
|-
| colspan="3" |
|-
| colspan="3" |The following are Res Charts across the exposure field:
|-
|0.605 , 1.005
| -10.115000
|12.150000
|-
|same for each
| -7.415000
|12.150000
|-
|" "
| -4.715000
|12.150000
|-
|" "
| -2.015000
|12.150000
|-
|" "
|0.685000
|12.150000
|-
|" "
|3.385000
|12.150000
|-
|" "
|6.085000
|12.150000
|-
|" "
|8.785000
|12.150000
|-
!
!
!
|-
|
| -10.115000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.715000
|9.450000
|-
|
| -2.015000
|9.450000
|-
|
|0.685000
|9.450000
|-
|
|3.385000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|8.785000
|9.450000
|-
!
!
!
|-
|
| -10.115000
|6.750000
|-
|
| -7.415000
|6.750000
|-
|
| -4.715000
|6.750000
|-
|
| -2.015000
|6.750000
|-
|
|0.685000
|6.750000
|-
|
|3.385000
|6.750000
|-
|
|6.085000
|6.750000
|-
|
|8.785000
|6.750000
|-
!
!
!
|-
|
| -10.115000
|4.050000
|-
|
| -7.415000
|4.050000
|-
|
| -4.715000
|4.050000
|-
|
| -2.015000
|4.050000
|-
|
|0.685000
|4.050000
|-
|
|3.385000
|4.050000
|-
|
|6.085000
|4.050000
|-
|
|8.785000
|4.050000
|-
!
!
!
|-
|
| -10.115000
|1.350000
|-
|
| -7.415000
|1.350000
|-
|
| -4.715000
|1.350000
|-
|
| -2.015000
|1.350000
|-
|
|0.685000
|1.350000
|-
|
|3.385000
|1.350000
|-
|
|6.085000
|1.350000
|-
|
|8.785000
|1.350000
|-
!
!
!
|-
|
| -10.115000
| -1.350000
|-
|
| -7.415000
| -1.350000
|-
|
| -4.715000
| -1.350000
|-
|
| -2.015000
| -1.350000
|-
|
|0.685000
| -1.350000
|-
|
|3.385000
| -1.350000
|-
|
|6.085000
| -1.350000
|-
|
|8.785000
| -1.350000
|-
!
!
!
|-
|
| -10.115000
| -4.050000
|-
|
| -7.415000
| -4.050000
|-
|
| -4.715000
| -4.050000
|-
|
| -2.015000
| -4.050000
|-
|
|0.685000
| -4.050000
|-
|
|3.385000
| -4.050000
|-
|
|6.085000
| -4.050000
|-
|
|8.785000
| -4.050000
|-
!
!
!
|-
|
| -10.115000
| -6.750000
|-
|
| -7.415000
| -6.750000
|-
|
| -4.715000
| -6.750000
|-
|
| -2.015000
| -6.750000
|-
|
|0.685000
| -6.750000
|-
|
|3.385000
| -6.750000
|-
|
|6.085000
| -6.750000
|-
|
|8.785000
| -6.750000
|-
!
!
!
|-
|
| -10.115000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.715000
| -9.450000
|-
|
| -2.015000
| -9.450000
|-
|
|0.685000
| -9.450000
|-
|
|3.385000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|8.785000
| -9.450000
|-
!
!
!
|-
|
| -10.115000
| -12.150000
|-
|
| -7.415000
| -12.150000
|-
|
| -4.715000
| -12.150000
|-
|
| -2.015000
| -12.150000
|-
|
|0.685000
| -12.150000
|-
|
|3.385000
| -12.150000
|-
|
|6.085000
| -12.150000
|-
|
|8.785000
| -12.150000
|}

===== Coords for "UCSB_Cal" Calibration Patterns =====
Each of the above "''UCSB_Cal''" cells, including all 7 patterns, is repeated on the following coordinates across the plate (coords are to the center of the "''UCSB_Cal''" cell):
{| class="wikitable"
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X

(Wafer, mm)
!Image Shift
Y

(Wafer, mm)
|-
|2.610000 , 2.610000
| -9.450000
|12.150000
|-
|same as above
| -6.750000
|12.150000
|-
|" "
| -4.050000
|12.150000
|-
|" "
| -1.350000
|12.150000
|-
|" "
|1.350000
|12.150000
|-
|" "
|4.050000
|12.150000
|-
|" "
|6.750000
|12.150000
|-
|" "
|9.450000
|12.150000
|-
! colspan="3" |
|-
|
| -9.450000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.050000
|9.450000
|-
|
| -1.350000
|9.450000
|-
|
|1.350000
|9.450000
|-
|
|4.050000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|9.450000
|9.450000
|-
! colspan="3" |
|-
|
| -9.450000
|6.750000
|-
|
| -6.750000
|6.750000
|-
|
| -4.050000
|6.750000
|-
|
| -1.350000
|6.750000
|-
|
|1.350000
|6.750000
|-
|
|4.050000
|6.750000
|-
|
|6.750000
|6.750000
|-
|
|9.450000
|6.750000
|-
! colspan="3" |
|-
|
| -9.450000
|4.050000
|-
|
| -6.750000
|4.050000
|-
|
| -4.050000
|4.050000
|-
|
| -1.350000
|4.050000
|-
|
|1.350000
|4.050000
|-
|
|4.050000
|4.050000
|-
|
|6.750000
|4.050000
|-
|
|9.450000
|4.050000
|-
! colspan="3" |
|-
|
| -9.450000
|1.350000
|-
|
| -6.750000
|1.350000
|-
|
| -4.050000
|1.350000
|-
|
| -1.350000
|1.350000
|-
|
|1.350000
|1.350000
|-
|
|4.050000
|1.350000
|-
|
|6.750000
|1.350000
|-
|
|9.450000
|1.350000
|-
! colspan="3" |
|-
|
| -9.450000
| -1.350000
|-
|
| -6.750000
| -1.350000
|-
|
| -4.050000
| -1.350000
|-
|
| -1.350000
| -1.350000
|-
|
|1.350000
| -1.350000
|-
|
|4.050000
| -1.350000
|-
|
|6.750000
| -1.350000
|-
|
|9.450000
| -1.350000
|-
! colspan="3" |
|-
|
| -9.450000
| -4.050000
|-
|
| -6.750000
| -4.050000
|-
|
| -4.050000
| -4.050000
|-
|
| -1.350000
| -4.050000
|-
|
|1.350000
| -4.050000
|-
|
|4.050000
| -4.050000
|-
|
|6.750000
| -4.050000
|-
|
|9.450000
| -4.050000
|-
! colspan="3" |
|-
|
| -9.450000
| -6.750000
|-
|
| -6.750000
| -6.750000
|-
|
| -4.050000
| -6.750000
|-
|
| -1.350000
| -6.750000
|-
|
|1.350000
| -6.750000
|-
|
|4.050000
| -6.750000
|-
|
|6.750000
| -6.750000
|-
|
|9.450000
| -6.750000
|-
! colspan="3" |
|-
|
| -9.450000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.050000
| -9.450000
|-
|
| -1.350000
| -9.450000
|-
|
|1.350000
| -9.450000
|-
|
|4.050000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|9.450000
| -9.450000
|-
! colspan="3" |
|-
|
| -9.450000
| -12.150000
|-
|
| -6.750000
| -12.150000
|-
|
| -4.050000
| -12.150000
|-
|
| -1.350000
| -12.150000
|-
|
|1.350000
| -12.150000
|-
|
|4.050000
| -12.150000
|-
|
|6.750000
| -12.150000
|-
|
|9.450000
| -12.150000
|}

ASML Stepper 3 - UCSB Test Reticles

2026-02-26T06:14:59Z

John d: added headings

== Other Masks and Images ==
We have various patterns on other plates, such as:

* various line/space,
* alignment markers modifications,
* full-field exposure,
* 1mm boxes

See this document for programming info:

[https://docs.google.com/document/d/1sNfphnUfw0k9v7HkZGNpgm5siRxQiU6SCPqIY13mD2w/edit?tab=t.0 '''<big>UCSB Masks and Images for ASML</big>''']

* These are inside the Secure Google Drive folder, you will need to login with your UCSBNetID to access. Ask the [[Demis D. John|Supervisor]] for access.
* Remember your UCSB NetID is a Google Login, formatted as '''''MyNetID'''@ucsb.edu''. If you are trained on the tool, you already have access using this UCSB NetID login.

== Alignment Marks for other systems, other patterns ==

=== Reticle ID: "'''UCSBMARKS26'''" ===
This reticle is always installed in the system, in the "System Reticles" Box #1.

Contains many alignment marks, for as many litho systems in the Nanofab as possible. Also edge-bead removal 1cm field, dicing guides, 1mm "boxes" for Laser Monitoring, verniers etc.

See the GDS File & Programming Params in the [https://drive.google.com/drive/folders/1nZhD1lcizLurOxHx1gKKNvAy05SUGXOo?usp=drive_link UCSB Masks Google Drive] (login via UCSB NetID)
{| class="wikitable"
!Image ID
! colspan="2" |Image Size
(Wafer, mm)
! colspan="2" |Image Shift
(Wafer, mm)
!Notes/Description
!Schematics
|-
!
!X
!Y
!X
!Y
!
!
|-
| colspan="7" |
==== '''Alignment Markers''' ====
|-
|Square_30p5
|0.030500
|0.030500
| -4.000000
| -1.000000
|
|
|-
|RaithMark_20um
|0.020000
|0.020000
| -4.000000
| -4.000000
|
|
|-
|MLA_Align
|0.700000
|0.700000
| -4.000000
|10.500000
|
|
|-
|GCA_Align
|0.350000
|0.150000
| -4.000000
|9.000000
|Coord is center to GCA mark. Center of DFAS mark is +0.200mm to the right.
|White is Chrome, Pattern is Clear[[File:Stepper align - Screen Shot 2018-07-23 at 11.24.31 AM.png|frameless|213x213px]]
[[Media:GCA stepper align.gds|CAD File (GDS):GCA_stepper_align.gds]]
|-
|Contact_AlignLyr2
|0.300000
|0.300000
| -4.000000
| -5.500000
|
|
|-
| colspan="7" |
==== '''Open Squares of various sizes''' ====
|-
|Square_100um
|0.100000
|0.100000
|7.500000
|12.000000
|
|
|-
|Square_200um
|0.200000
|0.200000
|6.000000
|12.000000
|
|
|-
|Square_500um
|0.500000
|0.500000
|4.500000
|12.000000
|Good for Laser Monitor openings
|
|-
|Square_1mm
|1.000000
|1.000000
|2.500000
|12.000000
|Preferred for Laser Monitor openings
|
|-
|Square_2mm
|2.000000
|2.000000
|0.000000
|12.000000
|
|
|-
|Square_5mm
|5.000000
|5.000000
|8.500000
|8.000000
|
|
|-
|Square_10mm
|10.000000
|10.000000
|6.000000
| -5.000000
|Good for Edge-Bead Exposure
|
|}

==== Other available Images ====
More patterns can be found on the OAS file and the Excel Sheet of ASML Programming Parameters

([https://drive.google.com/drive/folders/1nZhD1lcizLurOxHx1gKKNvAy05SUGXOo?usp=drive_link see gDrive folder here] - requires UCSB NetID), such as:

* Same alignment marks as above, but with X/Y Vernier alignment measurements
* Layer-2 Vernier (to match the above verniers)
* Dicing guides in X & Y
* ASML PM Marks rotated by 90°, 180° and 270°
* Calibration patterns used in Nanofab LithoCals and EtchCals, such as
** Hex array of holes at 250nm diam / 250nm gap
** Hex array of holes at 400nm diam / 300nm gap (ASML LithoCals)
** 10µm, 1µm, 0.50µm Line/Space (DSE EtchCals)
* Complementary (Layer-2) Alignment Marks for Contact, Inverted marks

=== Reticle ID: "'''UCSB-OPC1'''" ===
This reticle is always installed in the system, in the "System Reticles" Box #1.

The reticle contains alignment markers for various NanoFab lithography systems, along with resolution test structures and patterns for calibrating [https://en.wikipedia.org/wiki/Optical_proximity_correction optical proximity correction] on the system. Some patterns are proprietary to the mask designer, so we can not share the full GDS CAD file.

==== Alignment Markers ====
{| class="wikitable"
!Image ID
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X , Y

(Wafer, mm)
!Notes/Description
!Schematics
|-
|GCA_Align
|0.530000 , 0.140000
| -6.750000 , 9.450000
|ImageShift references the center of the -X- "global" mark.
The <nowiki>==|||</nowiki> "Local" mark is X+200µm to the right

has 1.1mm margin on all sides
|White is Chrome, Pattern is Clear[[File:Stepper align - Screen Shot 2018-07-23 at 11.24.31 AM.png|frameless|213x213px]]
[[Media:GCA stepper align.gds|CAD File (GDS):GCA_stepper_align.gds]]
|-
|JEOL E-Beam Litho Alignment Mark - Positive
|0.900000 , 0.900000
| -6.750000 , -9.450000
|ImageShift is the center coords of the larger "+" mark
Smaller "+" mark is (0.225,-0.225)mm down-right

0.925mm margin on all sides
|White is Chrome, Pattern is Clear
[[File:GlobalMulti POS - Screen Shot 2018-07-23 at 11.17.23 AM.png|frameless|145x145px]]

[[Media:EBL-GlobalMulti POS.gds|CAD File (GDS): EBL-GlobalMulti_POS.gds]]
|-
|JEOL E-Beam Litho Alignment Mark - Negative
|0.710000 , 0.710000
|6.750000 , -9.450000
|ImageShift is the center coords of the larger "+" mark
Smaller "+" mark is (0.225,-0.225)mm down-right

Blank (masked) space on left+top sides

1.0mm margin on all sides
|Striped area is Clear
[[File:GlobalMulti NEG - Screen Shot 2018-07-23 at 11.22.19 AM.png|frameless|115x115px]]

[[Media:EBL-GlobalMulti NEG.gds|CAD File (GDS): EBL-GlobalMulti_NEG.gds]]
|-
|Contact Mark
|0.564000 , 0.564000
|6.750000 , 9.450000
|ImageShift references the center of the contact alignment mark "+"

with 1.1mm margin on all sides

Note the Polarity - will ''expose'' a ~550µm area.
|White is Chrome, Striped area is Clear
[[File:Align Front - Screen Shot 2018-07-23 at 11.32.16 AM.png|frameless|146x146px]]

[[Media:Contact-AlignFront.gds|CAD File (GDS): Contact-AlignFront.gds]]

[[Media:MA6-FrontBack AlignMarks only.gds|Corresponding male/female alignment marks (GDS): MA6-FrontBack_AlignMarks_only.gds]]
|}

==== Resolution Test Charts ====
The Resolution test charts are repeated all across the reticle, in order to test for lens aberrations. You can have the system expose only a single resolution chart, but since they are placed closely together on the reticle, it's very likely that partial shots of adjacent charts will also be exposed.

In addition, the repeating cells allow us to test for the proper [https://en.wikipedia.org/wiki/Optical_proximity_correction optical proximity correction] (OPC) algorithm. The Five <code>Dense_...</code> patterns are for calibrating the OPC algorithm, and are not for user analysis.

'''''Patterned area is CLEAR/transparent.'''''

===== Calibration Chart Layout =====

Cell name is "''UCSB_Cal''", with coordinates below pointing to center of this cell.[[File:UCSB cal - Screen Shot 2018-07-23 at 12.06.58 PM.png|alt=Layout of the repeating calibration charts|none|thumb|512x512px|Layout of the repeating calibration charts]]

===== Resolution Chart =====
"resolution_chart_ORIG" cell in the above. '''''Blue/patterned area is CLEAR/transparent.'''''
[[File:Resolution Chart - Screen Shot 2018-07-23 at 1.36.31 PM.png|alt=Resolution Chart Layout schematic|none|thumb|400x400px|'''"resolution_chart_ORIG":''' Resolution Chart Layout, with res. test from 2.00µm to 0.130µm]]

The ""resolution_chart_OPC" version has an optical proximity correction algorithm applied:
[[File:Resolution chart OPC - Screen Shot 2018-07-23 at 1.40.48 PM.png|alt=OPC'd Resolution Chart Layout schematic|none|thumb|395x395px|'''"resolution_chart_OPC":''' OPC'd Resolution Chart Layout, with res. test from 2.0µm to 0.130µm]]

===== Coords for "resolution_chart" Calibration patterns =====
''Image coords for each of the "resolution_chart_ORIG" cells. You can pick just one of these for shooting a resolution test structure. The purpose of the many different locations is to check for variations due to lens aberrations. You could just choose one near the center of the plate to test your process, or you could choose a chart that is in a similar location as the pattern you're shooting on your mask plate.''

''Note that some portion of the adjacent patterns will likely be exposed as well, due to the patterns not being surrounded by 1mm of chrome. Make sure you set your Cell Size large enough to make sure the bleed-over doesn't overlap with adjacent die.''
{| class="wikitable"
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X

(Wafer, mm)
!Image Shift
Y

(Wafer, mm)
|-
| colspan="3" |Use this for a single Resolution Chart:
|-
|0.605 , 1.005
|0.685000
|1.350000
|-
| colspan="3" |
|-
| colspan="3" |The following are Res Charts across the exposure field:
|-
|0.605 , 1.005
| -10.115000
|12.150000
|-
|same for each
| -7.415000
|12.150000
|-
|" "
| -4.715000
|12.150000
|-
|" "
| -2.015000
|12.150000
|-
|" "
|0.685000
|12.150000
|-
|" "
|3.385000
|12.150000
|-
|" "
|6.085000
|12.150000
|-
|" "
|8.785000
|12.150000
|-
!
!
!
|-
|
| -10.115000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.715000
|9.450000
|-
|
| -2.015000
|9.450000
|-
|
|0.685000
|9.450000
|-
|
|3.385000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|8.785000
|9.450000
|-
!
!
!
|-
|
| -10.115000
|6.750000
|-
|
| -7.415000
|6.750000
|-
|
| -4.715000
|6.750000
|-
|
| -2.015000
|6.750000
|-
|
|0.685000
|6.750000
|-
|
|3.385000
|6.750000
|-
|
|6.085000
|6.750000
|-
|
|8.785000
|6.750000
|-
!
!
!
|-
|
| -10.115000
|4.050000
|-
|
| -7.415000
|4.050000
|-
|
| -4.715000
|4.050000
|-
|
| -2.015000
|4.050000
|-
|
|0.685000
|4.050000
|-
|
|3.385000
|4.050000
|-
|
|6.085000
|4.050000
|-
|
|8.785000
|4.050000
|-
!
!
!
|-
|
| -10.115000
|1.350000
|-
|
| -7.415000
|1.350000
|-
|
| -4.715000
|1.350000
|-
|
| -2.015000
|1.350000
|-
|
|0.685000
|1.350000
|-
|
|3.385000
|1.350000
|-
|
|6.085000
|1.350000
|-
|
|8.785000
|1.350000
|-
!
!
!
|-
|
| -10.115000
| -1.350000
|-
|
| -7.415000
| -1.350000
|-
|
| -4.715000
| -1.350000
|-
|
| -2.015000
| -1.350000
|-
|
|0.685000
| -1.350000
|-
|
|3.385000
| -1.350000
|-
|
|6.085000
| -1.350000
|-
|
|8.785000
| -1.350000
|-
!
!
!
|-
|
| -10.115000
| -4.050000
|-
|
| -7.415000
| -4.050000
|-
|
| -4.715000
| -4.050000
|-
|
| -2.015000
| -4.050000
|-
|
|0.685000
| -4.050000
|-
|
|3.385000
| -4.050000
|-
|
|6.085000
| -4.050000
|-
|
|8.785000
| -4.050000
|-
!
!
!
|-
|
| -10.115000
| -6.750000
|-
|
| -7.415000
| -6.750000
|-
|
| -4.715000
| -6.750000
|-
|
| -2.015000
| -6.750000
|-
|
|0.685000
| -6.750000
|-
|
|3.385000
| -6.750000
|-
|
|6.085000
| -6.750000
|-
|
|8.785000
| -6.750000
|-
!
!
!
|-
|
| -10.115000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.715000
| -9.450000
|-
|
| -2.015000
| -9.450000
|-
|
|0.685000
| -9.450000
|-
|
|3.385000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|8.785000
| -9.450000
|-
!
!
!
|-
|
| -10.115000
| -12.150000
|-
|
| -7.415000
| -12.150000
|-
|
| -4.715000
| -12.150000
|-
|
| -2.015000
| -12.150000
|-
|
|0.685000
| -12.150000
|-
|
|3.385000
| -12.150000
|-
|
|6.085000
| -12.150000
|-
|
|8.785000
| -12.150000
|}

===== Coords for "UCSB_Cal" Calibration Patterns =====
Each of the above "''UCSB_Cal''" cells, including all 7 patterns, is repeated on the following coordinates across the plate (coords are to the center of the "''UCSB_Cal''" cell):
{| class="wikitable"
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X

(Wafer, mm)
!Image Shift
Y

(Wafer, mm)
|-
|2.610000 , 2.610000
| -9.450000
|12.150000
|-
|same as above
| -6.750000
|12.150000
|-
|" "
| -4.050000
|12.150000
|-
|" "
| -1.350000
|12.150000
|-
|" "
|1.350000
|12.150000
|-
|" "
|4.050000
|12.150000
|-
|" "
|6.750000
|12.150000
|-
|" "
|9.450000
|12.150000
|-
! colspan="3" |
|-
|
| -9.450000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.050000
|9.450000
|-
|
| -1.350000
|9.450000
|-
|
|1.350000
|9.450000
|-
|
|4.050000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|9.450000
|9.450000
|-
! colspan="3" |
|-
|
| -9.450000
|6.750000
|-
|
| -6.750000
|6.750000
|-
|
| -4.050000
|6.750000
|-
|
| -1.350000
|6.750000
|-
|
|1.350000
|6.750000
|-
|
|4.050000
|6.750000
|-
|
|6.750000
|6.750000
|-
|
|9.450000
|6.750000
|-
! colspan="3" |
|-
|
| -9.450000
|4.050000
|-
|
| -6.750000
|4.050000
|-
|
| -4.050000
|4.050000
|-
|
| -1.350000
|4.050000
|-
|
|1.350000
|4.050000
|-
|
|4.050000
|4.050000
|-
|
|6.750000
|4.050000
|-
|
|9.450000
|4.050000
|-
! colspan="3" |
|-
|
| -9.450000
|1.350000
|-
|
| -6.750000
|1.350000
|-
|
| -4.050000
|1.350000
|-
|
| -1.350000
|1.350000
|-
|
|1.350000
|1.350000
|-
|
|4.050000
|1.350000
|-
|
|6.750000
|1.350000
|-
|
|9.450000
|1.350000
|-
! colspan="3" |
|-
|
| -9.450000
| -1.350000
|-
|
| -6.750000
| -1.350000
|-
|
| -4.050000
| -1.350000
|-
|
| -1.350000
| -1.350000
|-
|
|1.350000
| -1.350000
|-
|
|4.050000
| -1.350000
|-
|
|6.750000
| -1.350000
|-
|
|9.450000
| -1.350000
|-
! colspan="3" |
|-
|
| -9.450000
| -4.050000
|-
|
| -6.750000
| -4.050000
|-
|
| -4.050000
| -4.050000
|-
|
| -1.350000
| -4.050000
|-
|
|1.350000
| -4.050000
|-
|
|4.050000
| -4.050000
|-
|
|6.750000
| -4.050000
|-
|
|9.450000
| -4.050000
|-
! colspan="3" |
|-
|
| -9.450000
| -6.750000
|-
|
| -6.750000
| -6.750000
|-
|
| -4.050000
| -6.750000
|-
|
| -1.350000
| -6.750000
|-
|
|1.350000
| -6.750000
|-
|
|4.050000
| -6.750000
|-
|
|6.750000
| -6.750000
|-
|
|9.450000
| -6.750000
|-
! colspan="3" |
|-
|
| -9.450000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.050000
| -9.450000
|-
|
| -1.350000
| -9.450000
|-
|
|1.350000
| -9.450000
|-
|
|4.050000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|9.450000
| -9.450000
|-
! colspan="3" |
|-
|
| -9.450000
| -12.150000
|-
|
| -6.750000
| -12.150000
|-
|
| -4.050000
| -12.150000
|-
|
| -1.350000
| -12.150000
|-
|
|1.350000
| -12.150000
|-
|
|4.050000
| -12.150000
|-
|
|6.750000
| -12.150000
|-
|
|9.450000
| -12.150000
|}

ASML Stepper 3 - UCSB Test Reticles

2026-02-26T06:14:12Z

John d:

== Other Masks and Images ==
We have various patterns on other plates, such as:

* various line/space,
* alignment markers modifications,
* full-field exposure,
* 1mm boxes

See this document for programming info:

[https://docs.google.com/document/d/1sNfphnUfw0k9v7HkZGNpgm5siRxQiU6SCPqIY13mD2w/edit?tab=t.0 '''<big>UCSB Masks and Images for ASML</big>''']

* These are inside the Secure Google Drive folder, you will need to login with your UCSBNetID to access. Ask the [[Demis D. John|Supervisor]] for access.
* Remember your UCSB NetID is a Google Login, formatted as '''''MyNetID'''@ucsb.edu''. If you are trained on the tool, you already have access using this UCSB NetID login.

== Alignment Marks for other systems, other patterns ==

=== Reticle ID: "'''UCSBMARKS26'''" ===
This reticle is always installed in the system, in the "System Reticles" Box #1.

Contains many alignment marks, for as many litho systems in the Nanofab as possible. Also edge-bead removal 1cm field, dicing guides, 1mm "boxes" for Laser Monitoring, verniers etc.

See the GDS File & Programming Params in the [https://drive.google.com/drive/folders/1nZhD1lcizLurOxHx1gKKNvAy05SUGXOo?usp=drive_link UCSB Masks Google Drive] (login via UCSB NetID)
{| class="wikitable"
!Image ID
! colspan="2" |Image Size
(Wafer, mm)
! colspan="2" |Image Shift
(Wafer, mm)
!Notes/Description
!Schematics
|-
!
!X
!Y
!X
!Y
!
!
|-
| colspan="7" |'''Alignment Markers'''
|-
|Square_30p5
|0.030500
|0.030500
| -4.000000
| -1.000000
|
|
|-
|RaithMark_20um
|0.020000
|0.020000
| -4.000000
| -4.000000
|
|
|-
|MLA_Align
|0.700000
|0.700000
| -4.000000
|10.500000
|
|
|-
|GCA_Align
|0.350000
|0.150000
| -4.000000
|9.000000
|Coord is center to GCA mark. Center of DFAS mark is +0.200mm to the right.
|White is Chrome, Pattern is Clear[[File:Stepper align - Screen Shot 2018-07-23 at 11.24.31 AM.png|frameless|213x213px]]
[[Media:GCA stepper align.gds|CAD File (GDS):GCA_stepper_align.gds]]
|-
|Contact_AlignLyr2
|0.300000
|0.300000
| -4.000000
| -5.500000
|
|
|-
| colspan="7" |'''Open Squares of various sizes'''
|-
|Square_100um
|0.100000
|0.100000
|7.500000
|12.000000
|
|
|-
|Square_200um
|0.200000
|0.200000
|6.000000
|12.000000
|
|
|-
|Square_500um
|0.500000
|0.500000
|4.500000
|12.000000
|Good for Laser Monitor openings
|
|-
|Square_1mm
|1.000000
|1.000000
|2.500000
|12.000000
|Preferred for Laser Monitor openings
|
|-
|Square_2mm
|2.000000
|2.000000
|0.000000
|12.000000
|
|
|-
|Square_5mm
|5.000000
|5.000000
|8.500000
|8.000000
|
|
|-
|Square_10mm
|10.000000
|10.000000
|6.000000
| -5.000000
|Good for Edge-Bead Exposure
|
|}
More patterns can be found on the OAS file and the Excel Sheet of ASML Programming Parameters

([https://drive.google.com/drive/folders/1nZhD1lcizLurOxHx1gKKNvAy05SUGXOo?usp=drive_link see gDrive folder here] - requires UCSB NetID), such as:

* Same alignment marks as above, but with X/Y Vernier alignment measurements
* Layer-2 Vernier (to match the above verniers)
* Dicing guides in X & Y
* ASML PM Marks rotated by 90°, 180° and 270°
* Calibration patterns used in Nanofab LithoCals and EtchCals, such as
** Hex array of holes at 250nm diam / 250nm gap
** Hex array of holes at 400nm diam / 300nm gap (ASML LithoCals)
** 10µm, 1µm, 0.50µm Line/Space (DSE EtchCals)
* Complementary (Layer-2) Alignment Marks for Contact, Inverted marks

=== Reticle ID: "'''UCSB-OPC1'''" ===
This reticle is always installed in the system, in the "System Reticles" Box #1.

The reticle contains alignment markers for various NanoFab lithography systems, along with resolution test structures and patterns for calibrating [https://en.wikipedia.org/wiki/Optical_proximity_correction optical proximity correction] on the system. Some patterns are proprietary to the mask designer, so we can not share the full GDS CAD file.

==== Alignment Markers ====
{| class="wikitable"
!Image ID
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X , Y

(Wafer, mm)
!Notes/Description
!Schematics
|-
|GCA_Align
|0.530000 , 0.140000
| -6.750000 , 9.450000
|ImageShift references the center of the -X- "global" mark.
The <nowiki>==|||</nowiki> "Local" mark is X+200µm to the right

has 1.1mm margin on all sides
|White is Chrome, Pattern is Clear[[File:Stepper align - Screen Shot 2018-07-23 at 11.24.31 AM.png|frameless|213x213px]]
[[Media:GCA stepper align.gds|CAD File (GDS):GCA_stepper_align.gds]]
|-
|JEOL E-Beam Litho Alignment Mark - Positive
|0.900000 , 0.900000
| -6.750000 , -9.450000
|ImageShift is the center coords of the larger "+" mark
Smaller "+" mark is (0.225,-0.225)mm down-right

0.925mm margin on all sides
|White is Chrome, Pattern is Clear
[[File:GlobalMulti POS - Screen Shot 2018-07-23 at 11.17.23 AM.png|frameless|145x145px]]

[[Media:EBL-GlobalMulti POS.gds|CAD File (GDS): EBL-GlobalMulti_POS.gds]]
|-
|JEOL E-Beam Litho Alignment Mark - Negative
|0.710000 , 0.710000
|6.750000 , -9.450000
|ImageShift is the center coords of the larger "+" mark
Smaller "+" mark is (0.225,-0.225)mm down-right

Blank (masked) space on left+top sides

1.0mm margin on all sides
|Striped area is Clear
[[File:GlobalMulti NEG - Screen Shot 2018-07-23 at 11.22.19 AM.png|frameless|115x115px]]

[[Media:EBL-GlobalMulti NEG.gds|CAD File (GDS): EBL-GlobalMulti_NEG.gds]]
|-
|Contact Mark
|0.564000 , 0.564000
|6.750000 , 9.450000
|ImageShift references the center of the contact alignment mark "+"

with 1.1mm margin on all sides

Note the Polarity - will ''expose'' a ~550µm area.
|White is Chrome, Striped area is Clear
[[File:Align Front - Screen Shot 2018-07-23 at 11.32.16 AM.png|frameless|146x146px]]

[[Media:Contact-AlignFront.gds|CAD File (GDS): Contact-AlignFront.gds]]

[[Media:MA6-FrontBack AlignMarks only.gds|Corresponding male/female alignment marks (GDS): MA6-FrontBack_AlignMarks_only.gds]]
|}

==== Resolution Test Charts ====
The Resolution test charts are repeated all across the reticle, in order to test for lens aberrations. You can have the system expose only a single resolution chart, but since they are placed closely together on the reticle, it's very likely that partial shots of adjacent charts will also be exposed.

In addition, the repeating cells allow us to test for the proper [https://en.wikipedia.org/wiki/Optical_proximity_correction optical proximity correction] (OPC) algorithm. The Five <code>Dense_...</code> patterns are for calibrating the OPC algorithm, and are not for user analysis.

'''''Patterned area is CLEAR/transparent.'''''

===== Calibration Chart Layout =====

Cell name is "''UCSB_Cal''", with coordinates below pointing to center of this cell.[[File:UCSB cal - Screen Shot 2018-07-23 at 12.06.58 PM.png|alt=Layout of the repeating calibration charts|none|thumb|512x512px|Layout of the repeating calibration charts]]

===== Resolution Chart =====
"resolution_chart_ORIG" cell in the above. '''''Blue/patterned area is CLEAR/transparent.'''''
[[File:Resolution Chart - Screen Shot 2018-07-23 at 1.36.31 PM.png|alt=Resolution Chart Layout schematic|none|thumb|400x400px|'''"resolution_chart_ORIG":''' Resolution Chart Layout, with res. test from 2.00µm to 0.130µm]]

The ""resolution_chart_OPC" version has an optical proximity correction algorithm applied:
[[File:Resolution chart OPC - Screen Shot 2018-07-23 at 1.40.48 PM.png|alt=OPC'd Resolution Chart Layout schematic|none|thumb|395x395px|'''"resolution_chart_OPC":''' OPC'd Resolution Chart Layout, with res. test from 2.0µm to 0.130µm]]

===== Coords for "resolution_chart" Calibration patterns =====
''Image coords for each of the "resolution_chart_ORIG" cells. You can pick just one of these for shooting a resolution test structure. The purpose of the many different locations is to check for variations due to lens aberrations. You could just choose one near the center of the plate to test your process, or you could choose a chart that is in a similar location as the pattern you're shooting on your mask plate.''

''Note that some portion of the adjacent patterns will likely be exposed as well, due to the patterns not being surrounded by 1mm of chrome. Make sure you set your Cell Size large enough to make sure the bleed-over doesn't overlap with adjacent die.''
{| class="wikitable"
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X

(Wafer, mm)
!Image Shift
Y

(Wafer, mm)
|-
| colspan="3" |Use this for a single Resolution Chart:
|-
|0.605 , 1.005
|0.685000
|1.350000
|-
| colspan="3" |
|-
| colspan="3" |The following are Res Charts across the exposure field:
|-
|0.605 , 1.005
| -10.115000
|12.150000
|-
|same for each
| -7.415000
|12.150000
|-
|" "
| -4.715000
|12.150000
|-
|" "
| -2.015000
|12.150000
|-
|" "
|0.685000
|12.150000
|-
|" "
|3.385000
|12.150000
|-
|" "
|6.085000
|12.150000
|-
|" "
|8.785000
|12.150000
|-
!
!
!
|-
|
| -10.115000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.715000
|9.450000
|-
|
| -2.015000
|9.450000
|-
|
|0.685000
|9.450000
|-
|
|3.385000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|8.785000
|9.450000
|-
!
!
!
|-
|
| -10.115000
|6.750000
|-
|
| -7.415000
|6.750000
|-
|
| -4.715000
|6.750000
|-
|
| -2.015000
|6.750000
|-
|
|0.685000
|6.750000
|-
|
|3.385000
|6.750000
|-
|
|6.085000
|6.750000
|-
|
|8.785000
|6.750000
|-
!
!
!
|-
|
| -10.115000
|4.050000
|-
|
| -7.415000
|4.050000
|-
|
| -4.715000
|4.050000
|-
|
| -2.015000
|4.050000
|-
|
|0.685000
|4.050000
|-
|
|3.385000
|4.050000
|-
|
|6.085000
|4.050000
|-
|
|8.785000
|4.050000
|-
!
!
!
|-
|
| -10.115000
|1.350000
|-
|
| -7.415000
|1.350000
|-
|
| -4.715000
|1.350000
|-
|
| -2.015000
|1.350000
|-
|
|0.685000
|1.350000
|-
|
|3.385000
|1.350000
|-
|
|6.085000
|1.350000
|-
|
|8.785000
|1.350000
|-
!
!
!
|-
|
| -10.115000
| -1.350000
|-
|
| -7.415000
| -1.350000
|-
|
| -4.715000
| -1.350000
|-
|
| -2.015000
| -1.350000
|-
|
|0.685000
| -1.350000
|-
|
|3.385000
| -1.350000
|-
|
|6.085000
| -1.350000
|-
|
|8.785000
| -1.350000
|-
!
!
!
|-
|
| -10.115000
| -4.050000
|-
|
| -7.415000
| -4.050000
|-
|
| -4.715000
| -4.050000
|-
|
| -2.015000
| -4.050000
|-
|
|0.685000
| -4.050000
|-
|
|3.385000
| -4.050000
|-
|
|6.085000
| -4.050000
|-
|
|8.785000
| -4.050000
|-
!
!
!
|-
|
| -10.115000
| -6.750000
|-
|
| -7.415000
| -6.750000
|-
|
| -4.715000
| -6.750000
|-
|
| -2.015000
| -6.750000
|-
|
|0.685000
| -6.750000
|-
|
|3.385000
| -6.750000
|-
|
|6.085000
| -6.750000
|-
|
|8.785000
| -6.750000
|-
!
!
!
|-
|
| -10.115000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.715000
| -9.450000
|-
|
| -2.015000
| -9.450000
|-
|
|0.685000
| -9.450000
|-
|
|3.385000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|8.785000
| -9.450000
|-
!
!
!
|-
|
| -10.115000
| -12.150000
|-
|
| -7.415000
| -12.150000
|-
|
| -4.715000
| -12.150000
|-
|
| -2.015000
| -12.150000
|-
|
|0.685000
| -12.150000
|-
|
|3.385000
| -12.150000
|-
|
|6.085000
| -12.150000
|-
|
|8.785000
| -12.150000
|}

===== Coords for "UCSB_Cal" Calibration Patterns =====
Each of the above "''UCSB_Cal''" cells, including all 7 patterns, is repeated on the following coordinates across the plate (coords are to the center of the "''UCSB_Cal''" cell):
{| class="wikitable"
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X

(Wafer, mm)
!Image Shift
Y

(Wafer, mm)
|-
|2.610000 , 2.610000
| -9.450000
|12.150000
|-
|same as above
| -6.750000
|12.150000
|-
|" "
| -4.050000
|12.150000
|-
|" "
| -1.350000
|12.150000
|-
|" "
|1.350000
|12.150000
|-
|" "
|4.050000
|12.150000
|-
|" "
|6.750000
|12.150000
|-
|" "
|9.450000
|12.150000
|-
! colspan="3" |
|-
|
| -9.450000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.050000
|9.450000
|-
|
| -1.350000
|9.450000
|-
|
|1.350000
|9.450000
|-
|
|4.050000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|9.450000
|9.450000
|-
! colspan="3" |
|-
|
| -9.450000
|6.750000
|-
|
| -6.750000
|6.750000
|-
|
| -4.050000
|6.750000
|-
|
| -1.350000
|6.750000
|-
|
|1.350000
|6.750000
|-
|
|4.050000
|6.750000
|-
|
|6.750000
|6.750000
|-
|
|9.450000
|6.750000
|-
! colspan="3" |
|-
|
| -9.450000
|4.050000
|-
|
| -6.750000
|4.050000
|-
|
| -4.050000
|4.050000
|-
|
| -1.350000
|4.050000
|-
|
|1.350000
|4.050000
|-
|
|4.050000
|4.050000
|-
|
|6.750000
|4.050000
|-
|
|9.450000
|4.050000
|-
! colspan="3" |
|-
|
| -9.450000
|1.350000
|-
|
| -6.750000
|1.350000
|-
|
| -4.050000
|1.350000
|-
|
| -1.350000
|1.350000
|-
|
|1.350000
|1.350000
|-
|
|4.050000
|1.350000
|-
|
|6.750000
|1.350000
|-
|
|9.450000
|1.350000
|-
! colspan="3" |
|-
|
| -9.450000
| -1.350000
|-
|
| -6.750000
| -1.350000
|-
|
| -4.050000
| -1.350000
|-
|
| -1.350000
| -1.350000
|-
|
|1.350000
| -1.350000
|-
|
|4.050000
| -1.350000
|-
|
|6.750000
| -1.350000
|-
|
|9.450000
| -1.350000
|-
! colspan="3" |
|-
|
| -9.450000
| -4.050000
|-
|
| -6.750000
| -4.050000
|-
|
| -4.050000
| -4.050000
|-
|
| -1.350000
| -4.050000
|-
|
|1.350000
| -4.050000
|-
|
|4.050000
| -4.050000
|-
|
|6.750000
| -4.050000
|-
|
|9.450000
| -4.050000
|-
! colspan="3" |
|-
|
| -9.450000
| -6.750000
|-
|
| -6.750000
| -6.750000
|-
|
| -4.050000
| -6.750000
|-
|
| -1.350000
| -6.750000
|-
|
|1.350000
| -6.750000
|-
|
|4.050000
| -6.750000
|-
|
|6.750000
| -6.750000
|-
|
|9.450000
| -6.750000
|-
! colspan="3" |
|-
|
| -9.450000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.050000
| -9.450000
|-
|
| -1.350000
| -9.450000
|-
|
|1.350000
| -9.450000
|-
|
|4.050000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|9.450000
| -9.450000
|-
! colspan="3" |
|-
|
| -9.450000
| -12.150000
|-
|
| -6.750000
| -12.150000
|-
|
| -4.050000
| -12.150000
|-
|
| -1.350000
| -12.150000
|-
|
|1.350000
| -12.150000
|-
|
|4.050000
| -12.150000
|-
|
|6.750000
| -12.150000
|-
|
|9.450000
| -12.150000
|}

ASML Stepper 3 - UCSB Test Reticles

2026-02-26T06:13:51Z

John d: /* Alignment Marks for other systems */ added UCSBMARKS26

== Other Masks and Images ==
We have various patterns on other plates, such as:

* various line/space,
* alignment markers modifications,
* full-field exposure,
* 1mm boxes

See this document for programming info:

[https://docs.google.com/document/d/1sNfphnUfw0k9v7HkZGNpgm5siRxQiU6SCPqIY13mD2w/edit?tab=t.0 '''<big>UCSB Masks and Images for ASML</big>''']

* These are inside the Secure Google Drive folder, you will need to login with your UCSBNetID to access. Ask the [[Demis D. John|Supervisor]] for access.
* Remember your UCSB NetID is a Google Login, formatted as '''''MyNetID'''@ucsb.edu''. If you are trained on the tool, you already have access using this UCSB NetID login.

== Alignment Marks for other systems, other patterns ==

=== Reticle ID: "UCSBMARKS26" ===
This reticle is always installed in the system, in the "System Reticles" Box #1.

Contains many alignment marks, for as many litho systems in the Nanofab as possible. Also edge-bead removal 1cm field, dicing guides, 1mm "boxes" for Laser Monitoring, verniers etc.

See the GDS File & Programming Params in the [https://drive.google.com/drive/folders/1nZhD1lcizLurOxHx1gKKNvAy05SUGXOo?usp=drive_link UCSB Masks Google Drive] (login via UCSB NetID)
{| class="wikitable"
!Image ID
! colspan="2" |Image Size
(Wafer, mm)
! colspan="2" |Image Shift
(Wafer, mm)
!Notes/Description
!Schematics
|-
!
!X
!Y
!X
!Y
!
!
|-
| colspan="7" |'''Alignment Markers'''
|-
|Square_30p5
|0.030500
|0.030500
| -4.000000
| -1.000000
|
|
|-
|RaithMark_20um
|0.020000
|0.020000
| -4.000000
| -4.000000
|
|
|-
|MLA_Align
|0.700000
|0.700000
| -4.000000
|10.500000
|
|
|-
|GCA_Align
|0.350000
|0.150000
| -4.000000
|9.000000
|Coord is center to GCA mark. Center of DFAS mark is +0.200mm to the right.
|White is Chrome, Pattern is Clear[[File:Stepper align - Screen Shot 2018-07-23 at 11.24.31 AM.png|frameless|213x213px]]
[[Media:GCA stepper align.gds|CAD File (GDS):GCA_stepper_align.gds]]
|-
|Contact_AlignLyr2
|0.300000
|0.300000
| -4.000000
| -5.500000
|
|
|-
| colspan="7" |'''Open Squares of various sizes'''
|-
|Square_100um
|0.100000
|0.100000
|7.500000
|12.000000
|
|
|-
|Square_200um
|0.200000
|0.200000
|6.000000
|12.000000
|
|
|-
|Square_500um
|0.500000
|0.500000
|4.500000
|12.000000
|Good for Laser Monitor openings
|
|-
|Square_1mm
|1.000000
|1.000000
|2.500000
|12.000000
|Preferred for Laser Monitor openings
|
|-
|Square_2mm
|2.000000
|2.000000
|0.000000
|12.000000
|
|
|-
|Square_5mm
|5.000000
|5.000000
|8.500000
|8.000000
|
|
|-
|Square_10mm
|10.000000
|10.000000
|6.000000
| -5.000000
|Good for Edge-Bead Exposure
|
|}
More patterns can be found on the OAS file and the Excel Sheet of ASML Programming Parameters

([https://drive.google.com/drive/folders/1nZhD1lcizLurOxHx1gKKNvAy05SUGXOo?usp=drive_link see gDrive folder here] - requires UCSB NetID), such as:

* Same alignment marks as above, but with X/Y Vernier alignment measurements
* Layer-2 Vernier (to match the above verniers)
* Dicing guides in X & Y
* ASML PM Marks rotated by 90°, 180° and 270°
* Calibration patterns used in Nanofab LithoCals and EtchCals, such as
** Hex array of holes at 250nm diam / 250nm gap
** Hex array of holes at 400nm diam / 300nm gap (ASML LithoCals)
** 10µm, 1µm, 0.50µm Line/Space (DSE EtchCals)
* Complementary (Layer-2) Alignment Marks for Contact, Inverted marks

=== Reticle ID: "'''UCSB-OPC1'''" ===
This reticle is always installed in the system, in the "System Reticles" Box #1.

The reticle contains alignment markers for various NanoFab lithography systems, along with resolution test structures and patterns for calibrating [https://en.wikipedia.org/wiki/Optical_proximity_correction optical proximity correction] on the system. Some patterns are proprietary to the mask designer, so we can not share the full GDS CAD file.

==== Alignment Markers ====
{| class="wikitable"
!Image ID
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X , Y

(Wafer, mm)
!Notes/Description
!Schematics
|-
|GCA_Align
|0.530000 , 0.140000
| -6.750000 , 9.450000
|ImageShift references the center of the -X- "global" mark.
The <nowiki>==|||</nowiki> "Local" mark is X+200µm to the right

has 1.1mm margin on all sides
|White is Chrome, Pattern is Clear[[File:Stepper align - Screen Shot 2018-07-23 at 11.24.31 AM.png|frameless|213x213px]]
[[Media:GCA stepper align.gds|CAD File (GDS):GCA_stepper_align.gds]]
|-
|JEOL E-Beam Litho Alignment Mark - Positive
|0.900000 , 0.900000
| -6.750000 , -9.450000
|ImageShift is the center coords of the larger "+" mark
Smaller "+" mark is (0.225,-0.225)mm down-right

0.925mm margin on all sides
|White is Chrome, Pattern is Clear
[[File:GlobalMulti POS - Screen Shot 2018-07-23 at 11.17.23 AM.png|frameless|145x145px]]

[[Media:EBL-GlobalMulti POS.gds|CAD File (GDS): EBL-GlobalMulti_POS.gds]]
|-
|JEOL E-Beam Litho Alignment Mark - Negative
|0.710000 , 0.710000
|6.750000 , -9.450000
|ImageShift is the center coords of the larger "+" mark
Smaller "+" mark is (0.225,-0.225)mm down-right

Blank (masked) space on left+top sides

1.0mm margin on all sides
|Striped area is Clear
[[File:GlobalMulti NEG - Screen Shot 2018-07-23 at 11.22.19 AM.png|frameless|115x115px]]

[[Media:EBL-GlobalMulti NEG.gds|CAD File (GDS): EBL-GlobalMulti_NEG.gds]]
|-
|Contact Mark
|0.564000 , 0.564000
|6.750000 , 9.450000
|ImageShift references the center of the contact alignment mark "+"

with 1.1mm margin on all sides

Note the Polarity - will ''expose'' a ~550µm area.
|White is Chrome, Striped area is Clear
[[File:Align Front - Screen Shot 2018-07-23 at 11.32.16 AM.png|frameless|146x146px]]

[[Media:Contact-AlignFront.gds|CAD File (GDS): Contact-AlignFront.gds]]

[[Media:MA6-FrontBack AlignMarks only.gds|Corresponding male/female alignment marks (GDS): MA6-FrontBack_AlignMarks_only.gds]]
|}

==== Resolution Test Charts ====
The Resolution test charts are repeated all across the reticle, in order to test for lens aberrations. You can have the system expose only a single resolution chart, but since they are placed closely together on the reticle, it's very likely that partial shots of adjacent charts will also be exposed.

In addition, the repeating cells allow us to test for the proper [https://en.wikipedia.org/wiki/Optical_proximity_correction optical proximity correction] (OPC) algorithm. The Five <code>Dense_...</code> patterns are for calibrating the OPC algorithm, and are not for user analysis.

'''''Patterned area is CLEAR/transparent.'''''

===== Calibration Chart Layout =====

Cell name is "''UCSB_Cal''", with coordinates below pointing to center of this cell.[[File:UCSB cal - Screen Shot 2018-07-23 at 12.06.58 PM.png|alt=Layout of the repeating calibration charts|none|thumb|512x512px|Layout of the repeating calibration charts]]

===== Resolution Chart =====
"resolution_chart_ORIG" cell in the above. '''''Blue/patterned area is CLEAR/transparent.'''''
[[File:Resolution Chart - Screen Shot 2018-07-23 at 1.36.31 PM.png|alt=Resolution Chart Layout schematic|none|thumb|400x400px|'''"resolution_chart_ORIG":''' Resolution Chart Layout, with res. test from 2.00µm to 0.130µm]]

The ""resolution_chart_OPC" version has an optical proximity correction algorithm applied:
[[File:Resolution chart OPC - Screen Shot 2018-07-23 at 1.40.48 PM.png|alt=OPC'd Resolution Chart Layout schematic|none|thumb|395x395px|'''"resolution_chart_OPC":''' OPC'd Resolution Chart Layout, with res. test from 2.0µm to 0.130µm]]

===== Coords for "resolution_chart" Calibration patterns =====
''Image coords for each of the "resolution_chart_ORIG" cells. You can pick just one of these for shooting a resolution test structure. The purpose of the many different locations is to check for variations due to lens aberrations. You could just choose one near the center of the plate to test your process, or you could choose a chart that is in a similar location as the pattern you're shooting on your mask plate.''

''Note that some portion of the adjacent patterns will likely be exposed as well, due to the patterns not being surrounded by 1mm of chrome. Make sure you set your Cell Size large enough to make sure the bleed-over doesn't overlap with adjacent die.''
{| class="wikitable"
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X

(Wafer, mm)
!Image Shift
Y

(Wafer, mm)
|-
| colspan="3" |Use this for a single Resolution Chart:
|-
|0.605 , 1.005
|0.685000
|1.350000
|-
| colspan="3" |
|-
| colspan="3" |The following are Res Charts across the exposure field:
|-
|0.605 , 1.005
| -10.115000
|12.150000
|-
|same for each
| -7.415000
|12.150000
|-
|" "
| -4.715000
|12.150000
|-
|" "
| -2.015000
|12.150000
|-
|" "
|0.685000
|12.150000
|-
|" "
|3.385000
|12.150000
|-
|" "
|6.085000
|12.150000
|-
|" "
|8.785000
|12.150000
|-
!
!
!
|-
|
| -10.115000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.715000
|9.450000
|-
|
| -2.015000
|9.450000
|-
|
|0.685000
|9.450000
|-
|
|3.385000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|8.785000
|9.450000
|-
!
!
!
|-
|
| -10.115000
|6.750000
|-
|
| -7.415000
|6.750000
|-
|
| -4.715000
|6.750000
|-
|
| -2.015000
|6.750000
|-
|
|0.685000
|6.750000
|-
|
|3.385000
|6.750000
|-
|
|6.085000
|6.750000
|-
|
|8.785000
|6.750000
|-
!
!
!
|-
|
| -10.115000
|4.050000
|-
|
| -7.415000
|4.050000
|-
|
| -4.715000
|4.050000
|-
|
| -2.015000
|4.050000
|-
|
|0.685000
|4.050000
|-
|
|3.385000
|4.050000
|-
|
|6.085000
|4.050000
|-
|
|8.785000
|4.050000
|-
!
!
!
|-
|
| -10.115000
|1.350000
|-
|
| -7.415000
|1.350000
|-
|
| -4.715000
|1.350000
|-
|
| -2.015000
|1.350000
|-
|
|0.685000
|1.350000
|-
|
|3.385000
|1.350000
|-
|
|6.085000
|1.350000
|-
|
|8.785000
|1.350000
|-
!
!
!
|-
|
| -10.115000
| -1.350000
|-
|
| -7.415000
| -1.350000
|-
|
| -4.715000
| -1.350000
|-
|
| -2.015000
| -1.350000
|-
|
|0.685000
| -1.350000
|-
|
|3.385000
| -1.350000
|-
|
|6.085000
| -1.350000
|-
|
|8.785000
| -1.350000
|-
!
!
!
|-
|
| -10.115000
| -4.050000
|-
|
| -7.415000
| -4.050000
|-
|
| -4.715000
| -4.050000
|-
|
| -2.015000
| -4.050000
|-
|
|0.685000
| -4.050000
|-
|
|3.385000
| -4.050000
|-
|
|6.085000
| -4.050000
|-
|
|8.785000
| -4.050000
|-
!
!
!
|-
|
| -10.115000
| -6.750000
|-
|
| -7.415000
| -6.750000
|-
|
| -4.715000
| -6.750000
|-
|
| -2.015000
| -6.750000
|-
|
|0.685000
| -6.750000
|-
|
|3.385000
| -6.750000
|-
|
|6.085000
| -6.750000
|-
|
|8.785000
| -6.750000
|-
!
!
!
|-
|
| -10.115000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.715000
| -9.450000
|-
|
| -2.015000
| -9.450000
|-
|
|0.685000
| -9.450000
|-
|
|3.385000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|8.785000
| -9.450000
|-
!
!
!
|-
|
| -10.115000
| -12.150000
|-
|
| -7.415000
| -12.150000
|-
|
| -4.715000
| -12.150000
|-
|
| -2.015000
| -12.150000
|-
|
|0.685000
| -12.150000
|-
|
|3.385000
| -12.150000
|-
|
|6.085000
| -12.150000
|-
|
|8.785000
| -12.150000
|}

===== Coords for "UCSB_Cal" Calibration Patterns =====
Each of the above "''UCSB_Cal''" cells, including all 7 patterns, is repeated on the following coordinates across the plate (coords are to the center of the "''UCSB_Cal''" cell):
{| class="wikitable"
!Image Size
X , Y

(Wafer, mm)
!Image Shift
X

(Wafer, mm)
!Image Shift
Y

(Wafer, mm)
|-
|2.610000 , 2.610000
| -9.450000
|12.150000
|-
|same as above
| -6.750000
|12.150000
|-
|" "
| -4.050000
|12.150000
|-
|" "
| -1.350000
|12.150000
|-
|" "
|1.350000
|12.150000
|-
|" "
|4.050000
|12.150000
|-
|" "
|6.750000
|12.150000
|-
|" "
|9.450000
|12.150000
|-
! colspan="3" |
|-
|
| -9.450000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.050000
|9.450000
|-
|
| -1.350000
|9.450000
|-
|
|1.350000
|9.450000
|-
|
|4.050000
|9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|9.450000
|9.450000
|-
! colspan="3" |
|-
|
| -9.450000
|6.750000
|-
|
| -6.750000
|6.750000
|-
|
| -4.050000
|6.750000
|-
|
| -1.350000
|6.750000
|-
|
|1.350000
|6.750000
|-
|
|4.050000
|6.750000
|-
|
|6.750000
|6.750000
|-
|
|9.450000
|6.750000
|-
! colspan="3" |
|-
|
| -9.450000
|4.050000
|-
|
| -6.750000
|4.050000
|-
|
| -4.050000
|4.050000
|-
|
| -1.350000
|4.050000
|-
|
|1.350000
|4.050000
|-
|
|4.050000
|4.050000
|-
|
|6.750000
|4.050000
|-
|
|9.450000
|4.050000
|-
! colspan="3" |
|-
|
| -9.450000
|1.350000
|-
|
| -6.750000
|1.350000
|-
|
| -4.050000
|1.350000
|-
|
| -1.350000
|1.350000
|-
|
|1.350000
|1.350000
|-
|
|4.050000
|1.350000
|-
|
|6.750000
|1.350000
|-
|
|9.450000
|1.350000
|-
! colspan="3" |
|-
|
| -9.450000
| -1.350000
|-
|
| -6.750000
| -1.350000
|-
|
| -4.050000
| -1.350000
|-
|
| -1.350000
| -1.350000
|-
|
|1.350000
| -1.350000
|-
|
|4.050000
| -1.350000
|-
|
|6.750000
| -1.350000
|-
|
|9.450000
| -1.350000
|-
! colspan="3" |
|-
|
| -9.450000
| -4.050000
|-
|
| -6.750000
| -4.050000
|-
|
| -4.050000
| -4.050000
|-
|
| -1.350000
| -4.050000
|-
|
|1.350000
| -4.050000
|-
|
|4.050000
| -4.050000
|-
|
|6.750000
| -4.050000
|-
|
|9.450000
| -4.050000
|-
! colspan="3" |
|-
|
| -9.450000
| -6.750000
|-
|
| -6.750000
| -6.750000
|-
|
| -4.050000
| -6.750000
|-
|
| -1.350000
| -6.750000
|-
|
|1.350000
| -6.750000
|-
|
|4.050000
| -6.750000
|-
|
|6.750000
| -6.750000
|-
|
|9.450000
| -6.750000
|-
! colspan="3" |
|-
|
| -9.450000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
| -4.050000
| -9.450000
|-
|
| -1.350000
| -9.450000
|-
|
|1.350000
| -9.450000
|-
|
|4.050000
| -9.450000
|-
|
| colspan="2" |''Alignment Marker''
|-
|
|9.450000
| -9.450000
|-
! colspan="3" |
|-
|
| -9.450000
| -12.150000
|-
|
| -6.750000
| -12.150000
|-
|
| -4.050000
| -12.150000
|-
|
| -1.350000
| -12.150000
|-
|
|1.350000
| -12.150000
|-
|
|4.050000
| -12.150000
|-
|
|6.750000
| -12.150000
|-
|
|9.450000
| -12.150000
|}

Oven 4 (Thermo-Fisher HeraTherm)

2026-02-25T20:04:59Z

John d: fixed instructions link

{{tool2|{{PAGENAME}}
|picture=Oven4.jpg
|type = Lithography
|super= Michael Barreraz
|super2= Aidan Hopkins
|location=Bay 6
|description = Programmable Oven
|manufacturer = Thermo Scientific
|model = HeraTherm
|toolid=68
}}

==About==
This oven is often used for long thermal cures and wafer bonding. It has programmable temperature ramps and hold times, but the ramp rate is only "low/med./high" (not an exact ramp rate). A manual needle valve for nitrogen purge has been installed on the back of the oven.

==Specifications==

*Maximum Temperature = 330 C (no active cooling)
*Gases: N2, manually set with needle valve (not programmable)
*Multi-step programmable temperature ramps
*Programmable atmospheric purge (for cooling)

==Documentation==

* [https://wiki.nanotech.ucsb.edu/w/images/8/8e/Heratherm_instructions.pdf Instructions (from HeraTherm)]

Oxford ICP Etcher (PlasmaPro 100 Cobra)

2026-02-25T17:47:23Z

John d: /* Documentation */ sub heading to video training

{{tool2|{{PAGENAME}}
|picture=OxfordPlasmaPro.jpg
|type = Dry Etch
|super= Tony Bosch
|super2= Bill Millerski
|location=Bay 2
|description = ICP Etches for III-V/ALE
|manufacturer = [https://www.oxinst.com Oxford Instruments]
|materials = InP, GaAs, GaN, Silicon ALE
|model = PlasmaPro 100 Cobra 300
|toolid=
}}
==About==

The Oxford PlasmaPro 100 Cobra 300 is intended for etching InP-based, GaAs-baased and GaN-based epitaxies, in addition to Atomic Layer Etching (ALE) processes.
The system has a load lock, wide temperature range with rapid heating/cooling, Inductively Coupled Plasma (ICP) coil and a capactively coupled substrate HF (13.56MHz)
The fixturing is configured for 4" diameter Si wafers and uses a clamp to hold the sample on the RF chuck. Small pieces may be placed on Silicon carrier wafers, with or without mounting adhesive. Helium back-side cooling is used to keep the sample cool during the etch, but pieces do heat up when placed on carriers.

The in-situ laser monitor installed on this system allows for repeatable etches and endpoint detection via continuous optical monitoring of the wafer reflectivity in a user-determined location, through a porthole on the chamber.
The system also has an ''in situ'' optical emission monitor for plasma spectroscopy, utilized for chamber clean endpoint detection.

==Detailed Specifications==

*Temperature Range: –150°C to +400°C
*Gases Available: CH4, H2, Ar, Cl2, BCl3, SF6, SiCl4, O2, N2
*ICP Power (max): 3000 W
*RF Power (max): 600 W
*He-back-side cooling
*100mm wafer held down with ceramic clamp., single-load
**Users may place pieces onto carrier wafer with or without adhesive. Standard recipes use no adhesive.
**Pieces must be >7mm from edge of carrier to avoid wafer-clamping mechanism.
*Windows-based Cortex software control of process and wafer handling
*Allowed Materials:
**InP-based epitaxies - ''qualified and ready''
**GaAs-baased epitaxies - ''starter recipe is available''
**GaN-based epitaxies - ''starter recipe is available''
**GaSb-based epitaxies - ''starter recipe is available''
**Atomic Layer Etching on select materials - ''starter recipe is available''
*Standard masking materials include:
**SiO2
**Si3N4
**photoresist (at << 100°C).

Other materials can be exposed to the chamber only with staff approval.

*Laser monitoring with camera and etch simulation software: [[Laser Etch Monitoring|Intellemetrics LEP 500]]
*Optical Emission Spectroscopy (Ocean Optics) for endpoint detection of chamber cleans & etches - integrated into Oxford software

==Documentation==

*{{file|Oxford_Cobra_300_SOP_v2021-12-14.pdf|Oxford PlasmaPro Operating Instructions|}}
**''Includes "Travelers" and post-cleaning for each type of standard etch (InP, GaAs, GaN)''
*[[Laser Etch Monitoring|Laser Etch Monitoring procedures]]

==== Online Training Video: ====
*[https://gauchocast.hosted.panopto.com/Panopto/Pages/Viewer.aspx?id=de1bb5fd-628f-4e70-b820-ae13010ee80b Oxford Cobra 300 Training]
*'''Important:''' ''This video is for reference only, and does not give you authorization to use the tool. You must be officially authorized by the supervisor before using this machine.''

==Recipes==

=== '''[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford PlasmaPro Recipes]]''' ← Recipes specific to this tool. ===
*All [[Dry Etching Recipes]] - use this list to see other options for dry etching various materials.

=== [[ICP Etching Recipes#Process Control Data .28Oxford ICP Etcher.29|Process Control Data]] ===
''Click above for calibration etch data for verifying tool performance over time.''

=== High-Temp (200°C) InP Etch Process ===

* InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
** Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
** Very dependent on open area, more area => lower E.R.s
** Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
** Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''

* [https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
* [https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

==== [https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Std InP Ridge Etch: Cl2/CH4/H2/60°C] ====
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

''No longer calibrating 60°C process as of 05-2025.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

==== GaN Etch (Cl2/BCl3/Ar/200°C) ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''
* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.

* CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data
* CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots

OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiO2 mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]]<hr style="height:5px">

Flip-Chip Bonder (Finetech)

2026-02-18T18:12:53Z

John d:

{{tool2|{{PAGENAME}}
|picture=FinetechFlip.jpg
|type = Packaging
|super= Tony Bosch
|super2= Bill Millerski
|location=Bay 3
|description = Finetech Flip Chip Bonder
|manufacturer = [http://www.finetechusa.com/bonders/products/fineplacerr-lambda.html Finetech]
|materials =
|toolid=40
}}
= About =
The Finetech Fineplacer Lambda tool is designed for flip-chip bonding of two parts with an alignment accuracy of about 1um. The system is a semiautomatic bonder with full computer control of the bonding parameters and an integrated side-camera system for observation during the bond.

Sample sizes as small as 500um on a side to as large as 50mm on a side can be accommodated.

Forces from as small as 0.3N to as large as 500N can be applied to the parts.

Ultrasonication is also available.

Bonding temperatures up to 400C are possible.

The system also has a formic acid module (reduced atmosphere environment) that is used to prevent oxide formation during heated indium bonding.