UCSB Nanofab Wiki - User contributions [en]

Noah Dutra

2026-10-09T22:36:05Z

Noahdutra:

{{staff|{{PAGENAME}}
|position = Process Engineer
|room = 1109F
|phone = (805) 893-5052
|cell =
|email = noahdutra@ucsb.edu
}}
==About==
Noah is a Process Engineer at the UCSB NanoFab. He earned his degree in Chemical Engineering from UCSB in 2023, where he distinguished himself with the top capstone design project of his cohort. During his undergraduate studies in 2022, Noah was among the first interns at the UCSB NanoFab, marking his initial exposure to semiconductor engineering. This experience inspired him to accept a position as a Semiconductor Process Engineer at Lockheed Martin/Santa Barbara Focalplane in Goleta, where he contributed to the production of infrared focal plane arrays for military and space applications. Driven by the dynamic environment and opportunities at the UCSB NanoFab, Noah rejoined the facility in 2024. As of 2026, Noah is currently pursuing a Masters of Science degree in Electronics and Photonics at UCSB.

==Current Work==
In his current role, Noah focuses on process development to support both the NanoFab as well as local companies. He is one of two process staff members directly involved with the CA DREAMS initiative, which includes leveraging analytics software to enhance SPC on laboratory tools. Noah also oversees and mentors undergraduate interns responsible for process calibrations while developing new ones himself to benefit lab users.

==Tools==
Noah is the supervisor for the following tools:

*TBD

==External Professional Websites==

*[https://www.linkedin.com/in/noah-dutra-703777215 LinkedIn]

OLD Direct-Write I-Line Recipes

2026-09-25T22:41:40Z

Noahdutra: changed bake times to 60s for SPR955

==[[Maskless Aligner (Heidelberg MLA150)]]==
Photolithography Recipes for the [[Maskless Aligner (Heidelberg MLA150)|Heidelberg MLA150]]. ''Description of litho params- different lasers available, greyscale etc.''
===Positive Resist (MLA150)===
''General notes: Hotplates used, filters, laser wavelengths, etc. “Soft Bake” is right after spin, “PEB” is post-exposure bake - right after exposure''
{| class="wikitable" border="1" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Soft Bake
! width="75" |Thickness
!Laser (nm)
! width="125" |Exposure Dose (mJ/cm2)
! width="100" |DeFocus
! width="75" |Post-Exposure Bake
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[:File:AXP4000pb-Datasheet.pdf|AZ4110]]
|4 krpm/30s
|95°C/60s
|~ 1.1 µm
|405
|240
|5
|''none''
|AZ400K:DI 1:4
|50s
|Used MLA design (good for isolated lines 0.8-1um)
|-
|[[:File:AXP4000pb-Datasheet.pdf|AZ4330]]
|4 krpm/30s
|95°C/60s
|~ 3.3 µm
|405
|320
|6
|''none''
|AZ400K:DI 1:4
|90s
|Used MLA design
|-
|[[:File:Az p4620 photoresist data package.pdf|AZ4620]]
|
|
|
|
|
|
|
|
|
|
|-
|[[:File:SPR220-Positive-Resist-Datasheet.pdf|SPR 955 1.8]]
|4 krpm/30s
|95°C/60”
|~1.8 µm
|405
|210
| 10
|110°C/60s
|AZ300MIF
|60s
|UCSB design (good for dense lines~1um)
|-
|[[:File:SPR220-Positive-Resist-Datasheet.pdf|SPR 220-3.0]]
|2.5 krpm/30s
|115°C/90”
|~ 2.7 µm
|405
|325
| - 4
|115°C/90s
|AZ300MIF
|60s
|Used MLA design
|-
|[[:File:SPR220-Positive-Resist-Datasheet.pdf|SPR 220-7.0]]
|3.5 krpm/30s
|115°C/2m
|~7 µm
|405
|440
|5
|50°C/1m, ramp up, 115°C/90s
|AZ300MIF
|70s
|UCSB design 1um pillars/5um trenches]
|-
|[[:File:SPR955-Positive-Resist-Datasheet.pdf|SPR 955-CM0.9]]
|3 krpm/30s
|95°C/60”
|~ 0.9 µm
|405
|250
| - 7
|110°C/60s
|AZ300MIF
|60s
|Used MLA design, [for 5um pillars/1um trench:150/5]
|-
|[[:File:3600 D, D2v Spin Speed Curve.pdf|THMR-3600HP]]
|1.5 krpm/45s250 rpm/s
|100°C/60s
|0.430µm
|405
|180–220
|<nowiki>-4</nowiki>
|100°C/60s
|AZ300MiF
|20s
|line/space:
low dose for clear-field, high does for dark-field
|-
|[[:File:3600 D, D2v Spin Speed Curve.pdf|THMR-3600HP]]
|6 krpm/30sec
|100°C/60s
|0.260µm
|405
|190
|<nowiki>-4</nowiki>
|100°C/60s
|AZ300MiF
|20s
|Big pattern (>2um), dense
|}

===Negative Resist (MLA150)===
''General notes: Hotplates used, filters, laser wavelengths, etc. “Soft Bake” is right after spin, “PEB” is post-exposure bake - right after exposure. “Flood exposure” is only for AZ5214 for image reversal, after PEB.''
{| class="wikitable" border="1" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Soft Bake
! width="75" |Thickness
!Laser (nm)
! width="125" |Exposure Dose (mJ/cm2)
! width="100" |DeFocus
! width="75" |PEB
! width="75" |Flood
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[:File:AZ5214-Negative-Resist-Datasheet.pdf|AZ5214]]
|6 krpm/30s
|95°C/60s
|~ 1.0 µm
|375
|35
| - 5
|110°C/60s
|60"
|AZ300MIF
|60s
|Used UCSB design. Good for up to ~1.3um open line space.
|-
|AZnLOF2020
|4 krpm/30s
|110°C/60s
|~ 2.1µm
|375
|340
| - 3
|110°C/60s
|''none''
|AZ300MIF
|90s
|Used UCSB design. Good for 2um open line space.
|-
|[[:File:SU-8-2075-revA.pdf|SU-8 2075]]
|
|
|~70µm
|375
|
|
|
|
|
|
|Extremely viscous. Pour into a wide-mouthed bottle, dispense directly from bottle. Replace napkin at end.
|}
===Greyscale Lithography (MLA150)===
''Description...''
{| class="wikitable" border="1" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
! width="75" |Laser
! width="125" |Exposure Dose (mJ/cm2)
! width="100" |Focus Offset
! width="75" |Rehydrate
! width="75" |PEB
! width="75" |Flood
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|AZ4620
|– krpm/30”
|95°C/60”
|
|
|
|
|
|60"
|AZ300MIF
|60"
| align="left" |
*TBD
|-
|SPR 220-7
|–3.5krpm/30”
|105°C/120” Cool 1min
|~7um
|375
|624mJ to clear large mm area, 520mJ to clear ~5um lines
|neg 20
|>1hr
|115C/90s
|AZ300MIF
|70s
|align="left"|
*TBD
|Rehydration after exposure is necessary, to prevent bubbles at PEB
|}

Stepper Recipes

2026-09-25T22:37:50Z

Noahdutra:

{{recipes|Lithography}}
[[category: Lithography]]

Below is a listing of stepper lithography recipes.
Stepper 1 and Stepper 2 are i-line systems with good piece handling capabilities.

Stepper 3 is a DUV (248nm) system primarily used for full 100mm wafers. DUV resists do not work for i-line and i-line resists do not work for DUV.

This listing is a guideline to get you started. For critical lithography steps, you should run your own exposure and/or focus array to determine the proper parameters. Based on your sample reflectivity, absorption (or whether or not you use an ARC layer), and surface topography, the exposure time / focus offset parameters may vary.

The recipes are tabulated to give you the values of the key parameters you will need to establish your recipe. Underlayers such as LOL2000 or PMGI can be used on the stepper systems. See the underlayer datasheets for details. Post develop bakes (not listed) are used to make the resist more etch resistant and depend on subsequent processes. Care should be taken with post development bakes as resist reflow can occur. Unless otherwise noted, all exposures are done on flat, silicon wafers.

Parameters are indicated in separate tables for each stepper system.

__TOC__

=[[Stepper 1 (GCA 6300)]]=

Multiply the GCA 6300 exposure times by 0.30 to get a starting exposure time for the GCA Autostep200 system.

==Positive Resist (GCA 6300)== 

Unless otherwise noted, bakes are on hot plates. For recipes with CEM, the CEM is spun on after the first resist bake, exposure is then done, and the CEM is rinsed off with DI water before the PEB. CEM generally improves resolution and process tolerance at the expense of higher exposure time.

{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
! width="125" |Exposure Time
! width="100" |Focus Offset
! width="75" |PEB
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[Media:SPR955-Positive-Resist-Datasheet.pdf|SPR955CM0.9]]
|3 krpm/30”
|95°C/60”
|~ 0.9 um
|1.2”
|0
|110°C/60”
|AZ300MIF
|60"
| align="left" |
*0.5 um isolated lines
*{{fl|SPR955CMstepperrecipe.pdf|See SPR955CM data file}}

|-
|[[Media:SPR955-Positive-Resist-Datasheet.pdf|SPR955CM-0.9]]
|3 krpm/30”
|95°C/60”
|~ 0.9 um
|3.0”
|4
|110°C/60”
|AZ300MIF
|60"
| align="left" |
*0.5 um holes
*Much longer exposure time for dense isolated holes
*{{fl|SPR955CMstepperrecipe.pdf|See SPR955CM data file}}

|-
|[[Media:SPR955-Positive-Resist-Datasheet.pdf|SPR955CM-0.9]] 
[[Media:CEM365iS-Contrast-Enhancement-Datasheet.pdf|CEM365iS]]
|3 krpm/30” 
5 krpm/30”
|95°C/90”
|~ 0.9 um
|2.2”
| -10
|110°C/60”
|AZ300MIF
|60"
| align="left" |
*0.35um isolated spaces by SEM measurement.
*Higher exposure time due to CEM
*{{fl|SPR955CMstepperrecipe.pdf|See SPR955CM data file}}

|-
|SPR950-0.8
|4 krpm/30”
|95°C/60”
|~ 0.8 um
|1.0”
|0
|105°C/60”
|AZ300MIF
|60"
| align="left" |

|-
|[[Media:SPR955-Positive-Resist-Datasheet.pdf|SPR955CM-1.8]]
|4 krpm/30”
|90°C/90”
|~ 1.8 um
|2.3”
|0
|110°C/90”
|AZ300MIF
|60"
| align="left" |
*0.5 um isolated lines
*{{fl|spr955_1.8GCA6300.pdf|See 955CM-1.8 data file}}

|-
|[[Media:SPR955-Positive-Resist-Datasheet.pdf|SPR955CM-1.8]]
|4 krpm/30”
|90°C/90”
|~ 1.8 um
|1.7”
| -5
|110°C/90”
|AZ300MIF
|60"
| align="left" |
*1 um isolated posts
*{{fl|spr955_1.8GCA6300.pdf|See 955CM-1.8 data file}}

|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR220-3.0]]
|2.5 krpm/30”
|115°C/90”
|~ 2.7 um
|2.4”
|10
|115°C/90”
|AZ300MIF
|60"
| align="left" |
*0.5 um isolated lines
*{{fl|SPR-220-3.0_OptimizationNew.pdf|See SPR220-3 Data File}}

|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR220-7.0]]
|3.5 krpm/45”
|115°C/120”
|~ 7.0 um
|4.5”
|0
|*50°C/60” 
115°C/90”

|AZ300MIF
|120"
| align="left" |
*1.0 um isolated lines; 1.25 um isolated spaces
**Let sample sit in air for 20 minutes before PEB, step to 50°C for 60” first, then 115°C
*{{fl|SPR-220-7.0stepperrecipe.pdf|See SPR220-7 Data File}}

|}

==Negative Resist (GCA 6300)== 

Unless otherwise noted, bakes are on hot plate. All flood exposures are done in broadband light using any contact aligner. Also, because the tone is negative, a shorter first exposure time will result in more undercut, which is desirable for single-layer lift-off processes. Under these conditions more develop time will also give more undercut.

{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
! width="125" |Exposure Time
! width="100" |Focus Offset
! width="75" |PEB*
! width="75" |Flood**
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[Media:AZ5214-Negative-Resist-Datasheet.pdf|AZ5214]]**
|6 krpm/30”
|95°C/60”
|~ 1.0 um
|0.2”
|0
|110°C/60”
|60"
|AZ300MIF
|60"
| align="left" |
*0.7 um res. possible 

|-
|[[Media:AZnLOF5510-Negative-Resist-Datasheet.pdf|nLOF5510]]
|3 krpm/30”
|90°C/60”
|~ 0.93 um
|0.74”
| -6
|110°C/60”
|none
|AZ300MIF
|60"
| align="left" |
*0.5 um line openings good dense or isolated
*Use heated 1165 stripper for removal or lift-off
*{{fl|nLOF5510stepperrecipe.pdf|See nLOF5510 data file}}

|-
|[[Media:AZnLOF2020-Negative-Resist-Datasheet.pdf|nLOF2020]]
|4 krpm/30”
|110°C/60”
|~ 2 um
|0.55”
| -6
|110°C/60”
|none
|AZ300MIF
|90"
| align="left" |
*~ .85 um line opening/lift-off good. Isolated mesas can be smaller.
*Use heated 1165 stripper for removal or lift-off Sensetive to PEB temp.
*{{fl|nLOF2020stepperrecipe.pdf|See nLOF2020 Data File}}
|-
| colspan="11" |* PEB: post-exposure bake. For AZ 5214-IR, this performs Image Reversal
<nowiki>**</nowiki> To use AZ5214 as a negative PR requires Flood Exposure with the [[Contact Aligner (SUSS MA-6)|MA6]] or [[Suss Aligners (SUSS MJB-3)|MJB]] aligner '''''after PEB''''', before developing. See here for a [[AZ5214 - Basic Process|basic AZ5214 process]], it is different than typical negative resists.
|}

=[[Stepper 2 (AutoStep 200)]]=

==Positive Resist (AutoStep 200)== 
Unless otherwise noted, bakes are on hot plates. For recipes with CEM, the CEM is spun on after the first resist bake, exposure is then done, and the CEM is rinsed off with DI water before the PEB. CEM generally improves resolution and process tolerance at the expense of higher exposure time.

'''NOTE''': The bolded exposure times were found by multiplying the exposure times from the GCA 6300 system by 0.30. They should be sued as a starting point. You will need to do an exposure array to get precise times for the Autostep system. In general, the resolution achievable is ~ 100 nm smaller for the Autostep200 system.

{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
! width="125" |Exposure Time
! width="100" |Focus Offset
! width="75" |PEB
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[Media:SPR955-Positive-Resist-Datasheet.pdf|SPR955CM-0.9]]
|3 krpm/30”
|95°C/90”
|~ 0.9 um
|0.35”
|0
|110°C/90”
|AZ300MIF
|60”
| align="left" |
*0.5um dense lines
*{{fl|SPR955-0.9-AS200-stepperrecipe.pdf|See SPR955CM AS200 data file}}

|-
|[[Media:SPR955-Positive-Resist-Datasheet.pdf|SPR955CM-0.9]]
|3 krpm/30”
|95°C/90”
|~ 0.9 um
|0.8”
|0
|110°C/90”
|AZ300MIF
|60”
| align="left" |
*0.5um holes

|-
|[[Media:SPR955-Positive-Resist-Datasheet.pdf|SPR955CM-1.8]]
|4 krpm/30”
|95°C/90”
|~ 1.8 um
|0.4”
| -1
|110°C/90”
|AZ300MIF
|60”
| align="left" |
*{{fl|SPR955-1.8-AS200-stepperrecipe.pdf|See SPR955-1.8 AS200 data file}}

|-
|SPR950-0.8
|4 krpm/30”
|95°C/90”
|~ 0.8 um
|'''0.30”'''
|0
|105°C/90”
|AZ300MIF
|60"
| align="left" |
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR220-3.0]]
|2.5 krpm/30”
|115°C/90”
|~ 2.7 um
|'''0.72”'''
|10
|115°C/90”
|AZ300MIF
|60"
| align="left" |
*0.5 um isolated lines

|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR220-7.0]]
|3.5 krpm/45”
|115°C/120”
|~ 7.0 um
|'''1.35"'''
|0
|*50°C/60” 
115°C/90”

|AZ300MIF
|120"
| align="left" |
*1.0 um isolated lines; 1.25 um isolated spaces
**Let sample sit in air for 20 minutes before PEB, step to 50°C for 60” first, then 115°C

|-
|[[Media:AXP4000pb-Datasheet.pdf|AZ4210]]
|step1:500rpm/5", step2:4krpm/45”
|95°C/60"
|~ 2.1 um
|'''0.75"'''
|0
|

|AZ400K:DI=1:4
|60"
| align="left" |
*2.0 um dense holes

|}

==Negative Resist (AutoStep 200)== 
Unless otherwise noted, bakes are on hot plate. All flood exposures are done in broadband light using any contact aligner. Also, because the tone is negative, a shorter first exposure time will result in more undercut, which is desirable for single-layer lift-off processes. Under these conditions more develop time will also give more undercut.

'''NOTE''': The bolded exposure times were found by multiplying the exposure times from the GCA 6300 system by 0.30. They should be sued as a starting point. You will need to do an exposure array to get precise times for the Autostep system. In general, the resolution achievable is ~ 100 nm smaller for the Autostep200 system.

{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
! width="125" |Exposure Time
! width="100" |Focus Offset
! width="75" |PEB*
! width="75" |Flood**
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[Media:AZnLOF5510-Negative-Resist-Datasheet.pdf|nLOF5510]]
|3 krpm/30”
|90°C/60”
|~ 0.93 um
|.25”
| -1
|110°C/60”
|0
|AZ300MIF
|60”
| align="left" |
*0.4 um lines dense good
*Use heated 1165 stripper for removal or lift-off
*{{fl|nLOF5510-AS200-stepperrecipe.pdf|See nLOF5510 As200 data file}}

|-
|[[Media:AZ5214-Negative-Resist-Datasheet.pdf|AZ5214]]**
|6 krpm/30”
|95°C/60”
|~ 1.0 um
|'''0.06”'''
|0
|110°C/60”
|60"
|AZ300MIF
|60"
| align="left" |
*0.7 um res. possible

|-
|[[Media:AZnLOF2020-Negative-Resist-Datasheet.pdf|nLOF2020]]
|4 krpm/30”
|110°C/60”
|~ 2 um
|'''0.17”'''
| -6
|110°C/60”
|0
|AZ300MIF
|90"
| align="left" |
*~ .85 um line opening/lift-off good. Isolated mesas can be smaller.
*Use heated 1165 stripper for removal or lift-off Sensetive to PEB temp.
|-

|[[Media:NR9-1000PY-revA.pdf|NR9-1000PY]]
|3 krpm/30”
|135°C/180” lid down
|~ 1.2 um
|'''0.92”'''
|0
|115°C/120” lid down
|0
|AZ300MIF
|20"
| align="left" |
*~ .55 um line opening/lift-off good.
*Use heated 1165 stripper for removal 8Hrs min.
*{{fl|NR9-1000PY-AS200-stepperrecipe.pdf|See NR9-1000PY As200 data file}}
|-
| colspan="11" |*PEB: post-exposure bake. For AZ 5214-IR, this performs Image Reversal
<nowiki>**</nowiki> To use AZ5214 as a negative PR requires Flood Exposure with the [[Contact Aligner (SUSS MA-6)|MA6]] or [[Suss Aligners (SUSS MJB-3)|MJB]] aligner '''''after PEB''''', before developing. See here for a [[AZ5214 - Basic Process|basic AZ5214 process]], it is different than typical negative resists.
|}

=[[Stepper 3 (ASML DUV)]]=
{| class="wikitable"
!Stepper 3: Table of Contents (DUV)
|-
|
#[[Stepper_Recipes#Process_Control_Data|Process Control Data]]
#[[Stepper Recipes#General Litho + Recipe Info|General Litho + Recipe Info]]
#[[Stepper Recipes#Photomasks .26 Job Programming|Photomasks & Job Programming]]
#[[Stepper Recipes#Anti-Reflective Coatings|Anti-Reflective Coatings]]
#[[Stepper Recipes#Positive Resist .28ASML DUV.29|Positive Resist]]
#[[Stepper Recipes#Negative Resist .28ASML DUV.29|Negative Resist]]
#[[Stepper Recipes#Other Lithography Processes .28ASML DUV.29|Other Lithography Processes]]
##Edge Bead Removal
##Lift-off Processes
##FEM Analysis
|}

==Process Control Data==

*''The Process Group regularly measures data on lithography Critical Dimension ("CD") and Wafer-stage Particulate Contamination for this tool, using a sensitive lithography process that will reveal small changes in Dose repeatability and wafer flatness.''
*[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281 '''Plots of CD Repeatability''']
*[https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0 '''Data for CD Uniformity and Particulate Contamination''']

:{|
|[[File:ASML CD Cals - Example Table.jpg|alt=ASML CD Calibration data - Screenshot of Table|none|thumb|300x300px|''Example of Data Table with SEM's of 320nm features. [https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0 Click for full data table.]''|link=https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=0]]
|[[File:ASML CD Cals - Example Plot.jpg|alt=ASML CD Calibration Data - Screenshot of SPC Plot|none|thumb|''Example SPC Chart - Measured Critical Dimension "CD" versus Date. [https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281 Click for charts.]''|link=https://docs.google.com/spreadsheets/d/1xW1TFH_QjPMWl9T1jiKzwmYe4B2wg7KY-nqOKUoXttI/edit#gid=1804752281]]
|}

=== Particle Checks ===
Our cal process enables both ~300nm critical dimension logging, and also allows us to see when a particle is present on the exposure chuck (a "hot spot").
[[File:ASML Cal Particle Check.png|alt=Image showing 2 wafers with colorful rainbow patterns, both show a black spot on the right side.|none|thumb|Both wafers show a "hot spot" on the left side, so the tool has a particle at that location, requiring physical cleaning. (''Demis D. John, 2024'')]]
==General Litho + Recipe Info==

=== Photomasks & Job Programming ===
You can find info on making photomasks, CAD files for alignment marks, and other Job programming tools on the main Tool page, here:

[[Stepper 3 (ASML DUV)#Design%20Tools|Stepper 3 (ASML DUV) > Design Tools]]

=== ASML Focus movement ===
A positive focus offset moves the wafer stage upwards, closer to the lens.

=== Feature Size vs. Dose ===
The ASML tends to give fine control over feature size via variations in Exposure Dose (mJ/cm2). One such process is plotted here, for 200nm fixed hole size on the mask plate:
[[File:ASML Dose vs Hole Diam - AT230829.png|none|thumb|484x484px|Plot of Dose vs. Hole Diameter for UV6-0.8 (credit: [[Foong Fatt]] & [[Demis D. John]])]]

=== BARC (Anti-Reflection Coating) Etching ===
The DUV42P BARC layer, which is best suited for resolving small features, needs to be O2 etched after develop.

Counter-intuitively, this does ''not'' lead to your total resist thickness being significantly thinner, as explained in [https://www.fabublox.com/process-editor/e70f6d97-b27b-4c05-ac45-479cec8a9f0b this FabuBlox process schematic] (login may be required to view). (Provided you do not overetch by an excessive amount.)

"BARC" and "ARC" etches have been written/test and are available on all our primary etchers.

Here are links to the recipes for each etcher: [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_Etching_.28Panasonic_1.29 ICP#1], [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 ICP#2], [https://wiki.nanotech.ucsb.edu/w/index.php?title=RIE_Etching_Recipes#Photoresist_and_ARC_.28RIE_5.29 RIE#5], [https://wiki.nanotech.ucsb.edu/wiki/ICP_Etching_Recipes#Photoresist_.26_ARC_.28Fluorine_ICP_Etcher.29 FL-ICP] & [[Ashers (Technics PEII)|Technics PEii ashers]].

==Anti-Reflective Coatings==
Bottom Anti-reflective coatings (aka. BARC or AR Coating) are, in general, used for the ASML stepper. LOL2000 and PMGI can also be used as under layers. BARC layers will increase the process tolerance, especially for features ≤ wavelength (248nm).

For example, without BARC you might find that 200nm features only resolve with focus of -0.2µm to -0.3µm, while with BARC the process tolerance may increase to -0.1µm to -0.4µm, which also increases tolerance to wafer flatness/PR spin uniformity.

====[https://wiki.nanotech.ucsb.edu/wiki/images/0/07/DUV42P-Anti-Reflective-Coating.pdf <big>DUV-42P-6</big>]====
''(replacement for AR2)''

*spin coat at 2500rpm for optimal anti-reflective properties (~60nm).
**Mistake: this was previously written as 3500rpm.
*Bake at 220°C for 60s on a hotplate.
*This AR coating is removed via oxygen plasma.
*This ARC can be etched on [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_Etching_.28Panasonic_1.29 ICP#1], [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 ICP#2], [https://wiki.nanotech.ucsb.edu/w/index.php?title=RIE_Etching_Recipes#Photoresist_and_ARC_.28RIE_5.29 RIE#5], [https://wiki.nanotech.ucsb.edu/wiki/ICP_Etching_Recipes#Photoresist_.26_ARC_.28Fluorine_ICP_Etcher.29 FL-ICP] or even [[Ashers (Technics PEII)|Technics PEii ashers]].
*Datasheet: '''[https://wiki.nanotech.ucsb.edu/wiki/images/0/07/DUV42P-Anti-Reflective-Coating.pdf DUV-42P-6]'''

====[https://wiki.nanotech.ucsb.edu/wiki/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf <big>DS-K101-304</big>]====

*Spin at 1500rpm and bake at 185°C for 60sec
**Approx 40nm for best anti-reflective properties
**Mistake: previously written as 5000rpm, ~20nm thickness (from DS-K101-307)
*This AR coating develops away and undercuts in AZ300MIF.
**For isolated lines, this can cause them to lift-off by undercutting the resist.
*Increase bake temperature to reduce undercut rate.
**[[DS-K101-304 Bake Temp. versus Develop Rate]] - Click for experimental data
**Can be used similarly to DUV42P (dry etch removal) by baking at 220°C.
*Datasheet: '''[https://wiki.nanotech.ucsb.edu/wiki/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101-304]'''

==Positive Resist (ASML DUV)==
Please see section above for anti-reflection coatings, which are usually used with the DUV Stepper.

{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
! width="125" |Exposure Dose(mj)
! width="100" |Focus Offset
! width="75" |PEB
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|UV6-0.7 (replaced by [[Media:UV6-Positive-Resist-Datasheet.pdf|UV6-0.8]])

|3.5 krpm/30”
|135°C/60”
|630nm
|17
| -0.2
|135°C/90”
|AZ300MIF
|45”
| align="left" |
*200nm dense line/space
*NA 0.57, Sigma 0.75
*Eo ~ 5.5mj
*UV6-0.7 was discontinued, we now stock UV6-0.8

|-
|[[Media:UV210-Positive-Resist-Datasheet.pdf|UV210-0.3]]
|5.0 krpm/30”
|135°C/60”
|230nm
|20
| -0.1
|135°C/90”
|AZ300MIF
|45"
| align="left" |
*150nm dense line/space
*'''Annular Illumination'''
*NA 0.63, Sigma_o 0.8, Sigma_i 0.5

|-
|[[Media:UV210-Positive-Resist-Datasheet.pdf|UV210-0.3]]
|3.0 krpm/30”
|135°C/90”
|260nm
|85
| -0.2
|135°C/90”
|AZ300MIF
|80”
| align="left" |
*170nm isolated holes
*'''Annular Illumination'''
*NA 0.63, Sigma_o 0.8, Sigma_i 0.5
|-
|[[Media:UV26-Positive-Resist-Datasheet.pdf|UV26-2.5]]
|''Available but no recipes characterized''
|135°C/90s
|~2.5 µm
|approx. 40
|approx. +0.8
|110°C/90s
|AZ300MiF
|Unknown
|Users must run your own development/FEM's.
|}

==Negative Resist (ASML DUV)==
Please see section above for anti-reflection coatings, which are usually used with the DUV Stepper.

{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
! width="125" |Exposure Dose (mj)
! width="100" |Focus Offset
! width="75" |PEB
! width="75" |Flood
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[Media:UVN-30 - Negative-Resist-Datasheet - Apr 2004.pdf|UVN30-0.8]]
|3.5 krpm/30”
|110°C/60”
|~550nm
|27
| +0.15
|105°C/60”
|Not Used
|AZ300MIF
|Approx. 20sec
(not thoroughly calibrated)
| align="left" |
*Replaced UVN2300, not identical. Dev time was 55-60 sec.

|}

==Other Lithography Processes (ASML DUV)==

*[[ASML DUV: Edge Bead Removal via Photolithography|DUV Photolithographic Edge Bead Removal]]
*[[Lift-Off with DUV Imaging + PMGI Underlayer|DUV Lift-Off Process with PMGI Underlayer]]
* [[Lithography Calibration - Analyzing a Focus-Exposure Matrix|Lithography Calibration - Analyzing a Focus-Exposure Matrix (FEM)]] - Projection litho systems (steppers, direct-writers) usually require a lithography calibration, using a Focus-Exposure Matrix/Array (FEM/FEA).

Direct-Write Lithography Recipes

2026-09-25T22:32:18Z

Noahdutra: /* Positive Resist (Raith PicoMasterXF) */

[[category: Lithography]]
[[category: Recipes]]
__TOC__

==[[Maskless Aligner (Heidelberg MLA150)]]==
For CAD design tips and requirements, see these pages:

*[[MLA150 - Design Guidelines|Design Guidelines + Tips]] - ''useful info for designing your CAD files, alignment marks etc.''
*[[MLA150 - CAD Files and Templates|CAD Files and Templates]] - example CAD files etc.

Photolithography Recipes for the [[Maskless Aligner (Heidelberg MLA150)|Heidelberg MLA150]]. All recipes were characterized on blank Silicon wafers. For different substrate coatings/materials, you will likely need to run a focus-exposure matrix ("series" exposure mode), using our params as a starting point.

These recipes use the same spin and bake params as our contact aligner and stepper recipes, using built-in hotplates on the photoresist spinner benches.

'''''Any I-Line PR is usable''''', although we only characterized a select few below. Run your own Focus-Exposure Matrix to characterize a new PR.

'''Note:''' On this tool, it is common to have to run a Focus-Exposure Matrix (aka. FEM), via "''Series''" exposure mode, for each new layer structure and/or critical feature size. The layer structure can strongly affect the exposure parameters. See the [[ASML Stepper 3 Standard Operating Procedure#Tips for FEM analysis|FEM Analysis Tips page]] for how to choose the proper exposure parameters.

The [[MLA150 - Troubleshooting#Out Of Focus Exposures|'''MLA''' '''Troubleshooting > Out-of-Focus Exposures''']] section can help you avoid bad exposures, please read it!

===Positive Resist (MLA150)===
''We found that positive PR's worked well with the 405nm laser - the 375nm laser would likely also work. Sub-micron features are possible. Overexposure is recommended to avoid stitching and horiz/vert discrepancies; compensate for widening/narrowing using CD Bias [[MLA150 - Design Guidelines#High-Resolution Writing|as described here]].''

Note: calibrations done with the "HIMT design" will show higher dose, due to using only dark-field line/space patterns.

{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
!Laser (nm)
! width="125" |Exposure Dose (mJ/cm2)
! width="100" |DeFocus
!Rehydrate*
! width="75" |PEB**
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[Media:AXP4000pb-Datasheet.pdf|AZ4110]]
|4 krpm, 30s
|95°C, 60s
|~ 1.1 µm
|405
|240
|5
|
|''none''
|AZ400K:DI 1:4
|50s
|Used HIMT design (good for isolated lines 0.8-1um)
|-

|[[Media:AXP4000pb-Datasheet.pdf|AZ4330]]
|4 krpm, 30s
|95°C, 60s
|~ 3.3 µm
|405
|320
|6
|
|''none''
|AZ400K:DI 1:4
|90s
|Used HIMT design
|-
|[[Media:AXP4000pb-Datasheet.pdf|AZ4620]]
|
|
|
|
|
|
|
|
|
|
|
|-
|[[Media:SPR955-Positive-Resist-Datasheet.pdf|SPR 955-CM0.9]]
|3 krpm, 30s
|95°C, 60s
|~ 0.9 µm
|405
|250
| - 7
|
|110°C, 60s
|AZ300MIF
|60s
|Used by UCSB Staff for tool calibrations/process control.
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR 955-1.8]]
|4 krpm, 30s
|95°C, 60s
|~ 1.8 µm
|405
|210
|10
|
|110°C, 60s
|AZ300MIF
|60s
|Used UCSB design (1um dense lines)
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR 220-3.0]]
|2.5 krpm, 30s
|115°C, 90s
|~ 2.7 µm
|405
|325
| - 4
|
|115°C, 90s
|AZ300MIF
|60s
|Used HIMT design. 0.6-0.9µm line/space.
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR 220-7.0]]
|3.5 krpm, 30s
|105°C/2min
Cool 1min
|~ 7.0µm
|375
|~550mJ
| -20
|>1hr
|115°C, 90s
|AZ300MiF
|70s
|Rehydration after exposure is necessary, to prevent bubbles at PEB.
|-
|[[Media:3600 D, D2v Spin Speed Curve.pdf|THMR-3600HP]]
|1.5 krpm, 45s;
250 rpm/s
|100°C, 60s
|0.430µm
|405
|180–220
|<nowiki>-4</nowiki>
|
|100°C, 60s
|AZ300MiF
|20s
|~0.4nm line/space:

lower dose for clear-field, higher dose for dark-field.
|-
| colspan="12" |*''Rehydration'': After exposure, leave sample in lab air (ok to cover in tray, with tinfoil). Allows water vapor in air to diffuse into PR to complete chemical reaction.
<nowiki>**</nowiki>''PEB: Post-exposure bake'': after exposure, before develop
|}

===Negative Resist (MLA150)===
''We found that all the negative PR's we tested required the 375nm in order to be fully exposed with reasonable dose/time.''

{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
!Laser (nm)
! width="125" |Exposure Dose (mJ/cm2)
! width="100" |DeFocus
! width="75" |PEB*
! width="75" |Flood**
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[Media:AZ5214-Negative-Resist-Datasheet.pdf|AZ5214]]**
|6 krpm, 30s
|95°C, 60s
|~ 1.0 µm
|375
|35
| - 5
|110°C, 60s
|60"
|AZ300MIF
|60s
|Used UCSB design. Good for up to ~1.3um open line space.
|-
|[[Media:AZnLOF2020-Negative-Resist-Datasheet.pdf|AZnLOF2020]]
|4 krpm, 30s
|110°C, 60s
|~ 2.1µm
|375
|340
| - 3
|110°C, 60s
|''none''
|AZ300MIF
|90s
|Used UCSB design. Good for 2um open line space.
|-
|[[Media:SU-8-2075-revA.pdf|SU-8 2075]]
|
|
|~70µm
|375
|
|
|
|
|
|
|Extremely viscous. Pour into a wide-mouthed bottle, dispense directly from bottle. Replace napkin at end.
|-
| colspan="12" |*PEB: post-exposure bake. For AZ 5214-IR, this performs Image Reversal
<nowiki>**</nowiki> To use AZ5214 as a negative PR requires Flood Exposure with the [[Contact Aligner (SUSS MA-6)|MA6]] or [[Suss Aligners (SUSS MJB-3)|MJB]] aligner '''''after PEB''''', before developing. See here for a [[AZ5214 - Basic Process|basic AZ5214 process]], it is different than typical negative resists.
|}

===Greyscale Lithography (MLA150)===
''AZ4620 is the manufacturer-recommended PR for greyscale litho.''

Please see the [[MLA150 - Design Guidelines#Limitations%20.26%20Workarounds|'''MLA150 - Greyscale Design Guidelines & Limitation''']]
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
!Laser
! width="125" |Exposure Dose (mJ/cm2)
! width="100" |Focus Offset
!Rehydrate*
! width="75" |PEB**
! width="100" |Developer
! width="125" |Developer Time
!Reflow***
! width="300" |Comments
|-
|[[Media:Az p4620 photoresist data package.pdf|AZ4620]]
|? krpm/30”
|95°C, 60”
|
|
|
|
|
|
|AZ300MIF
|60s
|
| align="left" |''To Be Added''
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR 220-7.0]]
|3.5 krpm, 30s
|105°C/2min
Cool 1min
|~ 7.0µm
|375
|~624mJ to clear large mm-area,
520mJ to clear ~5µm lines.
| -20
|≥1hr
|115°C, 90s
|AZ300MiF
|70s
|TBD
|Author Credit:
*Patrick Curtis, 2022
*Biljana Stamenic 2023
*Demis D. John 2023
|-
|
| colspan="12" |Notes on SPR 220-7 Greyscale: Rehydration after exposure is necessary, to prevent bubbles at PEB.
Stitching leaves ridges in Y-direction with ~5% height of removed PR depth. Can be reduced via reflow, but significantly affects PR profile.

Author Credit: Patrick Curtis, 2022 & Biljana Stamenic 2023 & Demis D. John 2023; Please see our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publications policy]].
|-
| colspan="13" |*''Rehydration'': After exposure, leave sample in lab air (ok to cover in tray, with tinfoil). Allows water vapor in air to diffuse into PR to complete chemical reaction.
<nowiki>**</nowiki>''PEB: Post-exposure bake'': after exposure, before develop

<nowiki>***</nowiki>''Reflow'': To smooth out stitching lines. Will change sharp vertical profiles considerably, only good for gradually-sloped profiles.
|}

== [[E-Beam Lithography System (Raith EBPG 5150+)|E-Beam Lithography Recipes (Raith EBPG 5150+)]] ==

=== Electron Beam Resists Available ===
EBL Resists are custom-mixed according to user resolution needs - contact [[Bill Mitchell]] to get a bottle.

Currently available at UCSB are:
*'''PMMA''': (950K in anisole, 950K in MIBK, 495K in anisole, 50K in anisole)
**High-resolution positive polymer-based resist with relatively poor sensitivity (resolution scales directly and sensitivity scales inversely with molecular weight);
**Poor plasma etch resistance, hence used primarily to fabricate metal lines via liftoff processes (via a bi-layer resist scheme...low MW on bottom, high MW on top for single lines, or vice-versa for T-gate fabrication);
**Utilizes an inert solvent developer (usually MIBK:IPA mixtures)

*'''P(MMA-MAA) copolymer''': (low MW methyl-methacrylate (MMA) and methacrylic acid (MAA) copolymers in ethyl lactate)
**A positive polymer-based resist with poor resolution but with significantly higher sensitivity than the higher MW PMMA resists above
**Used primarily as the top layer in a bi-layer resist scheme for T-Gate fabrication, and utilizes inert solvent developer (MIBK:IPA mixtures)

*'''CSAR-62''': ZEP-equivalent resist manufactured in Germany at much more competitive pricing!
**High-resolution polymer-based positive resist with very good sensitivity and excellent etch resistance
**Can be used in both metal lift-off processes (slight overexposure results in an excellent undercut profile) and various dry-etch processes for pattern transfer to the underlying substrate
**Utilizes inert solvent developers (e.g., n-amyl acetate for higher sensitivity and good resolution or MIBK:IPA mixtures for increased LER performance)

*'''maN-2403''': negative polymer-based resist (that is NOT chemically amplified)
**Very good resolution (down to the 40-50nm range) and sensitivity
**Exhibits excellent dry-etch resistance
**Developed using a dilute basic solution (e.g., metal-ion-free developers such as AZ-300MIF)

*'''HSQ''': negative resist that is based on spin-on glass material (ie, not polymer-based)
**Extremely good resolution (features below 10nm can be resolved)
**Etch resistance is high in Cl-based chemistries since HSQ reduces to a porous SiOx structure after exposure and development
**Sensitivity and contrast are very dependent on developer solution used and are usually poor
***Standard AZ300MIF developer solutions have decent sensitivity (100's of uC/cm2 at 100kV) but extremely poor contrast
***Stronger (and toxic!) 25%TMAH solutions have much better contrast but poor sensitivity (1000's of uC/cm2 at 100kV)
***"Salty" developer solutions using 1wt% NaCl dissolved in either 4wt% NaOH or AZ300MIF solutions have the best contrast but reduce sensitivity significantly (10,000's of uC/cm2 at 100kV)

*'''DUV resists: UV6, UV210 UVN-30''': chemically amplified polymer-based resists
**High resolution and excellent sensitivity (clearing doses below 100uC/cm2 at 100kV)
**UV6 used mostly in optimized t-gate resist structures
**Developed using a dilute basic solution (e.g., metal-ion-free developers such as AZ-300MIF)
**Can be "double exposed" by [[Stepper 3 (ASML DUV)|ASML DUV Stepper]] and EBL.
***Recommended to produce ASML alignment marks first for double exposure methods.
**See ASML litho recipes for datasheets.

=== EBL Exposure Recipes ===
'''''To Be Added''''' - BEAMER simulation is always required for small (<<micron) features.

==[[Maskless Aligner (Raith PicoMasterXF)]]- WIP (needs to be linked to equipment page) ==

=== Positive Resist (Raith PicoMasterXF) ===

=== Note: Calibrations done with the "UCSB design" on 4 inch Si wafers, using resists listed below. ===
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
!Laser (nm)
! width="125" |Exposure Dose (mJ/cm2)
! width="100" |DeFocus
!Rehydrate*
! width="75" |PEB**
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[Media:AXP4000pb-Datasheet.pdf|AZ4110]]
|4 krpm, 30s
|95°C, 60s
|~ 1.1 µm
|405
|130
|0
|
|''none''
|AZ400K:DI 1:4
|50s
|Used UCSB design
(dense line/gap, 0.65um/0.65um)
|-

|[[Media:AXP4000pb-Datasheet.pdf|AZ4330]]
|4 krpm, 30s
|95°C, 60s
|~ 3.3 µm
|405
|200
| -1
|
|''none''
|AZ400K:DI 1:4
|90s
|Used UCSB design
(dense line/gap, 1um/1um)
|-
|[[Media:SPR955-Positive-Resist-Datasheet.pdf|SPR 955-CM0.9]]
|3 krpm, 30s
|95°C, 60s
|~ 0.9 µm
|405
|120
| 0
|
|110°C, 60s
|AZ300MIF
|60s
|Used UCSB design
(dense line/gap, 0.6um/0.6um)
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR 955-1.8]]
|4 krpm, 30s
|95°C, 60s
|~ 1.8 µm
|405
|200
|0
|
|110°C, 60s
|AZ300MIF
|60s
|Used UCSB design
(dense line/gap, 0.6um/0.6um)
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR 220-3.0]]
|2.5 krpm, 30s
|115°C, 90s
|~ 2.7 µm
|405
|180
| -1
|
|115°C, 90s
|AZ300MIF
|60s
|Used UCSB design
(dense line/gap, 0.65um/0.65um)
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR 220-7.0]]
|3.5 krpm, 30s
|105°C/2min
Cool 1min
|~ 7.0µm
|405
|340
| -3
|>1hr
|115°C, 90s
|AZ300MiF
|70s
|Used UCSB design
(dense line/gap, >>1um/1um)
|}

===Negative Resist (Raith PicoMasterXF)===

Note: Calibrations done with the "UCSB design" on 4 inch Si wafers, using resists listed below.

{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
!Laser (nm)
! width="125" |Exposure Dose (mJ/cm2)
! width="100" |DeFocus
! width="75" |PEB*
! width="75" |Flood**
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[Media:AZ5214-Negative-Resist-Datasheet.pdf|AZ5214]]**
|6 krpm, 30s
|95°C, 60s
|~ 1.0 µm
|405
|30
|0
|110°C, 60s
|60"
|AZ300MIF
|60s
|Used UCSB design (dense lines are patterned negative resist) (line/gap=1um/1um)
|-
|[[Media:AZnLOF2020-Negative-Resist-Datasheet.pdf|AZnLOF2020]]
|4 krpm, 30s
|110°C, 60s
|~ 2.1µm
|405
|450 (or higher)
| +2
|110°C, 60s
|''none''
|AZ300MIF
|30s
|Used UCSB design (dense lines are patterned negative resist) (line/gap=1um/1um)
|-
|}
<nowiki>*</nowiki>PEB: post-exposure bake. For AZ 5214-IR, this performs Image Reversal

<nowiki>**</nowiki> To use AZ5214 as a negative PR requires Flood Exposure with the [[Contact Aligner (SUSS MA-6)|MA6]] or [[Suss Aligners (SUSS MJB-3)|MJB]] aligner '''''after PEB''''', before developing. See here for a [[AZ5214 - Basic Process|basic AZ5214 process]], it is different than typical negative resists.

Direct-Write Lithography Recipes

2026-09-25T22:31:44Z

Noahdutra: changed SPR955 to PEB and soft bake to 60s

[[category: Lithography]]
[[category: Recipes]]
__TOC__

==[[Maskless Aligner (Heidelberg MLA150)]]==
For CAD design tips and requirements, see these pages:

*[[MLA150 - Design Guidelines|Design Guidelines + Tips]] - ''useful info for designing your CAD files, alignment marks etc.''
*[[MLA150 - CAD Files and Templates|CAD Files and Templates]] - example CAD files etc.

Photolithography Recipes for the [[Maskless Aligner (Heidelberg MLA150)|Heidelberg MLA150]]. All recipes were characterized on blank Silicon wafers. For different substrate coatings/materials, you will likely need to run a focus-exposure matrix ("series" exposure mode), using our params as a starting point.

These recipes use the same spin and bake params as our contact aligner and stepper recipes, using built-in hotplates on the photoresist spinner benches.

'''''Any I-Line PR is usable''''', although we only characterized a select few below. Run your own Focus-Exposure Matrix to characterize a new PR.

'''Note:''' On this tool, it is common to have to run a Focus-Exposure Matrix (aka. FEM), via "''Series''" exposure mode, for each new layer structure and/or critical feature size. The layer structure can strongly affect the exposure parameters. See the [[ASML Stepper 3 Standard Operating Procedure#Tips for FEM analysis|FEM Analysis Tips page]] for how to choose the proper exposure parameters.

The [[MLA150 - Troubleshooting#Out Of Focus Exposures|'''MLA''' '''Troubleshooting > Out-of-Focus Exposures''']] section can help you avoid bad exposures, please read it!

===Positive Resist (MLA150)===
''We found that positive PR's worked well with the 405nm laser - the 375nm laser would likely also work. Sub-micron features are possible. Overexposure is recommended to avoid stitching and horiz/vert discrepancies; compensate for widening/narrowing using CD Bias [[MLA150 - Design Guidelines#High-Resolution Writing|as described here]].''

Note: calibrations done with the "HIMT design" will show higher dose, due to using only dark-field line/space patterns.

{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
!Laser (nm)
! width="125" |Exposure Dose (mJ/cm2)
! width="100" |DeFocus
!Rehydrate*
! width="75" |PEB**
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[Media:AXP4000pb-Datasheet.pdf|AZ4110]]
|4 krpm, 30s
|95°C, 60s
|~ 1.1 µm
|405
|240
|5
|
|''none''
|AZ400K:DI 1:4
|50s
|Used HIMT design (good for isolated lines 0.8-1um)
|-

|[[Media:AXP4000pb-Datasheet.pdf|AZ4330]]
|4 krpm, 30s
|95°C, 60s
|~ 3.3 µm
|405
|320
|6
|
|''none''
|AZ400K:DI 1:4
|90s
|Used HIMT design
|-
|[[Media:AXP4000pb-Datasheet.pdf|AZ4620]]
|
|
|
|
|
|
|
|
|
|
|
|-
|[[Media:SPR955-Positive-Resist-Datasheet.pdf|SPR 955-CM0.9]]
|3 krpm, 30s
|95°C, 60s
|~ 0.9 µm
|405
|250
| - 7
|
|110°C, 60s
|AZ300MIF
|60s
|Used by UCSB Staff for tool calibrations/process control.
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR 955-1.8]]
|4 krpm, 30s
|95°C, 60s
|~ 1.8 µm
|405
|210
|10
|
|110°C, 60s
|AZ300MIF
|60s
|Used UCSB design (1um dense lines)
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR 220-3.0]]
|2.5 krpm, 30s
|115°C, 90s
|~ 2.7 µm
|405
|325
| - 4
|
|115°C, 90s
|AZ300MIF
|60s
|Used HIMT design. 0.6-0.9µm line/space.
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR 220-7.0]]
|3.5 krpm, 30s
|105°C/2min
Cool 1min
|~ 7.0µm
|375
|~550mJ
| -20
|>1hr
|115°C, 90s
|AZ300MiF
|70s
|Rehydration after exposure is necessary, to prevent bubbles at PEB.
|-
|[[Media:3600 D, D2v Spin Speed Curve.pdf|THMR-3600HP]]
|1.5 krpm, 45s;
250 rpm/s
|100°C, 60s
|0.430µm
|405
|180–220
|<nowiki>-4</nowiki>
|
|100°C, 60s
|AZ300MiF
|20s
|~0.4nm line/space:

lower dose for clear-field, higher dose for dark-field.
|-
| colspan="12" |*''Rehydration'': After exposure, leave sample in lab air (ok to cover in tray, with tinfoil). Allows water vapor in air to diffuse into PR to complete chemical reaction.
<nowiki>**</nowiki>''PEB: Post-exposure bake'': after exposure, before develop
|}

===Negative Resist (MLA150)===
''We found that all the negative PR's we tested required the 375nm in order to be fully exposed with reasonable dose/time.''

{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
!Laser (nm)
! width="125" |Exposure Dose (mJ/cm2)
! width="100" |DeFocus
! width="75" |PEB*
! width="75" |Flood**
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[Media:AZ5214-Negative-Resist-Datasheet.pdf|AZ5214]]**
|6 krpm, 30s
|95°C, 60s
|~ 1.0 µm
|375
|35
| - 5
|110°C, 60s
|60"
|AZ300MIF
|60s
|Used UCSB design. Good for up to ~1.3um open line space.
|-
|[[Media:AZnLOF2020-Negative-Resist-Datasheet.pdf|AZnLOF2020]]
|4 krpm, 30s
|110°C, 60s
|~ 2.1µm
|375
|340
| - 3
|110°C, 60s
|''none''
|AZ300MIF
|90s
|Used UCSB design. Good for 2um open line space.
|-
|[[Media:SU-8-2075-revA.pdf|SU-8 2075]]
|
|
|~70µm
|375
|
|
|
|
|
|
|Extremely viscous. Pour into a wide-mouthed bottle, dispense directly from bottle. Replace napkin at end.
|-
| colspan="12" |*PEB: post-exposure bake. For AZ 5214-IR, this performs Image Reversal
<nowiki>**</nowiki> To use AZ5214 as a negative PR requires Flood Exposure with the [[Contact Aligner (SUSS MA-6)|MA6]] or [[Suss Aligners (SUSS MJB-3)|MJB]] aligner '''''after PEB''''', before developing. See here for a [[AZ5214 - Basic Process|basic AZ5214 process]], it is different than typical negative resists.
|}

===Greyscale Lithography (MLA150)===
''AZ4620 is the manufacturer-recommended PR for greyscale litho.''

Please see the [[MLA150 - Design Guidelines#Limitations%20.26%20Workarounds|'''MLA150 - Greyscale Design Guidelines & Limitation''']]
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
!Laser
! width="125" |Exposure Dose (mJ/cm2)
! width="100" |Focus Offset
!Rehydrate*
! width="75" |PEB**
! width="100" |Developer
! width="125" |Developer Time
!Reflow***
! width="300" |Comments
|-
|[[Media:Az p4620 photoresist data package.pdf|AZ4620]]
|? krpm/30”
|95°C, 60”
|
|
|
|
|
|
|AZ300MIF
|60s
|
| align="left" |''To Be Added''
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR 220-7.0]]
|3.5 krpm, 30s
|105°C/2min
Cool 1min
|~ 7.0µm
|375
|~624mJ to clear large mm-area,
520mJ to clear ~5µm lines.
| -20
|≥1hr
|115°C, 90s
|AZ300MiF
|70s
|TBD
|Author Credit:
*Patrick Curtis, 2022
*Biljana Stamenic 2023
*Demis D. John 2023
|-
|
| colspan="12" |Notes on SPR 220-7 Greyscale: Rehydration after exposure is necessary, to prevent bubbles at PEB.
Stitching leaves ridges in Y-direction with ~5% height of removed PR depth. Can be reduced via reflow, but significantly affects PR profile.

Author Credit: Patrick Curtis, 2022 & Biljana Stamenic 2023 & Demis D. John 2023; Please see our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publications policy]].
|-
| colspan="13" |*''Rehydration'': After exposure, leave sample in lab air (ok to cover in tray, with tinfoil). Allows water vapor in air to diffuse into PR to complete chemical reaction.
<nowiki>**</nowiki>''PEB: Post-exposure bake'': after exposure, before develop

<nowiki>***</nowiki>''Reflow'': To smooth out stitching lines. Will change sharp vertical profiles considerably, only good for gradually-sloped profiles.
|}

== [[E-Beam Lithography System (Raith EBPG 5150+)|E-Beam Lithography Recipes (Raith EBPG 5150+)]] ==

=== Electron Beam Resists Available ===
EBL Resists are custom-mixed according to user resolution needs - contact [[Bill Mitchell]] to get a bottle.

Currently available at UCSB are:
*'''PMMA''': (950K in anisole, 950K in MIBK, 495K in anisole, 50K in anisole)
**High-resolution positive polymer-based resist with relatively poor sensitivity (resolution scales directly and sensitivity scales inversely with molecular weight);
**Poor plasma etch resistance, hence used primarily to fabricate metal lines via liftoff processes (via a bi-layer resist scheme...low MW on bottom, high MW on top for single lines, or vice-versa for T-gate fabrication);
**Utilizes an inert solvent developer (usually MIBK:IPA mixtures)

*'''P(MMA-MAA) copolymer''': (low MW methyl-methacrylate (MMA) and methacrylic acid (MAA) copolymers in ethyl lactate)
**A positive polymer-based resist with poor resolution but with significantly higher sensitivity than the higher MW PMMA resists above
**Used primarily as the top layer in a bi-layer resist scheme for T-Gate fabrication, and utilizes inert solvent developer (MIBK:IPA mixtures)

*'''CSAR-62''': ZEP-equivalent resist manufactured in Germany at much more competitive pricing!
**High-resolution polymer-based positive resist with very good sensitivity and excellent etch resistance
**Can be used in both metal lift-off processes (slight overexposure results in an excellent undercut profile) and various dry-etch processes for pattern transfer to the underlying substrate
**Utilizes inert solvent developers (e.g., n-amyl acetate for higher sensitivity and good resolution or MIBK:IPA mixtures for increased LER performance)

*'''maN-2403''': negative polymer-based resist (that is NOT chemically amplified)
**Very good resolution (down to the 40-50nm range) and sensitivity
**Exhibits excellent dry-etch resistance
**Developed using a dilute basic solution (e.g., metal-ion-free developers such as AZ-300MIF)

*'''HSQ''': negative resist that is based on spin-on glass material (ie, not polymer-based)
**Extremely good resolution (features below 10nm can be resolved)
**Etch resistance is high in Cl-based chemistries since HSQ reduces to a porous SiOx structure after exposure and development
**Sensitivity and contrast are very dependent on developer solution used and are usually poor
***Standard AZ300MIF developer solutions have decent sensitivity (100's of uC/cm2 at 100kV) but extremely poor contrast
***Stronger (and toxic!) 25%TMAH solutions have much better contrast but poor sensitivity (1000's of uC/cm2 at 100kV)
***"Salty" developer solutions using 1wt% NaCl dissolved in either 4wt% NaOH or AZ300MIF solutions have the best contrast but reduce sensitivity significantly (10,000's of uC/cm2 at 100kV)

*'''DUV resists: UV6, UV210 UVN-30''': chemically amplified polymer-based resists
**High resolution and excellent sensitivity (clearing doses below 100uC/cm2 at 100kV)
**UV6 used mostly in optimized t-gate resist structures
**Developed using a dilute basic solution (e.g., metal-ion-free developers such as AZ-300MIF)
**Can be "double exposed" by [[Stepper 3 (ASML DUV)|ASML DUV Stepper]] and EBL.
***Recommended to produce ASML alignment marks first for double exposure methods.
**See ASML litho recipes for datasheets.

=== EBL Exposure Recipes ===
'''''To Be Added''''' - BEAMER simulation is always required for small (<<micron) features.

==[[Maskless Aligner (Raith PicoMasterXF)]]- WIP (needs to be linked to equipment page) ==

=== Positive Resist (Raith PicoMasterXF) ===

=== Note: Calibrations done with the "UCSB design" on 4 inch Si wafers, using resists listed below. ===
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
!Laser (nm)
! width="125" |Exposure Dose (mJ/cm2)
! width="100" |DeFocus
!Rehydrate*
! width="75" |PEB**
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[Media:AXP4000pb-Datasheet.pdf|AZ4110]]
|4 krpm, 30s
|95°C, 60s
|~ 1.1 µm
|405
|130
|0
|
|''none''
|AZ400K:DI 1:4
|50s
|Used UCSB design
(dense line/gap, 0.65um/0.65um)
|-

|[[Media:AXP4000pb-Datasheet.pdf|AZ4330]]
|4 krpm, 30s
|95°C, 60s
|~ 3.3 µm
|405
|200
| -1
|
|''none''
|AZ400K:DI 1:4
|90s
|Used UCSB design
(dense line/gap, 1um/1um)
|-
|[[Media:SPR955-Positive-Resist-Datasheet.pdf|SPR 955-CM0.9]]
|3 krpm, 30s
|95°C, 90s
|~ 0.9 µm
|405
|120
| 0
|
|110°C, 90s
|AZ300MIF
|60s
|Used UCSB design
(dense line/gap, 0.6um/0.6um)
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR 955-1.8]]
|4 krpm, 30s
|95°C, 90s
|~ 1.8 µm
|405
|200
|0
|
|110°C, 90s
|AZ300MIF
|60s
|Used UCSB design
(dense line/gap, 0.6um/0.6um)
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR 220-3.0]]
|2.5 krpm, 30s
|115°C, 90s
|~ 2.7 µm
|405
|180
| -1
|
|115°C, 90s
|AZ300MIF
|60s
|Used UCSB design
(dense line/gap, 0.65um/0.65um)
|-
|[[Media:SPR220-Positive-Resist-Datasheet.pdf|SPR 220-7.0]]
|3.5 krpm, 30s
|105°C/2min
Cool 1min
|~ 7.0µm
|405
|340
| -3
|>1hr
|115°C, 90s
|AZ300MiF
|70s
|Used UCSB design
(dense line/gap, >>1um/1um)
|}

===Negative Resist (Raith PicoMasterXF)===

Note: Calibrations done with the "UCSB design" on 4 inch Si wafers, using resists listed below.

{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#D0E7FF"
! width="100" |Resist
! width="100" |Spin Cond.
! width="75" |Bake
! width="75" |Thickness
!Laser (nm)
! width="125" |Exposure Dose (mJ/cm2)
! width="100" |DeFocus
! width="75" |PEB*
! width="75" |Flood**
! width="100" |Developer
! width="125" |Developer Time
! width="300" |Comments
|-
|[[Media:AZ5214-Negative-Resist-Datasheet.pdf|AZ5214]]**
|6 krpm, 30s
|95°C, 60s
|~ 1.0 µm
|405
|30
|0
|110°C, 60s
|60"
|AZ300MIF
|60s
|Used UCSB design (dense lines are patterned negative resist) (line/gap=1um/1um)
|-
|[[Media:AZnLOF2020-Negative-Resist-Datasheet.pdf|AZnLOF2020]]
|4 krpm, 30s
|110°C, 60s
|~ 2.1µm
|405
|450 (or higher)
| +2
|110°C, 60s
|''none''
|AZ300MIF
|30s
|Used UCSB design (dense lines are patterned negative resist) (line/gap=1um/1um)
|-
|}
<nowiki>*</nowiki>PEB: post-exposure bake. For AZ 5214-IR, this performs Image Reversal

<nowiki>**</nowiki> To use AZ5214 as a negative PR requires Flood Exposure with the [[Contact Aligner (SUSS MA-6)|MA6]] or [[Suss Aligners (SUSS MJB-3)|MJB]] aligner '''''after PEB''''', before developing. See here for a [[AZ5214 - Basic Process|basic AZ5214 process]], it is different than typical negative resists.

Dry Etching Recipes

2026-09-23T22:16:38Z

Noahdutra: linked W etch FICP

===[[Process Group - Process Control Data#Etching .28Process Control Data.29|Process Control Data]]===
''See above [[Process Group - Process Control Data#Etching .28Process Control Data.29|linked page]] for [https://en.wikipedia.org/wiki/Statistical_process_control process control data] (dep rate/stress etc. over time), for a selection of often-used dry etches''

===Dry Etching Tools/Materials Table===

==== Process Maturity Ranking ====

* <code>'''R6'''</code> - most mature process with regular calibrations recorded on SPC charts.
* …
* <code>'''R1'''</code> - least mature - only run once ever.

''The Key/Legend for this table's <code>A...R6</code> values is at the [[Dry Etching Recipes#Process Ranking Table|bottom of the page]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center; font-size: 95%" border="1"
|-
! colspan="15" width="725" height="45" |<div style="font-size: 150%;">Dry Etching Recipes</div>
|- bgcolor="#d0e7ff"
| bgcolor="#eaecf0" |
! colspan="2" |'''[[RIE Etching Recipes|RIE Etching]]'''
! colspan="5" |'''[[ICP Etching Recipes|ICP Etching]]'''
! colspan="4" bgcolor="#d0e7ff" align="center" |'''[[Oxygen Plasma System Recipes|Oxygen Plasma Systems]]'''
! colspan="3" bgcolor="#d0e7ff" align="center" |'''[[Other Dry Etching Recipes|Other Dry Etchers]]'''
|- bgcolor="#d0e7ff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E646V)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ag
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Al Etch (Panasonic 1)|R1}}
|[[ICP Etching Recipes#Al Etch .28Panasonic 2.29|R2]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Au
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Cr
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Cr Etch (Panasonic 1)}}
|[[ICP Etching Recipes#Cr Etching (Panasonic 2)|R3]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Cu
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ge
|
|
|
|
|A
|R1
|
|
|
|
|
|[[Other Dry Etching Recipes|R2]]
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Mo
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!Nb
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ni
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|-
!Os
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Pt
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ru
|
|
|
|
|A
|[[ICP Etching Recipes#Ru .28Ruthenium.29 Etch .28Panasonic 2.29|R3]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Si
|
|
|[[ICP Etching Recipes#High Rate Bosch Etch (DSEIII)|R6]], [[ICP Etching Recipes#Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)|R3]]
|[[ICP Etching Recipes#Si Etch Recipes (Fluorine ICP Etcher)|R6]]
|
|
|R1
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ta
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ti
|
|
|
|
|{{rl|ICP Etching Recipes|Ti Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |W
|
|
|
|[[ICP Etching Recipes#W Etching (Fluorine ICP Etcher)|R3]]
|{{rl|ICP Etching Recipes|W-TiW Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|-
!TiW
|
|
|
|R3
|
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al2O3
|
|
|
|
|A
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Al2O3 (Sapphire)
|
|
|
|
|{{rl|ICP Etching Recipes|Sapphire Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlGaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |AlGaN
|
|
|
|
|
|
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R2]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlN
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!BCB
|
|
|
|
|A
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |CdZnTe
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|[[ICP Etching Recipes#GaAs Etch .28Panasonic 2.29|R6]]
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |GaN
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaN Etch (Panasonic 1)}}
|R1
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R6]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaSb
|
|
|
|
|A
|R1
|R1
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |HfO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!Hf
|
|
|
|
|
|
|R2
|
|
|
|
|
|
|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InGaAlAs
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|R1
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |InGaAsP
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InP
|[[RIE Etching Recipes|R3]]
|
|
|
|A
|R1
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R6]]
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ITO
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|R1
|
|
|
|
|
|
|R1
|-
!LiNbO3
|
|
|
|R1
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
!Photoresist & Organics
|
|[[RIE Etching Recipes#Photoresist and ARC (RIE 5)|R3]]
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|[https://wiki.nanotech.ucsb.edu/wiki/ICP_Etching_Recipes#Photoresist_and_ARC_Etching_.28Panasonic_1.29 R3]
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|R3
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|R1
|-
!ARC (Anti Reflective Coating)
|
|
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiC
|
|
|
|
|{{rl|ICP Etching Recipes|SiC Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiN
|
|
|
|[[ICP Etching Recipes#Si3N4 Etching .28Fluorine ICP Etcher.29|R3]]
|{{rl|ICP Etching Recipes|SiNx Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiNx Etching .28Panasonic 2.29|R3]]
|
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiO2
|
|
|[[ICP Etching Recipes#SiO2 Etch (DSEiii)|R3]]
|[[ICP Etching Recipes#SiO2 Etch Recipes (Fluorine ICP Etcher)|R6]]
|{{rl|ICP Etching Recipes|SiO2 Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiO2 Etching .28Panasonic 2.29|R6]]
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiOxNy
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|-
!SU8
|
|
|
|
|A
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ta2O5
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |TiN
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |TiO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZnS
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnSe
|[[RIE Etching Recipes|R2]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZrO2
|
|
|
|
|
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E640)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|}

===Process Ranking Table===
Processes in the table above are ranked by their "''Process Maturity Level''" as follows:
{| class="wikitable"
!Process Level
! colspan="11" |Description of Process Level Ranking
|-
|A
| colspan="11" |Process '''A'''llowed and materials available but never done
|-
|R1
| colspan="11" |Process has been ran at least once
|-
|R2
| colspan="11" |Process has been ran and procedure is documented
|-
|R3
| colspan="11" |Process has been ran, procedure is documented, and data is available
|-
|R4
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''no''' in-Situ control available
|-
|R5
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''and''' in-Situ control available
|-
|R6
| colspan="11" |Process has a documented procedure and control charts/limits available. Controlled process.
|}
[[Category:Processing]]

ICP Etching Recipes

2026-09-23T22:15:51Z

Noahdutra: Added W etch

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''[[ICP Etching Recipes#Process Control Data (DSEiii)|Process Control Data below]]''' - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==
*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with Al2O3 hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**Larger open area → lower selectivity & lower etch rate.
***<1% center to edge variability in etch rate for small open area.
***More variation across wafer for larger open area (eg. plasma dicing)
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}

=== '''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)''' ===
[[File:DSE plot.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281|232x232px]]
* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots''']

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
We have a new wafer-mounting process for through-silicon etching, using the UV-Release Dicing tape. Contact [[Demis D. John|staff]] for more info.
-- [[Demis D. John|Demis]] 2026-02-10

'''NOTE''':
'''DO NOT RUN''' the wax-mounting process without discussing with staff first. The wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer!
''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11

{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
with wax-mounting (small pieces only)
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - to eliminate grassing:

* Increase EtchA LF-Bias Power and Duration
** EtchA: 300W for 3.5–4sec
** New method as of ~2025
Old method: reduce Dep step:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

=== Plasma Dicing (DSEIII) ===
'''''Coming Soon''''': Plasma Dicing process with Dicing Tape as backing film.

This process has been developed by staff, is currently in the final stages of finalizing a public recipe. [[Demis D. John|'''''Contact staff''''']] if you want to use it sooner.

==Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)==

*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
**Smooth, Vertical, E.R. uniformity is within 5% on wafer
**Tested with 4" wafers that are ~50% open with UV6 PR
*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Older, alternate Si "shallow/smooth" etch recipe.
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

== SiO2 Etch (DSEiii) ==
These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].
*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
**Vertical/Smooth
**Tested by mounting 1cmx1cm piece with oil on 4" Si

==F-ICP Backup Recipes (DSEiii)==
These recipes were developed to serve as backup processes for the calibrated [[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|'''Fluorine-ICP''']] SiO2 and Si etches [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]].

[https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing FICP to DSE etch processes].

*'''[[ICP Etching Recipes#Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)|Si Etch v1 (⭐️Production)]]'''
*'''[[ICP Etching Recipes#SiO2 Etch (DSEiii)|SiO2 Etch v1 (⭐️Production)]]'''

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* '''[[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|Process Control Data for this tool]]''' - [[Process Group Internships|Intern-run Etches Weekly]], tracked over time.
** SiO2 and Silicon etche performance is regularly tracked.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data below]] - Staff/Intern-run Etches Weekly, tracked over time (with no BARC layer).
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

=== Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
[[File:FICP-Si.png|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots''']

==SiO2 Etch Recipes (Fluorine ICP Etcher)==
[[File:FL-ICP_50W_SiO2_etch_with_Ru_Hard_Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|thumb|266x266px|50W SiO2 Etch w/ Ru Hardmask]]
[[File:FL-ICP_200W_SiO2_Etch_with_Ru_Hardmask_-_Ning_Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|thumb|266x266px|200W SiO2 Etch w/ Ru Hardmask (Ning Cao)]]
*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.

=== [//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] ===

* Click above for [http://wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf Full Process Traveler]
** Process written for Sputtered Ru & I-Line GCA Stepper litho
** Can be transferred to ALD Ru or DUV/EBL Litho.

*''Ning Cao & Bill Mitchell, 2019-06''
*''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
*''Etch also works well with PR masking''
*''Chemistry: CHF3/CF4''
*''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
*Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
*50W Bias: ('''recommended''')
**Selectivity to photoresist: 1.10–1.20
**SiO2 selectivity to Ru: 36
**SiO2 etch rate: 263nm/min
**''Smoothest vertical etch for SiO2.''
*200W Bias: (higher etch rate)
**SiO2 selectivity to Ru: 38
**SiO2 etch rate: 471nm/min
*This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
*Updates: Many users have found that SiO2-masking the Ru hardmask results in vastly improved photoresist selectivity, making litho+etch of small features much better.
**Layer stack looks like: SiO2 (or other dielectric target layer to etch) / Ru hardmask / SiO2 hardmask (thin) / Photoresist.
**Typically strip the masks+PR with all dry etching. That means the entire etch process (all etches and strips) can be run ''in situ'' on the Panasonic ICP in a rapid single-tool etch process.
===Process Control: SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
[[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots''']

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===
[[File:SEM Image.png|thumb|New PR Strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Old PR strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**45sec-1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue
==W Etching (Fluorine ICP Etcher)==
[[File:W FICP Etch 2.jpg|thumb|223x223px|W Etch. Image Credit: Fatt Foong]]
<code>Developed by Fatt Foong. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/15W
*Pressure = 10mT
*C4F8/SF6/CF4 = 25/40/27sccm
**Etch Rate = 128nm/min

==Cleaning Procedures (Fluorine ICP Etcher)==

* [https://wiki.nanotech.ucsb.edu/w/images/6/69/Cleaning_Rules_for_Fluorine_ICP_Etch_tool.pdf '''Cleaning Rules'''] - for various etches. All cleans are O2 plasma.

=[[ICP Etch 1 (Panasonic E646V)]]=
'''Panasonic ICP#1 is currently down -''' Use Panasonic ICP#2 instead. Most processes directly transfer with only small change in etch rate. Data kept here for historical purposes only.

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure & Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get on the ''back'' of the carrier wafer or you will get Helium cooling errors.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch, and see their SEM's.

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

== Cr Etching (Panasonic 2) ==

* Cl2=48, O2=12sccm, 1.33Pa, ICP=600W, RF=50W
** Recipe #154 (please revert when done)
* Handles larger area etching with less loading effect
* Etch Rate: 24–33 nm/min
* Use PR mask. selectivity not measured but ~500nm PR works easily for etching ~85nm Cr.
* Strip PR in O2 plasma (in situ optional): [[ICP Etching Recipes#Photoresist Etch/Strip (Panasonic 2)|Photoresist Etch/Strip (Panasonic 2)]]
* [[Laser Etch Monitoring|Laser Monitor]] recommended

==GaAs Etch (Panasonic 2)==

*GaAs Etch Cal - ''Noah Dutra & Fatt Foong, 2025-02-12''
**Etch Rates ~1um/min, Selectivity to SiO2 ~ 27:1, Sidewalls ~ 90°
**Etch Rate/Selectivity [https://wiki.nanofab.ucsb.edu/w/images/7/76/GaAs_pressure_experiment.png highly sensitive to pressure] (image credit: Terry Guerrero)
**Cal Sample: ~1cm sample etched mounted with oil onto 150mm Si carrier
**Recipe: 0.5Pa, 100/900W, N2/Cl2=10/20sccm
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf Non-Calibration GaAs Etch Recipes - Panasonic 2 - Cl2N2]

===Process Control: GaAs Etch with N2/Cl2 (Panasonic 2)===
[[File:GaAs Etch ICP2 SPC.png|alt=example ICP2 process control chart|thumb|249x249px|[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for GaAs etching.|link=https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281]]
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=0#gid=0 GaAs Etch with N2/Cl2 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 GaAs Etch with N2/Cl2 - '''Plots''']

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])
*Recipe #152 (Please revert when done)

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
**''This etch is used in our Process Control weekly cals run by [[Process Group Interns|NanoFab Interns]]. Very stable over time ±5%.''
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

===Process Control: SiO2 Etch with CHF3/CF4 (Panasonic 2)===
[[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|thumb|269x269px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts] for SiO2 etching.|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]''Weekly cal etches of the CF4/CHF3 SiO2 etch, run by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots''']

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

=== Process Tips ===
* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* InP requires fairly high temperatures for making the Indium products volatile - so going to full-wafers (which are cooler) may requiring the table temperature. We have found that temperatures of ~150⁰C minimum may be required for preventing grassing etc.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==InP Ridge Etch (Oxford ICP Etcher)==
===High-Temp (200°C) InP Etch Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
[[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|thumb|218x218px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for 200°C InP Etch|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

===Low-Temp (60°C) InP Etch Process===
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: Low-Temp (60°C) InP Etch ====
[[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts] for 60°C InP Etch|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots''']

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''OLD 4" configuration: [https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**Also includes explanation of the Taguchi (L9) DOE method for learning how process variables interact.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: GaN Etch ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''

* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/11.6sccm.

* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]

[[File:GaN SPC.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279|219x219px]]OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]
==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning
*''[https://wiki.nanofab.ucsb.edu/w/images/d/d1/GaAs_Etch_Ver3_Recipe_Finalized_120925.pdf Std GaAs Etch - Cl2/N2 - 30C Etch Characterization] - F. Foong, 2025-12-10''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

File:W FICP Etch 2.jpg

2026-09-23T22:05:43Z

Noahdutra:

File:W FICP Etch 1.jpg

2026-09-23T22:05:00Z

Noahdutra:

ICP Etching Recipes

2026-09-23T21:59:20Z

Noahdutra: Added Tungsten Etch FICP recipe

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''[[ICP Etching Recipes#Process Control Data (DSEiii)|Process Control Data below]]''' - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==
*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with Al2O3 hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**Larger open area → lower selectivity & lower etch rate.
***<1% center to edge variability in etch rate for small open area.
***More variation across wafer for larger open area (eg. plasma dicing)
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}

=== '''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)''' ===
[[File:DSE plot.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281|232x232px]]
* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots''']

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
We have a new wafer-mounting process for through-silicon etching, using the UV-Release Dicing tape. Contact [[Demis D. John|staff]] for more info.
-- [[Demis D. John|Demis]] 2026-02-10

'''NOTE''':
'''DO NOT RUN''' the wax-mounting process without discussing with staff first. The wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer!
''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11

{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
with wax-mounting (small pieces only)
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - to eliminate grassing:

* Increase EtchA LF-Bias Power and Duration
** EtchA: 300W for 3.5–4sec
** New method as of ~2025
Old method: reduce Dep step:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

=== Plasma Dicing (DSEIII) ===
'''''Coming Soon''''': Plasma Dicing process with Dicing Tape as backing film.

This process has been developed by staff, is currently in the final stages of finalizing a public recipe. [[Demis D. John|'''''Contact staff''''']] if you want to use it sooner.

==Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)==

*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
**Smooth, Vertical, E.R. uniformity is within 5% on wafer
**Tested with 4" wafers that are ~50% open with UV6 PR
*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Older, alternate Si "shallow/smooth" etch recipe.
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

== SiO2 Etch (DSEiii) ==
These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].
*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
**Vertical/Smooth
**Tested by mounting 1cmx1cm piece with oil on 4" Si

==F-ICP Backup Recipes (DSEiii)==
These recipes were developed to serve as backup processes for the calibrated [[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|'''Fluorine-ICP''']] SiO2 and Si etches [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]].

[https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing FICP to DSE etch processes].

*'''[[ICP Etching Recipes#Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)|Si Etch v1 (⭐️Production)]]'''
*'''[[ICP Etching Recipes#SiO2 Etch (DSEiii)|SiO2 Etch v1 (⭐️Production)]]'''

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* '''[[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|Process Control Data for this tool]]''' - [[Process Group Internships|Intern-run Etches Weekly]], tracked over time.
** SiO2 and Silicon etche performance is regularly tracked.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data below]] - Staff/Intern-run Etches Weekly, tracked over time (with no BARC layer).
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

=== Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
[[File:FICP-Si.png|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots''']

==SiO2 Etch Recipes (Fluorine ICP Etcher)==
[[File:FL-ICP_50W_SiO2_etch_with_Ru_Hard_Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|thumb|266x266px|50W SiO2 Etch w/ Ru Hardmask]]
[[File:FL-ICP_200W_SiO2_Etch_with_Ru_Hardmask_-_Ning_Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|thumb|266x266px|200W SiO2 Etch w/ Ru Hardmask (Ning Cao)]]
*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.

=== [//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] ===

* Click above for [http://wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf Full Process Traveler]
** Process written for Sputtered Ru & I-Line GCA Stepper litho
** Can be transferred to ALD Ru or DUV/EBL Litho.

*''Ning Cao & Bill Mitchell, 2019-06''
*''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
*''Etch also works well with PR masking''
*''Chemistry: CHF3/CF4''
*''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
*Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
*50W Bias: ('''recommended''')
**Selectivity to photoresist: 1.10–1.20
**SiO2 selectivity to Ru: 36
**SiO2 etch rate: 263nm/min
**''Smoothest vertical etch for SiO2.''
*200W Bias: (higher etch rate)
**SiO2 selectivity to Ru: 38
**SiO2 etch rate: 471nm/min
*This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
*Updates: Many users have found that SiO2-masking the Ru hardmask results in vastly improved photoresist selectivity, making litho+etch of small features much better.
**Layer stack looks like: SiO2 (or other dielectric target layer to etch) / Ru hardmask / SiO2 hardmask (thin) / Photoresist.
**Typically strip the masks+PR with all dry etching. That means the entire etch process (all etches and strips) can be run ''in situ'' on the Panasonic ICP in a rapid single-tool etch process.
===Process Control: SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
[[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots''']

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===
[[File:SEM Image.png|thumb|New PR Strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Old PR strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**45sec-1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue
==W Etching (Fluorine ICP Etcher)==
<code>Developed by Fatt Foong. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/15W
*Pressure = 10mT
*C4F8/SF6/CF4 = 25/40/27sccm
**Etch Rate = 128nm/min
==Cleaning Procedures (Fluorine ICP Etcher)==

* [https://wiki.nanotech.ucsb.edu/w/images/6/69/Cleaning_Rules_for_Fluorine_ICP_Etch_tool.pdf '''Cleaning Rules'''] - for various etches. All cleans are O2 plasma.

=[[ICP Etch 1 (Panasonic E646V)]]=
'''Panasonic ICP#1 is currently down -''' Use Panasonic ICP#2 instead. Most processes directly transfer with only small change in etch rate. Data kept here for historical purposes only.

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure & Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get on the ''back'' of the carrier wafer or you will get Helium cooling errors.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch, and see their SEM's.

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

== Cr Etching (Panasonic 2) ==

* Cl2=48, O2=12sccm, 1.33Pa, ICP=600W, RF=50W
** Recipe #154 (please revert when done)
* Handles larger area etching with less loading effect
* Etch Rate: 24–33 nm/min
* Use PR mask. selectivity not measured but ~500nm PR works easily for etching ~85nm Cr.
* Strip PR in O2 plasma (in situ optional): [[ICP Etching Recipes#Photoresist Etch/Strip (Panasonic 2)|Photoresist Etch/Strip (Panasonic 2)]]
* [[Laser Etch Monitoring|Laser Monitor]] recommended

==GaAs Etch (Panasonic 2)==

*GaAs Etch Cal - ''Noah Dutra & Fatt Foong, 2025-02-12''
**Etch Rates ~1um/min, Selectivity to SiO2 ~ 27:1, Sidewalls ~ 90°
**Etch Rate/Selectivity [https://wiki.nanofab.ucsb.edu/w/images/7/76/GaAs_pressure_experiment.png highly sensitive to pressure] (image credit: Terry Guerrero)
**Cal Sample: ~1cm sample etched mounted with oil onto 150mm Si carrier
**Recipe: 0.5Pa, 100/900W, N2/Cl2=10/20sccm
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf Non-Calibration GaAs Etch Recipes - Panasonic 2 - Cl2N2]

===Process Control: GaAs Etch with N2/Cl2 (Panasonic 2)===
[[File:GaAs Etch ICP2 SPC.png|alt=example ICP2 process control chart|thumb|249x249px|[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for GaAs etching.|link=https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281]]
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=0#gid=0 GaAs Etch with N2/Cl2 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 GaAs Etch with N2/Cl2 - '''Plots''']

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])
*Recipe #152 (Please revert when done)

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
**''This etch is used in our Process Control weekly cals run by [[Process Group Interns|NanoFab Interns]]. Very stable over time ±5%.''
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

===Process Control: SiO2 Etch with CHF3/CF4 (Panasonic 2)===
[[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|thumb|269x269px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts] for SiO2 etching.|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]''Weekly cal etches of the CF4/CHF3 SiO2 etch, run by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots''']

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

=== Process Tips ===
* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* InP requires fairly high temperatures for making the Indium products volatile - so going to full-wafers (which are cooler) may requiring the table temperature. We have found that temperatures of ~150⁰C minimum may be required for preventing grassing etc.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==InP Ridge Etch (Oxford ICP Etcher)==
===High-Temp (200°C) InP Etch Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
[[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|thumb|218x218px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for 200°C InP Etch|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

===Low-Temp (60°C) InP Etch Process===
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: Low-Temp (60°C) InP Etch ====
[[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts] for 60°C InP Etch|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots''']

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''OLD 4" configuration: [https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**Also includes explanation of the Taguchi (L9) DOE method for learning how process variables interact.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: GaN Etch ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''

* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/11.6sccm.

* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]

[[File:GaN SPC.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279|219x219px]]OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]
==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning
*''[https://wiki.nanofab.ucsb.edu/w/images/d/d1/GaAs_Etch_Ver3_Recipe_Finalized_120925.pdf Std GaAs Etch - Cl2/N2 - 30C Etch Characterization] - F. Foong, 2025-12-10''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

Dry Etching Recipes

2026-09-23T20:48:36Z

Noahdutra: Added Cr as R3 to ICP2

===[[Process Group - Process Control Data#Etching .28Process Control Data.29|Process Control Data]]===
''See above [[Process Group - Process Control Data#Etching .28Process Control Data.29|linked page]] for [https://en.wikipedia.org/wiki/Statistical_process_control process control data] (dep rate/stress etc. over time), for a selection of often-used dry etches''

===Dry Etching Tools/Materials Table===

==== Process Maturity Ranking ====

* <code>'''R6'''</code> - most mature process with regular calibrations recorded on SPC charts.
* …
* <code>'''R1'''</code> - least mature - only run once ever.

''The Key/Legend for this table's <code>A...R6</code> values is at the [[Dry Etching Recipes#Process Ranking Table|bottom of the page]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center; font-size: 95%" border="1"
|-
! colspan="15" width="725" height="45" |<div style="font-size: 150%;">Dry Etching Recipes</div>
|- bgcolor="#d0e7ff"
| bgcolor="#eaecf0" |
! colspan="2" |'''[[RIE Etching Recipes|RIE Etching]]'''
! colspan="5" |'''[[ICP Etching Recipes|ICP Etching]]'''
! colspan="4" bgcolor="#d0e7ff" align="center" |'''[[Oxygen Plasma System Recipes|Oxygen Plasma Systems]]'''
! colspan="3" bgcolor="#d0e7ff" align="center" |'''[[Other Dry Etching Recipes|Other Dry Etchers]]'''
|- bgcolor="#d0e7ff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E646V)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ag
|
|
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|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Al Etch (Panasonic 1)|R1}}
|[[ICP Etching Recipes#Al Etch .28Panasonic 2.29|R2]]
|
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Au
|
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|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Cr
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Cr Etch (Panasonic 1)}}
|[[ICP Etching Recipes#Cr Etching (Panasonic 2)|R3]]
|
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Cu
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ge
|
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|A
|R1
|
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|
|[[Other Dry Etching Recipes|R2]]
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Mo
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|R1
|-
!Nb
|
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|A
|R1
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|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ni
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|
|[[Other Dry Etching Recipes|R3]]
|-
!Os
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|A
|R1
|
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|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Pt
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|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ru
|
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|A
|[[ICP Etching Recipes#Ru .28Ruthenium.29 Etch .28Panasonic 2.29|R3]]
|
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Si
|
|
|[[ICP Etching Recipes#High Rate Bosch Etch (DSEIII)|R6]], [[ICP Etching Recipes#Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)|R3]]
|[[ICP Etching Recipes#Si Etch Recipes (Fluorine ICP Etcher)|R6]]
|
|
|R1
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ta
|
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|A
|R1
|
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|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ti
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|{{rl|ICP Etching Recipes|Ti Etch (Panasonic 1)}}
|R1
|
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |W
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|R3
|{{rl|ICP Etching Recipes|W-TiW Etch (Panasonic 1)}}
|R1
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|R1
|-
!TiW
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|R3
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|R1
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|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al2O3
|
|
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|A
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Al2O3 (Sapphire)
|
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|{{rl|ICP Etching Recipes|Sapphire Etch (Panasonic 1)}}
|R1
|
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlGaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |AlGaN
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|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R2]]
|
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlN
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|R1
|-
!BCB
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|A
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|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |CdZnTe
|[[RIE Etching Recipes|R3]]
|
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|[[ICP Etching Recipes#GaAs Etch .28Panasonic 2.29|R6]]
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |GaN
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaN Etch (Panasonic 1)}}
|R1
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R6]]
|
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|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaSb
|
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|A
|R1
|R1
|
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |HfO2
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|R1
|-
!Hf
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|R2
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|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InGaAlAs
|[[RIE Etching Recipes|R3]]
|
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|R1
|
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |InGaAsP
|[[RIE Etching Recipes|R3]]
|
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|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R3]]
|
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InP
|[[RIE Etching Recipes|R3]]
|
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|A
|R1
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R6]]
|
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|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ITO
|[[RIE Etching Recipes|R3]]
|
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|R1
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|R1
|-
!LiNbO3
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|R1
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|R1
|- bgcolor="#ffffff"
!Photoresist & Organics
|
|[[RIE Etching Recipes#Photoresist and ARC (RIE 5)|R3]]
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|[https://wiki.nanotech.ucsb.edu/wiki/ICP_Etching_Recipes#Photoresist_and_ARC_Etching_.28Panasonic_1.29 R3]
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|R3
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
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|R1
|-
!ARC (Anti Reflective Coating)
|
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|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
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|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiC
|
|
|
|
|{{rl|ICP Etching Recipes|SiC Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiN
|
|
|
|[[ICP Etching Recipes#Si3N4 Etching .28Fluorine ICP Etcher.29|R3]]
|{{rl|ICP Etching Recipes|SiNx Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiNx Etching .28Panasonic 2.29|R3]]
|
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiO2
|
|
|[[ICP Etching Recipes#SiO2 Etch (DSEiii)|R3]]
|[[ICP Etching Recipes#SiO2 Etch Recipes (Fluorine ICP Etcher)|R6]]
|{{rl|ICP Etching Recipes|SiO2 Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiO2 Etching .28Panasonic 2.29|R6]]
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiOxNy
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|-
!SU8
|
|
|
|
|A
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ta2O5
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |TiN
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |TiO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZnS
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnSe
|[[RIE Etching Recipes|R2]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZrO2
|
|
|
|
|
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E640)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|}

===Process Ranking Table===
Processes in the table above are ranked by their "''Process Maturity Level''" as follows:
{| class="wikitable"
!Process Level
! colspan="11" |Description of Process Level Ranking
|-
|A
| colspan="11" |Process '''A'''llowed and materials available but never done
|-
|R1
| colspan="11" |Process has been ran at least once
|-
|R2
| colspan="11" |Process has been ran and procedure is documented
|-
|R3
| colspan="11" |Process has been ran, procedure is documented, and data is available
|-
|R4
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''no''' in-Situ control available
|-
|R5
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''and''' in-Situ control available
|-
|R6
| colspan="11" |Process has a documented procedure and control charts/limits available. Controlled process.
|}
[[Category:Processing]]

Process Group Interns

2026-09-21T21:51:41Z

Noahdutra: /* Current Interns */ Adding intern info for fall

The process group hosts a number of interns each year! Find out more on our [https://nanofab.ucsb.edu/workforce#internships internship page].

===Current Interns===
{| class="wikitable" border="1" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:left; font-size: 95%"
|- bgcolor="#D0E7FF"
! align="center" bgcolor="#D0E7FF" width="150" |'''Name'''
! align="center" bgcolor="#D0E7FF" width="250" |'''Major'''
! align="center" bgcolor="#D0E7FF" width="150" |'''Tasks'''
!Semesters
|-
|Brian Gonzalez
|Electrical Engineering
|PECVD Dep, Dry Etch/SEM
|Spring 2026-present
|-
|Tawshia Chowdhury
|Electrical Engineering
|PECVD Dep, Litho
|Fall 2026-present
|-
|Megan Fu
|Computer Engineering
|Dry Etch/SEM
|Fall 2026-present
|-
|Marcus Dong
|Electrical Engineering
|Litho, Dry Etch/SEM
|Fall 2026-present
|-
|Anurag Poddar
|Chemical Engineering
|Sputter/EBeam Dep
|Fall 2026-present
|-
|Eric Sun
|Electrical Engineering
|PECVD Dep, Dry Etch/SEM
|Fall 2026-present
|}

===Alumni===
{| class="wikitable" border="1" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:left; font-size: 95%"
|- bgcolor="#D0E7FF"
! align="center" bgcolor="#D0E7FF" width="150" |'''Name'''
! align="center" bgcolor="#D0E7FF" width="250" |'''Major'''
! align="center" bgcolor="#D0E7FF" width="150" |'''Tasks'''
!Semesters
|-
|Sean O'Donovan
|Electrical Engineering
|Litho, Dry Etch/SEM, Sputter/EBeam Dep
|Spring 2026-Summer 2026
|-
|Cooper Green
|Highschool (no major)
|PECVD Dep, Dry Etch/SEM, Litho
|Spring 2026-Summer 2026
|-
|Akhila Johny
|Electrical Engineering
|PECVD Dep, ALD Dep, Dry Etch/SEM, Litho Development
|Fall 2025–Summer 2026
|-
|Trace Chadwick
|Highschool (no major)
|PECVD Dep, Dry Etch/SEM, Litho
|Jan 2026–Spring 2026
|-
|Alex West
|Electrical Engineering
|Litho, Dry Etch/SEM, Sputter/EBeam Dep
|Jan 2026–Spring 2026
|-
|Ana Jevremoviç
|Santa Barbara City College: Materials Science and Engineering
|PECVD Dep, Dry Etch/SEM, Litho
|Fall 2025–Winter 2026
|-
|Leyna Chau
|Chemical Engineering
|Litho, Dry Etch/SEM, Sputter/EBeam Dep
|Fall 2025–Winter 2026
|-
|Diego Caceres Ceballos
|Physics
|Dry Etch, PECVD Dep, Sputter Development, Bosch etch development
|Summer 2025-Fall 2025
|-
|Ornob Barua
|Mechanical Engineering
|Dry Etch & Litho, LithoCal development
|Spring 2025–Fall 2025
|-
|Tanvi Kamath
|Chemical Engineering
|Glass Dep, Litho, Dry Etch
|Spring 2025–Fall 2025
|-
|William Cheng
|Electrical Engineering
|Dry Etch, Glass Dep & Litho
|Spring 2025–Fall 2025
|-
|Shiven Bhatt
|Electrical Engineering
|Dry Etch, PECVD Dep
|Spring 2025–Fall 2025
|-
|Terry Guerrero
|Physics
|Dry Etch, PECVD Dep, Dry Etch, Lithography, Metal Dep, ICP-PECVD, Ion-Beam Dep
|Fall 2024-Spring 2025
|-
|Javier Zamora Juarez
|Electrical Engineering
|PECVD Dep, Dry Etch, Lithography, E-Beam Dep (Developed), Litho Development
|Summer 2024-Spring 2025
|-
|Jiaheng "Robin" Teng
|Mechanical Engineering
|PECVD Deposition, Dry Etch, Lithography, Ion Beam Dep, ICP-PEVCD Dep, Litho Development
|Spring 2024–July 2025
|-
|Dhruv Patel
|Computer Science
|Dry Etch, PECVD Dep, Lithography
|Summer 2024–Winter 2025
|-
|Haley Hughes
|Electrical Engineering
|PECVD Dep, ICP-PECVD Dep., Dry Etch, Lithography
|Winter 2024–Winter 2025
|-
|William Matthews
|Dos Pueblos High School
|PECVD Dep, Dry Etch, Lithography
|Summer 2023–Summer 2024
|-
|Phineas Lehan
|Chemical Engineering
|Dry Etch, PECVD Deposition
|Winter 2023–Spring 2024
|-
|Allison Lebus
|Electrical Engineering
|PECVD Deposition, ICP-PECVD Dep, Ion Beam Dep., Traveler/spreadsheet Automation
|Winter 2023–Spring 2024
|-
|Judas Strayer
|Physics
|PECVD Dep., Dry Etch, Data Analysis
|Fall 2022–Summer 2023
|-
|Henry Allen
|Mechanical Engineering
|PECVD Deposition
|Summer 2022–Fall 2022
|-
|Noah Dutra
|Chemical Engineering
|Dry Etch, Lithography Development
|Spring 2022–Spring 2023
|-
|Nirav Pakala
|Electrical Engineering
|Dry Etch & Dry Etch Development/DOE
|Winter 2022–Summer 2022
|-
|Salim Tarazi
|Electrical Engineering
|PECVD Deposition
|Winter 2022–Summer 2022
|-
|Nastazia Moshirfatemi
|Physics
|PECVD Deposition, ICP-PECVD Dep, Ion Beam Dep, Data Analysis & Visualization
|Summer 2021–Winter 2022
|}

Process Group Interns

2026-09-21T21:45:37Z

Noahdutra: /* Alumni */ Updating intern table

The process group hosts a number of interns each year! Find out more on our [https://nanofab.ucsb.edu/workforce#internships internship page].

===Current Interns===
{| class="wikitable" border="1" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:left; font-size: 95%"
|- bgcolor="#D0E7FF"
! align="center" bgcolor="#D0E7FF" width="150" |'''Name'''
! align="center" bgcolor="#D0E7FF" width="250" |'''Major'''
! align="center" bgcolor="#D0E7FF" width="150" |'''Tasks'''
!Semesters
|-
|Brian Gonzalez
|Electrical Engineering
|PECVD Dep, Dry Etch/SEM
|Spring 2026-present
|}

===Alumni===
{| class="wikitable" border="1" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:left; font-size: 95%"
|- bgcolor="#D0E7FF"
! align="center" bgcolor="#D0E7FF" width="150" |'''Name'''
! align="center" bgcolor="#D0E7FF" width="250" |'''Major'''
! align="center" bgcolor="#D0E7FF" width="150" |'''Tasks'''
!Semesters
|-
|Sean O'Donovan
|Electrical Engineering
|Litho, Dry Etch/SEM, Sputter/EBeam Dep
|Spring 2026-Summer 2026
|-
|Cooper Green
|Highschool (no major)
|PECVD Dep, Dry Etch/SEM, Litho
|Spring 2026-Summer 2026
|-
|Akhila Johny
|Electrical Engineering
|PECVD Dep, ALD Dep, Dry Etch/SEM, Litho Development
|Fall 2025–Summer 2026
|-
|Trace Chadwick
|Highschool (no major)
|PECVD Dep, Dry Etch/SEM, Litho
|Jan 2026–Spring 2026
|-
|Alex West
|Electrical Engineering
|Litho, Dry Etch/SEM, Sputter/EBeam Dep
|Jan 2026–Spring 2026
|-
|Ana Jevremoviç
|Santa Barbara City College: Materials Science and Engineering
|PECVD Dep, Dry Etch/SEM, Litho
|Fall 2025–Winter 2026
|-
|Leyna Chau
|Chemical Engineering
|Litho, Dry Etch/SEM, Sputter/EBeam Dep
|Fall 2025–Winter 2026
|-
|Diego Caceres Ceballos
|Physics
|Dry Etch, PECVD Dep, Sputter Development, Bosch etch development
|Summer 2025-Fall 2025
|-
|Ornob Barua
|Mechanical Engineering
|Dry Etch & Litho, LithoCal development
|Spring 2025–Fall 2025
|-
|Tanvi Kamath
|Chemical Engineering
|Glass Dep, Litho, Dry Etch
|Spring 2025–Fall 2025
|-
|William Cheng
|Electrical Engineering
|Dry Etch, Glass Dep & Litho
|Spring 2025–Fall 2025
|-
|Shiven Bhatt
|Electrical Engineering
|Dry Etch, PECVD Dep
|Spring 2025–Fall 2025
|-
|Terry Guerrero
|Physics
|Dry Etch, PECVD Dep, Dry Etch, Lithography, Metal Dep, ICP-PECVD, Ion-Beam Dep
|Fall 2024-Spring 2025
|-
|Javier Zamora Juarez
|Electrical Engineering
|PECVD Dep, Dry Etch, Lithography, E-Beam Dep (Developed), Litho Development
|Summer 2024-Spring 2025
|-
|Jiaheng "Robin" Teng
|Mechanical Engineering
|PECVD Deposition, Dry Etch, Lithography, Ion Beam Dep, ICP-PEVCD Dep, Litho Development
|Spring 2024–July 2025
|-
|Dhruv Patel
|Computer Science
|Dry Etch, PECVD Dep, Lithography
|Summer 2024–Winter 2025
|-
|Haley Hughes
|Electrical Engineering
|PECVD Dep, ICP-PECVD Dep., Dry Etch, Lithography
|Winter 2024–Winter 2025
|-
|William Matthews
|Dos Pueblos High School
|PECVD Dep, Dry Etch, Lithography
|Summer 2023–Summer 2024
|-
|Phineas Lehan
|Chemical Engineering
|Dry Etch, PECVD Deposition
|Winter 2023–Spring 2024
|-
|Allison Lebus
|Electrical Engineering
|PECVD Deposition, ICP-PECVD Dep, Ion Beam Dep., Traveler/spreadsheet Automation
|Winter 2023–Spring 2024
|-
|Judas Strayer
|Physics
|PECVD Dep., Dry Etch, Data Analysis
|Fall 2022–Summer 2023
|-
|Henry Allen
|Mechanical Engineering
|PECVD Deposition
|Summer 2022–Fall 2022
|-
|Noah Dutra
|Chemical Engineering
|Dry Etch, Lithography Development
|Spring 2022–Spring 2023
|-
|Nirav Pakala
|Electrical Engineering
|Dry Etch & Dry Etch Development/DOE
|Winter 2022–Summer 2022
|-
|Salim Tarazi
|Electrical Engineering
|PECVD Deposition
|Winter 2022–Summer 2022
|-
|Nastazia Moshirfatemi
|Physics
|PECVD Deposition, ICP-PECVD Dep, Ion Beam Dep, Data Analysis & Visualization
|Summer 2021–Winter 2022
|}

Process Group Interns

2026-08-18T17:42:21Z

Noahdutra: /* Alumni */

The process group hosts a number of interns each year! Find out more on our [https://nanofab.ucsb.edu/workforce#internships internship page].

===Current Interns===
{| class="wikitable" border="1" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:left; font-size: 95%"
|- bgcolor="#D0E7FF"
! align="center" bgcolor="#D0E7FF" width="150" |'''Name'''
! align="center" bgcolor="#D0E7FF" width="250" |'''Major'''
! align="center" bgcolor="#D0E7FF" width="150" |'''Tasks'''
!Semesters
|-
|Brian Gonzalez
|Electrical Engineering
|PECVD Dep, Dry Etch/SEM
|Spring 2026-present
|-
|Sean O'Donovan
|Electrical Engineering
|Litho, Dry Etch/SEM, Sputter/EBeam Dep
|Spring 2026-present
|-
|Cooper Green
|Highschool (no major)
|PECVD Dep, Dry Etch/SEM, Litho
|Spring 2026-present
|-
|Akhila Johny
|Electrical Engineering
|PECVD Dep, Dry Etch/SEM, Litho
|Fall 2025–present
|}

===Alumni===
{| class="wikitable" border="1" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:left; font-size: 95%"
|- bgcolor="#D0E7FF"
! align="center" bgcolor="#D0E7FF" width="150" |'''Name'''
! align="center" bgcolor="#D0E7FF" width="250" |'''Major'''
! align="center" bgcolor="#D0E7FF" width="150" |'''Tasks'''
!Semesters
|-
|Trace Chadwick
|Highschool (no major)
|PECVD Dep, Dry Etch/SEM, Litho
|Jan 2026–Spring 2026
|-
|Alex West
|Electrical Engineering
|Litho, Dry Etch/SEM, Sputter/EBeam Dep
|Jan 2026–Spring 2026
|-
|Ana Jevremoviç
|Santa Barbara City College: Materials Science and Engineering
|PECVD Dep, Dry Etch/SEM, Litho
|Fall 2025–Winter 2026
|-
|Leyna Chau
|Chemical Engineering
|Litho, Dry Etch/SEM, Sputter/EBeam Dep
|Fall 2025–Winter 2026
|-
|Diego Caceres Ceballos
|Physics
|Dry Etch, PECVD Dep, Sputter Development, Bosch etch development
|Summer 2025-Fall 2025
|-
|Ornob Barua
|Mechanical Engineering
|Dry Etch & Litho, LithoCal development
|Spring 2025–Fall 2025
|-
|Tanvi Kamath
|Chemical Engineering
|Glass Dep, Litho, Dry Etch
|Spring 2025–Fall 2025
|-
|William Cheng
|Electrical Engineering
|Dry Etch, Glass Dep & Litho
|Spring 2025–Fall 2025
|-
|Shiven Bhatt
|Electrical Engineering
|Dry Etch, PECVD Dep
|Spring 2025–Fall 2025
|-
|Terry Guerrero
|Physics
|Dry Etch, PECVD Dep, Dry Etch, Lithography, Metal Dep, ICP-PECVD, Ion-Beam Dep
|Fall 2024-Spring 2025
|-
|Javier Zamora Juarez
|Electrical Engineering
|PECVD Dep, Dry Etch, Lithography, E-Beam Dep (Developed), Litho Development
|Summer 2024-Spring 2025
|-
|Jiaheng "Robin" Teng
|Mechanical Engineering
|PECVD Deposition, Dry Etch, Lithography, Ion Beam Dep, ICP-PEVCD Dep, Litho Development
|Spring 2024–July 2025
|-
|Dhruv Patel
|Computer Science
|Dry Etch, PECVD Dep, Lithography
|Summer 2024–Winter 2025
|-
|Haley Hughes
|Electrical Engineering
|PECVD Dep, ICP-PECVD Dep., Dry Etch, Lithography
|Winter 2024–Winter 2025
|-
|William Matthews
|Dos Pueblos High School
|PECVD Dep, Dry Etch, Lithography
|Summer 2023–Summer 2024
|-
|Phineas Lehan
|Chemical Engineering
|Dry Etch, PECVD Deposition
|Winter 2023–Spring 2024
|-
|Allison Lebus
|Electrical Engineering
|PECVD Deposition, ICP-PECVD Dep, Ion Beam Dep., Traveler/spreadsheet Automation
|Winter 2023–Spring 2024
|-
|Judas Strayer
|Physics
|PECVD Dep., Dry Etch, Data Analysis
|Fall 2022–Summer 2023
|-
|Henry Allen
|Mechanical Engineering
|PECVD Deposition
|Summer 2022–Fall 2022
|-
|Noah Dutra
|Chemical Engineering
|Dry Etch, Lithography Development
|Spring 2022–Spring 2023
|-
|Nirav Pakala
|Electrical Engineering
|Dry Etch & Dry Etch Development/DOE
|Winter 2022–Summer 2022
|-
|Salim Tarazi
|Electrical Engineering
|PECVD Deposition
|Winter 2022–Summer 2022
|-
|Nastazia Moshirfatemi
|Physics
|PECVD Deposition, ICP-PECVD Dep, Ion Beam Dep, Data Analysis & Visualization
|Summer 2021–Winter 2022
|}

Dry Etching Recipes

2026-08-05T18:30:07Z

Noahdutra: Added Hf as R2 to OXFD

===[[Process Group - Process Control Data#Etching .28Process Control Data.29|Process Control Data]]===
''See above [[Process Group - Process Control Data#Etching .28Process Control Data.29|linked page]] for [https://en.wikipedia.org/wiki/Statistical_process_control process control data] (dep rate/stress etc. over time), for a selection of often-used dry etches''

===Dry Etching Tools/Materials Table===

==== Process Maturity Ranking ====

* <code>'''R6'''</code> - most mature process with regular calibrations recorded on SPC charts.
* …
* <code>'''R1'''</code> - least mature - only run once ever.

''The Key/Legend for this table's <code>A...R6</code> values is at the [[Dry Etching Recipes#Process Ranking Table|bottom of the page]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center; font-size: 95%" border="1"
|-
! colspan="15" width="725" height="45" |<div style="font-size: 150%;">Dry Etching Recipes</div>
|- bgcolor="#d0e7ff"
| bgcolor="#eaecf0" |
! colspan="2" |'''[[RIE Etching Recipes|RIE Etching]]'''
! colspan="5" |'''[[ICP Etching Recipes|ICP Etching]]'''
! colspan="4" bgcolor="#d0e7ff" align="center" |'''[[Oxygen Plasma System Recipes|Oxygen Plasma Systems]]'''
! colspan="3" bgcolor="#d0e7ff" align="center" |'''[[Other Dry Etching Recipes|Other Dry Etchers]]'''
|- bgcolor="#d0e7ff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E646V)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ag
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Al Etch (Panasonic 1)|R1}}
|[[ICP Etching Recipes#Al Etch .28Panasonic 2.29|R2]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Au
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Cr
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Cr Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Cu
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ge
|
|
|
|
|A
|R1
|
|
|
|
|
|[[Other Dry Etching Recipes|R2]]
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Mo
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!Nb
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ni
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|-
!Os
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Pt
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ru
|
|
|
|
|A
|[[ICP Etching Recipes#Ru .28Ruthenium.29 Etch .28Panasonic 2.29|R3]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Si
|
|
|[[ICP Etching Recipes#High Rate Bosch Etch (DSEIII)|R6]], [[ICP Etching Recipes#Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)|R3]]
|[[ICP Etching Recipes#Si Etch Recipes (Fluorine ICP Etcher)|R6]]
|
|
|R1
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ta
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ti
|
|
|
|
|{{rl|ICP Etching Recipes|Ti Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |W
|
|
|
|R3
|{{rl|ICP Etching Recipes|W-TiW Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|-
!TiW
|
|
|
|R3
|
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al2O3
|
|
|
|
|A
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Al2O3 (Sapphire)
|
|
|
|
|{{rl|ICP Etching Recipes|Sapphire Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlGaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |AlGaN
|
|
|
|
|
|
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R2]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlN
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!BCB
|
|
|
|
|A
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |CdZnTe
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|[[ICP Etching Recipes#GaAs Etch .28Panasonic 2.29|R6]]
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |GaN
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaN Etch (Panasonic 1)}}
|R1
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R6]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaSb
|
|
|
|
|A
|R1
|R1
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |HfO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!Hf
|
|
|
|
|
|
|R2
|
|
|
|
|
|
|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InGaAlAs
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|R1
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |InGaAsP
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InP
|[[RIE Etching Recipes|R3]]
|
|
|
|A
|R1
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R6]]
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ITO
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|R1
|
|
|
|
|
|
|R1
|-
!LiNbO3
|
|
|
|R1
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
!Photoresist & Organics
|
|[[RIE Etching Recipes#Photoresist and ARC (RIE 5)|R3]]
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|[https://wiki.nanotech.ucsb.edu/wiki/ICP_Etching_Recipes#Photoresist_and_ARC_Etching_.28Panasonic_1.29 R3]
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|R3
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|R1
|-
!ARC (Anti Reflective Coating)
|
|
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiC
|
|
|
|
|{{rl|ICP Etching Recipes|SiC Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiN
|
|
|
|[[ICP Etching Recipes#Si3N4 Etching .28Fluorine ICP Etcher.29|R3]]
|{{rl|ICP Etching Recipes|SiNx Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiNx Etching .28Panasonic 2.29|R3]]
|
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiO2
|
|
|[[ICP Etching Recipes#SiO2 Etch (DSEiii)|R3]]
|[[ICP Etching Recipes#SiO2 Etch Recipes (Fluorine ICP Etcher)|R6]]
|{{rl|ICP Etching Recipes|SiO2 Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiO2 Etching .28Panasonic 2.29|R6]]
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiOxNy
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|-
!SU8
|
|
|
|
|A
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ta2O5
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |TiN
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |TiO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZnS
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnSe
|[[RIE Etching Recipes|R2]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZrO2
|
|
|
|
|
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E640)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|}

===Process Ranking Table===
Processes in the table above are ranked by their "''Process Maturity Level''" as follows:
{| class="wikitable"
!Process Level
! colspan="11" |Description of Process Level Ranking
|-
|A
| colspan="11" |Process '''A'''llowed and materials available but never done
|-
|R1
| colspan="11" |Process has been ran at least once
|-
|R2
| colspan="11" |Process has been ran and procedure is documented
|-
|R3
| colspan="11" |Process has been ran, procedure is documented, and data is available
|-
|R4
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''no''' in-Situ control available
|-
|R5
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''and''' in-Situ control available
|-
|R6
| colspan="11" |Process has a documented procedure and control charts/limits available. Controlled process.
|}
[[Category:Processing]]

Dry Etching Recipes

2026-08-05T18:22:11Z

Noahdutra: Added ITO OXFD and LiNbO3 FICP as R1s

===[[Process Group - Process Control Data#Etching .28Process Control Data.29|Process Control Data]]===
''See above [[Process Group - Process Control Data#Etching .28Process Control Data.29|linked page]] for [https://en.wikipedia.org/wiki/Statistical_process_control process control data] (dep rate/stress etc. over time), for a selection of often-used dry etches''

===Dry Etching Tools/Materials Table===

==== Process Maturity Ranking ====

* <code>'''R6'''</code> - most mature process with regular calibrations recorded on SPC charts.
* …
* <code>'''R1'''</code> - least mature - only run once ever.

''The Key/Legend for this table's <code>A...R6</code> values is at the [[Dry Etching Recipes#Process Ranking Table|bottom of the page]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center; font-size: 95%" border="1"
|-
! colspan="15" width="725" height="45" |<div style="font-size: 150%;">Dry Etching Recipes</div>
|- bgcolor="#d0e7ff"
| bgcolor="#eaecf0" |
! colspan="2" |'''[[RIE Etching Recipes|RIE Etching]]'''
! colspan="5" |'''[[ICP Etching Recipes|ICP Etching]]'''
! colspan="4" bgcolor="#d0e7ff" align="center" |'''[[Oxygen Plasma System Recipes|Oxygen Plasma Systems]]'''
! colspan="3" bgcolor="#d0e7ff" align="center" |'''[[Other Dry Etching Recipes|Other Dry Etchers]]'''
|- bgcolor="#d0e7ff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E646V)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ag
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Al Etch (Panasonic 1)|R1}}
|[[ICP Etching Recipes#Al Etch .28Panasonic 2.29|R2]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Au
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Cr
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Cr Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Cu
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ge
|
|
|
|
|A
|R1
|
|
|
|
|
|[[Other Dry Etching Recipes|R2]]
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Mo
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!Nb
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ni
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|-
!Os
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Pt
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ru
|
|
|
|
|A
|[[ICP Etching Recipes#Ru .28Ruthenium.29 Etch .28Panasonic 2.29|R3]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Si
|
|
|[[ICP Etching Recipes#High Rate Bosch Etch (DSEIII)|R6]], [[ICP Etching Recipes#Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)|R3]]
|[[ICP Etching Recipes#Si Etch Recipes (Fluorine ICP Etcher)|R6]]
|
|
|R1
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ta
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ti
|
|
|
|
|{{rl|ICP Etching Recipes|Ti Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |W
|
|
|
|R3
|{{rl|ICP Etching Recipes|W-TiW Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|-
!TiW
|
|
|
|R3
|
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al2O3
|
|
|
|
|A
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Al2O3 (Sapphire)
|
|
|
|
|{{rl|ICP Etching Recipes|Sapphire Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlGaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |AlGaN
|
|
|
|
|
|
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R2]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlN
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!BCB
|
|
|
|
|A
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |CdZnTe
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|[[ICP Etching Recipes#GaAs Etch .28Panasonic 2.29|R6]]
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |GaN
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaN Etch (Panasonic 1)}}
|R1
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R6]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaSb
|
|
|
|
|A
|R1
|R1
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |HfO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InGaAlAs
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|R1
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |InGaAsP
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InP
|[[RIE Etching Recipes|R3]]
|
|
|
|A
|R1
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R6]]
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ITO
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|R1
|
|
|
|
|
|
|R1
|-
!LiNbO3
|
|
|
|R1
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
!Photoresist & Organics
|
|[[RIE Etching Recipes#Photoresist and ARC (RIE 5)|R3]]
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|[https://wiki.nanotech.ucsb.edu/wiki/ICP_Etching_Recipes#Photoresist_and_ARC_Etching_.28Panasonic_1.29 R3]
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|R3
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|R1
|-
!ARC (Anti Reflective Coating)
|
|
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiC
|
|
|
|
|{{rl|ICP Etching Recipes|SiC Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiN
|
|
|
|[[ICP Etching Recipes#Si3N4 Etching .28Fluorine ICP Etcher.29|R3]]
|{{rl|ICP Etching Recipes|SiNx Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiNx Etching .28Panasonic 2.29|R3]]
|
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiO2
|
|
|[[ICP Etching Recipes#SiO2 Etch (DSEiii)|R3]]
|[[ICP Etching Recipes#SiO2 Etch Recipes (Fluorine ICP Etcher)|R6]]
|{{rl|ICP Etching Recipes|SiO2 Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiO2 Etching .28Panasonic 2.29|R6]]
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiOxNy
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|-
!SU8
|
|
|
|
|A
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ta2O5
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |TiN
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |TiO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZnS
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnSe
|[[RIE Etching Recipes|R2]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZrO2
|
|
|
|
|
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E640)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|}

===Process Ranking Table===
Processes in the table above are ranked by their "''Process Maturity Level''" as follows:
{| class="wikitable"
!Process Level
! colspan="11" |Description of Process Level Ranking
|-
|A
| colspan="11" |Process '''A'''llowed and materials available but never done
|-
|R1
| colspan="11" |Process has been ran at least once
|-
|R2
| colspan="11" |Process has been ran and procedure is documented
|-
|R3
| colspan="11" |Process has been ran, procedure is documented, and data is available
|-
|R4
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''no''' in-Situ control available
|-
|R5
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''and''' in-Situ control available
|-
|R6
| colspan="11" |Process has a documented procedure and control charts/limits available. Controlled process.
|}
[[Category:Processing]]

ICP Etching Recipes

2026-08-03T18:50:59Z

Noahdutra:

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''[[ICP Etching Recipes#Process Control Data (DSEiii)|Process Control Data below]]''' - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==High Rate Bosch Etch (DSEIII)==
*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with Al2O3 hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**Larger open area → lower selectivity & lower etch rate.
***<1% center to edge variability in etch rate for small open area.
***More variation across wafer for larger open area (eg. plasma dicing)
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}

=== '''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)''' ===
[[File:DSE plot.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281|232x232px]]
* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots''']

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
We have a new wafer-mounting process for through-silicon etching, using the UV-Release Dicing tape. Contact [[Demis D. John|staff]] for more info.
-- [[Demis D. John|Demis]] 2026-02-10

'''NOTE''':
'''DO NOT RUN''' the wax-mounting process without discussing with staff first. The wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer!
''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11

{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
with wax-mounting (small pieces only)
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - to eliminate grassing:

* Increase EtchA LF-Bias Power and Duration
** EtchA: 300W for 3.5–4sec
** New method as of ~2025
Old method: reduce Dep step:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

=== Plasma Dicing (DSEIII) ===
'''''Coming Soon''''': Plasma Dicing process with Dicing Tape as backing film.

This process has been developed by staff, is currently in the final stages of finalizing a public recipe. [[Demis D. John|'''''Contact staff''''']] if you want to use it sooner.

==Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)==

*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
**Smooth, Vertical, E.R. uniformity is within 5% on wafer
**Tested with 4" wafers that are ~50% open with UV6 PR
*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Older, alternate Si "shallow/smooth" etch recipe.
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

== SiO2 Etch (DSEiii) ==
These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].
*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
**Vertical/Smooth
**Tested by mounting 1cmx1cm piece with oil on 4" Si

==F-ICP Backup Recipes (DSEiii)==
These recipes were developed to serve as backup processes for the calibrated [[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|'''Fluorine-ICP''']] SiO2 and Si etches [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]].

[https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing FICP to DSE etch processes].

*'''[[ICP Etching Recipes#Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)|Si Etch v1 (⭐️Production)]]'''
*'''[[ICP Etching Recipes#SiO2 Etch (DSEiii)|SiO2 Etch v1 (⭐️Production)]]'''

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the [[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|'''Process Control Data below''']] - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

=== Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
[[File:FICP-Si.png|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots''']

==SiO2 Etch Recipes (Fluorine ICP Etcher)==
[[File:FL-ICP_50W_SiO2_etch_with_Ru_Hard_Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|thumb|266x266px|50W SiO2 Etch w/ Ru Hardmask]]
[[File:FL-ICP_200W_SiO2_Etch_with_Ru_Hardmask_-_Ning_Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|thumb|266x266px|200W SiO2 Etch w/ Ru Hardmask (Ning Cao)]]
*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.

=== [//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] ===

* Click above for [http://wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf Full Process Traveler]
** Process written for Sputtered Ru & I-Line GCA Stepper litho
** Can be transferred to ALD Ru or DUV/EBL Litho.

*''Ning Cao & Bill Mitchell, 2019-06''
*''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
*''Etch also works well with PR masking''
*''Chemistry: CHF3/CF4''
*''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
*Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
*50W Bias: ('''recommended''')
**Selectivity to photoresist: 1.10–1.20
**SiO2 selectivity to Ru: 36
**SiO2 etch rate: 263nm/min
**''Smoothest vertical etch for SiO2.''
*200W Bias: (higher etch rate)
**SiO2 selectivity to Ru: 38
**SiO2 etch rate: 471nm/min
*This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
*Updates: Many users have found that SiO2-masking the Ru hardmask results in vastly improved photoresist selectivity, making litho+etch of small features much better.
**Layer stack looks like: SiO2 (or other dielectric target layer to etch) / Ru hardmask / SiO2 hardmask (thin) / Photoresist.
**Typically strip the masks+PR with all dry etching. That means the entire etch process (all etches and strips) can be run ''in situ'' on the Panasonic ICP in a rapid single-tool etch process.
===Process Control: SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
[[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots''']

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===
[[File:SEM Image.png|thumb|New PR Strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Old PR strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**45sec-1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue

==Cleaning Procedures (Fluorine ICP Etcher)==

* [https://wiki.nanotech.ucsb.edu/w/images/6/69/Cleaning_Rules_for_Fluorine_ICP_Etch_tool.pdf '''Cleaning Rules'''] - for various etches. All cleans are O2 plasma.

=[[ICP Etch 1 (Panasonic E646V)]]=
'''Panasonic ICP#1 is currently down -''' Use Panasonic ICP#2 instead. Most processes directly transfer with only small change in etch rate. Data kept here for historical purposes only.

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure & Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get on the ''back'' of the carrier wafer or you will get Helium cooling errors.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch, and see their SEM's.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
**''This etch is used in our Process Control weekly cals run by [[Process Group Interns|NanoFab Interns]]. Very stable over time ±5%.''
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

===Process Control: SiO2 Etch with CHF3/CF4 (Panasonic 2)===
[[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|thumb|269x269px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts] for SiO2 etching.|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]''Weekly cal etches of the CF4/CHF3 SiO2 etch, run by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots''']

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*GaAs Etch Cal - ''Noah Dutra & Fatt Foong, 2025-02-12''
**Etch Rates ~1um/min, Selectivity to SiO2 ~ 27:1, Sidewalls ~ 90°
**Etch Rate/Selectivity [https://wiki.nanofab.ucsb.edu/w/images/7/76/GaAs_pressure_experiment.png highly sensitive to pressure] (image credit: Terry Guerrero)
**Cal Sample: ~1cm sample etched mounted with oil onto 150mm Si carrier
**Recipe: 0.5Pa, 100/900W, N2/Cl2=10/20sccm
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf Non-Calibration GaAs Etch Recipes - Panasonic 2 - Cl2N2]

===Process Control: GaAs Etch with N2/Cl2 (Panasonic 2)===
[[File:GaAs Etch ICP2 SPC.png|alt=example ICP2 process control chart|thumb|249x249px|[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for GaAs etching.|link=https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281]]
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=0#gid=0 GaAs Etch with N2/Cl2 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 GaAs Etch with N2/Cl2 - '''Plots''']

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

=== Process Tips ===
* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* InP requires fairly high temperatures for making the Indium products volatile - so going to full-wafers (which are cooler) may requiring the table temperature. We have found that temperatures of ~150⁰C minimum may be required for preventing grassing etc.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==InP Ridge Etch (Oxford ICP Etcher)==
===High-Temp (200°C) InP Etch Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
[[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|thumb|218x218px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for 200°C InP Etch|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

===Low-Temp (60°C) InP Etch Process===
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: Low-Temp (60°C) InP Etch ====
[[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts] for 60°C InP Etch|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots''']

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''OLD 4" configuration: [https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**Also includes explanation of the Taguchi (L9) DOE method for learning how process variables interact.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: GaN Etch ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''

* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/11.6sccm.

* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]

[[File:GaN SPC.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279|219x219px]]OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]
==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning
*''[https://wiki.nanofab.ucsb.edu/w/images/d/d1/GaAs_Etch_Ver3_Recipe_Finalized_120925.pdf Std GaAs Etch - Cl2/N2 - 30C Etch Characterization] - F. Foong, 2025-12-10''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

Oxford ICP Etcher (PlasmaPro 100 Cobra)

2026-08-03T18:49:38Z

Noahdutra: changed GaN etch recipe to have correct flow of BCl3

{{tool2|{{PAGENAME}}
|picture=OxfordPlasmaPro.jpg
|type = Dry Etch
|super= Tony Bosch
|super2= Bill Millerski
|location=Bay 2
|description = ICP Etches for III-V/ALE
|manufacturer = [https://www.oxinst.com Oxford Instruments]
|materials = InP, GaAs, GaN, Silicon ALE
|model = PlasmaPro 100 Cobra 300
|toolid=
}}
==About==

The Oxford PlasmaPro 100 Cobra 300 is intended for etching InP-based, GaAs-baased and GaN-based epitaxies, in addition to Atomic Layer Etching (ALE) processes.
The system has a load lock, wide temperature range with rapid heating/cooling, Inductively Coupled Plasma (ICP) coil and a capactively coupled substrate HF (13.56MHz)
The fixturing is configured for 4" diameter Si wafers and uses a clamp to hold the sample on the RF chuck. Small pieces may be placed on Silicon carrier wafers, with or without mounting adhesive. Helium back-side cooling is used to keep the sample cool during the etch, but pieces do heat up when placed on carriers.

The in-situ laser monitor installed on this system allows for repeatable etches and endpoint detection via continuous optical monitoring of the wafer reflectivity in a user-determined location, through a porthole on the chamber.
The system also has an ''in situ'' optical emission monitor for plasma spectroscopy, utilized for chamber clean endpoint detection.

==Detailed Specifications==

*Temperature Range: –150°C to +400°C
*Gases Available: CH4, H2, Ar, Cl2, BCl3, SF6, SiCl4, O2, N2
*ICP Power (max): 3000 W
*RF Power (max): 600 W
*He-back-side cooling
*100mm wafer held down with ceramic clamp., single-load
**Users may place pieces onto carrier wafer with or without adhesive. Standard recipes use no adhesive.
**Pieces must be >7mm from edge of carrier to avoid wafer-clamping mechanism.
*Windows-based Cortex software control of process and wafer handling
*Allowed Materials:
**InP-based epitaxies - ''qualified and ready''
**GaAs-baased epitaxies - ''starter recipe is available''
**GaN-based epitaxies - ''starter recipe is available''
**GaSb-based epitaxies - ''starter recipe is available''
**Atomic Layer Etching on select materials - ''starter recipe is available''
*Standard masking materials include:
**SiO2
**Si3N4
**photoresist (at << 100°C).

Other materials can be exposed to the chamber only with staff approval.

*Laser monitoring with camera and etch simulation software: [[Laser Etch Monitoring|Intellemetrics LEP 500]]
*Optical Emission Spectroscopy (Ocean Optics) for endpoint detection of chamber cleans & etches - integrated into Oxford software

==Documentation==

*{{file|Oxford_Cobra_300_SOP_v2021-12-14.pdf|Oxford PlasmaPro Operating Instructions|}}
**''Includes "Travelers" and post-cleaning for each type of standard etch (InP, GaAs, GaN)''
*[[Laser Etch Monitoring|Laser Etch Monitoring procedures]]

==== Online Training Video: ====
*[https://gauchocast.hosted.panopto.com/Panopto/Pages/Viewer.aspx?id=de1bb5fd-628f-4e70-b820-ae13010ee80b Oxford Cobra 300 Training]
*'''Important:''' ''This video is for reference only, and does not give you authorization to use the tool. You must be officially authorized by the supervisor before using this machine.''

==Recipes==

=== '''[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford PlasmaPro Recipes]]''' ← Recipes specific to this tool. ===
*All [[Dry Etching Recipes]] - use this list to see other options for dry etching various materials.

=== [[ICP Etching Recipes#Process Control Data .28Oxford ICP Etcher.29|Process Control Data]] ===
''Click above for calibration etch data for verifying tool performance over time.''

=== High-Temp (200°C) InP Etch Process ===

* InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
** Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
** Very dependent on open area, more area => lower E.R.s
** Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
** Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''

* [https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
* [https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

==== [https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Std InP Ridge Etch: Cl2/CH4/H2/60°C] ====
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

''No longer calibrating 60°C process as of 05-2025.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

==== GaN Etch (Cl2/BCl3/Ar/200°C) ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''
* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/11.6sccm.

* CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data
* CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots

OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiO2 mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]]<hr style="height:5px">

Nanofab Job Postings

2026-06-01T17:02:57Z

Noahdutra: Closed internship page and edited some details

You can see our Organization Chart here: https://www.nanotech.ucsb.edu/staff

==Current Openings==
''The following are positions we are currently hiring for:''

=== Intern - Processing Technician ===
*'''2027-2028 Academic Year Positions'''
**All positions are currently full through Summer 2027.
**We will start interviewing for 2027-2028 openings in '''April/May 2027'''.
*This position is open to Local High-School students, City College students, UCSB students or non-students.
*No Prerequisites nor experience required.
**We prefer some experience in ''any'' hands-on or technical field (construction, car repair, electronics/hobbies etc.).
**Optionally having taken one of [https://www.ece.ucsb.edu/department-resources/electronics-shop/tcr the UCSB cleanroom courses] (not required).
*6 month minimum hire, 10hr per week, paid. (Unpaid may also be available.)
**UCSB Work-study is accepted.
**A break during summer is acceptable, as long you can do 3 months before and 3 mo. after summer break.

*A position in the "[[Staff List#Process Group|Process Group]]", led by [[Demis D. John]].
**Running thin-film deposition calibrations on various high-use tools, your data will be listed on the public [[Process Group - Process Control Data|Process Control data]] pages.
**Will transition into Lithography & Plasma-Etch & Vacuum Deposition calibrations over time.
**Detailed info here: [[Process Group Internships]]
*To Apply: You can send an email to [[Noah Dutra|Noah]] and [[Demis D. John|Demis]]. We review apps every ~2-4 months, so you will receive a response ~4-6 weeks later once we start looking to fill the next cohort. Ok to follow-up and make sure we got it. Please send the following info:
**'''Your Résumé.''' List any hands-on and/or technical experience, paid or unpaid (including hobbies).
**'''What grade/year you are in''', if a student, and what school.
***Seniors, please make sure you can do a 6 month-long internship bearing graduation in mind!
**Can you work during the summer as well? Not required, but helpful.

==Filled/Closed Positions==

*'''''Internships are FULL through August 2027.'''''

==View all Nanofab Job Openings==
To search for available NanoFab job positions, follow these instructions:

#Follow the appropriate link:
##[https://careerspub.universityofcalifornia.edu/psp/ucsb/EMPLOYEE/HRMS/c/HRS_HRAM.HRS_APP_SCHJOB.GBL?Page=HRS_APP_SCHJOB&Action=U&FOCUS=Applicant&SiteId=31 Staff Jobs for "External Applicants"] - not a current UCSB employee
##[https://ucpath.universityofcalifornia.edu/peoplesoft-native/EMPLOYEE/HRMS/c/HRS_HRAM_EMP.HRS_APP_SCHJOB.GBL?Page=HRS_APP_SCHJOB&Action=U&SiteId=32&languageCd=ENG&FOCUS=Employee Staff Jobs for "Internal Applicants"] - for current UCSB employees
#In the "keywords" search field, search for "'''NanoFab'''".
#*All available NanoFab job postings should be listed.

(The same can be done by going to https://www.jobs.ucsb.edu/ > scroll to '''Browse Jobs''' > Choose Internal or External applicant.)

Noah Dutra

2026-05-21T03:37:38Z

Noahdutra:

{{staff|{{PAGENAME}}
|position = Process Engineer
|room = 1109F
|phone = (805) 893-5052
|cell =
|email = noahdutra@ucsb.edu
}}
==About==
Noah is a Process Engineer at the UCSB NanoFab. He earned his degree in Chemical Engineering from UCSB in 2023, where he distinguished himself with the top capstone design project of his cohort. During his undergraduate studies in 2022, Noah was among the first interns at the UCSB NanoFab, marking his initial exposure to semiconductor engineering. This experience inspired him to accept a position as a Semiconductor Process Engineer at Lockheed Martin/Santa Barbara Focalplane in Goleta, where he contributed to the production of infrared focal plane arrays for military and space applications. Driven by the dynamic environment and opportunities at the UCSB NanoFab, Noah rejoined the facility in 2024. In 2026, Noah will pursue a Masters of Science degree in Electronics and Photonics at UCSB.

==Current Work==
In his current role, Noah focuses on process development to support both the NanoFab as well as local companies. He is one of two process staff members directly involved with the CA DREAMS initiative, which includes leveraging analytics software to enhance SPC on laboratory tools. Noah also oversees and mentors undergraduate interns responsible for process calibrations while developing new ones himself to benefit lab users.

==Tools==
Noah is the supervisor for the following tools:

*TBD

==External Professional Websites==

*[https://www.linkedin.com/in/noah-dutra-703777215 LinkedIn]

Process Group Interns

2026-04-16T20:15:19Z

Noahdutra: /* Alumni */ added current interns and put Ana/leyna in alumni

The process group hosts a number of interns each year! Find out more on our [https://nanofab.ucsb.edu/workforce#internships internship page].

===Current Interns===
{| class="wikitable" border="1" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:left; font-size: 95%"
|- bgcolor="#D0E7FF"
! align="center" bgcolor="#D0E7FF" width="150" |'''Name'''
! align="center" bgcolor="#D0E7FF" width="250" |'''Major'''
! align="center" bgcolor="#D0E7FF" width="150" |'''Tasks'''
!Semesters
|-
|Brian Gonzalez
|Electrical Engineering
|PECVD Dep, Dry Etch/SEM
|Spring 2026-present
|-
|Sean O'Donovan
|Electrical Engineering
|Litho, Dry Etch/SEM, Sputter/EBeam Dep
|Spring 2026-present
|-
|Cooper Green
|Highschool (no major)
|PECVD Dep, Dry Etch/SEM, Litho
|Spring 2026-present
|-
|Akhila Johny
|Electrical Engineering
|PECVD Dep, Dry Etch/SEM, Litho
|Fall 2025–present
|-
|Trace Chadwick
|Highschool (no major)
|PECVD Dep, Dry Etch/SEM, Litho
|Jan 2026–present
|-
|Alex West
|Electrical Engineering
|Litho, Dry Etch/SEM, Sputter/EBeam Dep
|Jan 2026–present
|}

===Alumni===
{| class="wikitable" border="1" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:left; font-size: 95%"
|- bgcolor="#D0E7FF"
! align="center" bgcolor="#D0E7FF" width="150" |'''Name'''
! align="center" bgcolor="#D0E7FF" width="250" |'''Major'''
! align="center" bgcolor="#D0E7FF" width="150" |'''Tasks'''
!Semesters
|-
|Ana Jevremoviç
|Santa Barbara City College: Materials Science and Engineering
|PECVD Dep, Dry Etch/SEM, Litho
|Fall 2025–Winter 2026
|-
|Leyna Chau
|Chemical Engineering
|Litho, Dry Etch/SEM, Sputter/EBeam Dep
|Fall 2025–Winter 2026
|-
|Diego Caceres Ceballos
|Physics
|Dry Etch, PECVD Dep, Sputter Development, Bosch etch development
|Summer 2025-Fall 2025
|-
|Ornob Barua
|Mechanical Engineering
|Dry Etch & Litho, LithoCal development
|Spring 2025–Fall 2025
|-
|Tanvi Kamath
|Chemical Engineering
|Glass Dep, Litho, Dry Etch
|Spring 2025–Fall 2025
|-
|William Cheng
|Electrical Engineering
|Dry Etch, Glass Dep & Litho
|Spring 2025–Fall 2025
|-
|Shiven Bhatt
|Electrical Engineering
|Dry Etch, PECVD Dep
|Spring 2025–Fall 2025
|-
|Terry Guerrero
|Physics
|Dry Etch, PECVD Dep, Dry Etch, Lithography, Metal Dep, ICP-PECVD, Ion-Beam Dep
|Fall 2024-Spring 2025
|-
|Javier Zamora Juarez
|Electrical Engineering
|PECVD Dep, Dry Etch, Lithography, E-Beam Dep (Developed), Litho Development
|Summer 2024-Spring 2025
|-
|Jiaheng "Robin" Teng
|Mechanical Engineering
|PECVD Deposition, Dry Etch, Lithography, Ion Beam Dep, ICP-PEVCD Dep, Litho Development
|Spring 2024–July 2025
|-
|Dhruv Patel
|Computer Science
|Dry Etch, PECVD Dep, Lithography
|Summer 2024–Winter 2025
|-
|Haley Hughes
|Electrical Engineering
|PECVD Dep, ICP-PECVD Dep., Dry Etch, Lithography
|Winter 2024–Winter 2025
|-
|William Matthews
|Dos Pueblos High School
|PECVD Dep, Dry Etch, Lithography
|Summer 2023–Summer 2024
|-
|Phineas Lehan
|Chemical Engineering
|Dry Etch, PECVD Deposition
|Winter 2023–Spring 2024
|-
|Allison Lebus
|Electrical Engineering
|PECVD Deposition, ICP-PECVD Dep, Ion Beam Dep., Traveler/spreadsheet Automation
|Winter 2023–Spring 2024
|-
|Judas Strayer
|Physics
|PECVD Dep., Dry Etch, Data Analysis
|Fall 2022–Summer 2023
|-
|Henry Allen
|Mechanical Engineering
|PECVD Deposition
|Summer 2022–Fall 2022
|-
|Noah Dutra
|Chemical Engineering
|Dry Etch, Lithography Development
|Spring 2022–Spring 2023
|-
|Nirav Pakala
|Electrical Engineering
|Dry Etch & Dry Etch Development/DOE
|Winter 2022–Summer 2022
|-
|Salim Tarazi
|Electrical Engineering
|PECVD Deposition
|Winter 2022–Summer 2022
|-
|Nastazia Moshirfatemi
|Physics
|PECVD Deposition, ICP-PECVD Dep, Ion Beam Dep, Data Analysis & Visualization
|Summer 2021–Winter 2022
|}

Dry Etching Recipes

2026-04-14T17:10:57Z

Noahdutra:

===[[Process Group - Process Control Data#Etching .28Process Control Data.29|Process Control Data]]===
''See above [[Process Group - Process Control Data#Etching .28Process Control Data.29|linked page]] for [https://en.wikipedia.org/wiki/Statistical_process_control process control data] (dep rate/stress etc. over time), for a selection of often-used dry etches''

===Dry Etching Tools/Materials Table===

==== Process Maturity Ranking ====

* <code>'''R6'''</code> - most mature process with regular calibrations recorded on SPC charts.
* …
* <code>'''R1'''</code> - least mature - only run once ever.

''The Key/Legend for this table's <code>A...R6</code> values is at the [[Dry Etching Recipes#Process Ranking Table|bottom of the page]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center; font-size: 95%" border="1"
|-
! colspan="15" width="725" height="45" |<div style="font-size: 150%;">Dry Etching Recipes</div>
|- bgcolor="#d0e7ff"
| bgcolor="#eaecf0" |
! colspan="2" |'''[[RIE Etching Recipes|RIE Etching]]'''
! colspan="5" |'''[[ICP Etching Recipes|ICP Etching]]'''
! colspan="4" bgcolor="#d0e7ff" align="center" |'''[[Oxygen Plasma System Recipes|Oxygen Plasma Systems]]'''
! colspan="3" bgcolor="#d0e7ff" align="center" |'''[[Other Dry Etching Recipes|Other Dry Etchers]]'''
|- bgcolor="#d0e7ff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E646V)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ag
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Al Etch (Panasonic 1)|R1}}
|[[ICP Etching Recipes#Al Etch .28Panasonic 2.29|R2]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Au
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Cr
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Cr Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Cu
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ge
|
|
|
|
|A
|R1
|
|
|
|
|
|[[Other Dry Etching Recipes|R2]]
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Mo
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!Nb
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ni
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|-
!Os
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Pt
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ru
|
|
|
|
|A
|[[ICP Etching Recipes#Ru .28Ruthenium.29 Etch .28Panasonic 2.29|R3]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Si
|
|
|[[ICP Etching Recipes#High Rate Bosch Etch (DSEIII)|R6]], [[ICP Etching Recipes#Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)|R3]]
|[[ICP Etching Recipes#Si Etch Recipes (Fluorine ICP Etcher)|R6]]
|
|
|R1
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ta
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ti
|
|
|
|
|{{rl|ICP Etching Recipes|Ti Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |W
|
|
|
|R3
|{{rl|ICP Etching Recipes|W-TiW Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|-
!TiW
|
|
|
|R3
|
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al2O3
|
|
|
|
|A
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Al2O3 (Sapphire)
|
|
|
|
|{{rl|ICP Etching Recipes|Sapphire Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlGaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |AlGaN
|
|
|
|
|
|
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R2]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlN
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!BCB
|
|
|
|
|A
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |CdZnTe
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|[[ICP Etching Recipes#GaAs Etch .28Panasonic 2.29|R6]]
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |GaN
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaN Etch (Panasonic 1)}}
|R1
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R6]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaSb
|
|
|
|
|A
|R1
|R1
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |HfO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InGaAlAs
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|R1
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |InGaAsP
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InP
|[[RIE Etching Recipes|R3]]
|
|
|
|A
|R1
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R6]]
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ITO
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!LiNbO3
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
!Photoresist & Organics
|
|[[RIE Etching Recipes#Photoresist and ARC (RIE 5)|R3]]
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|[https://wiki.nanotech.ucsb.edu/wiki/ICP_Etching_Recipes#Photoresist_and_ARC_Etching_.28Panasonic_1.29 R3]
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|R3
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|R1
|-
!ARC (Anti Reflective Coating)
|
|
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiC
|
|
|
|
|{{rl|ICP Etching Recipes|SiC Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiN
|
|
|
|[[ICP Etching Recipes#Si3N4 Etching .28Fluorine ICP Etcher.29|R3]]
|{{rl|ICP Etching Recipes|SiNx Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiNx Etching .28Panasonic 2.29|R3]]
|
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiO2
|
|
|[[ICP Etching Recipes#SiO2 Etch (DSEiii)|R3]]
|[[ICP Etching Recipes#SiO2 Etch Recipes (Fluorine ICP Etcher)|R6]]
|{{rl|ICP Etching Recipes|SiO2 Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiO2 Etching .28Panasonic 2.29|R6]]
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiOxNy
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|-
!SU8
|
|
|
|
|A
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ta2O5
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |TiN
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |TiO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZnS
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnSe
|[[RIE Etching Recipes|R2]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZrO2
|
|
|
|
|
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E640)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|}

===Process Ranking Table===
Processes in the table above are ranked by their "''Process Maturity Level''" as follows:
{| class="wikitable"
!Process Level
! colspan="11" |Description of Process Level Ranking
|-
|A
| colspan="11" |Process '''A'''llowed and materials available but never done
|-
|R1
| colspan="11" |Process has been ran at least once
|-
|R2
| colspan="11" |Process has been ran and procedure is documented
|-
|R3
| colspan="11" |Process has been ran, procedure is documented, and data is available
|-
|R4
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''no''' in-Situ control available
|-
|R5
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''and''' in-Situ control available
|-
|R6
| colspan="11" |Process has a documented procedure and control charts/limits available. Controlled process.
|}
[[Category:Processing]]

Process Group Interns

2026-03-31T17:19:18Z

Noahdutra: /* Current Interns */ Rudro only did <1mo of work so taking him off

The process group hosts a number of interns each year! Find out more on our [https://nanofab.ucsb.edu/workforce#internships internship page].

===Current Interns===
{| class="wikitable" border="1" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:left; font-size: 95%"
|- bgcolor="#D0E7FF"
! align="center" bgcolor="#D0E7FF" width="150" |'''Name'''
! align="center" bgcolor="#D0E7FF" width="250" |'''Major'''
! align="center" bgcolor="#D0E7FF" width="150" |'''Tasks'''
!Semesters
|-
|Ana Jevremoviç
|Santa Barbara City College: Materials Science and Engineering
|PECVD Dep, Dry Etch/SEM, Litho
|Fall 2025–present
|-
|Akhila Johny
|Electrical Engineering
|PECVD Dep, Dry Etch/SEM, Litho
|Fall 2025–present
|-
|Leyna Chau
|Chemical Engineering
|Litho, Dry Etch/SEM, Sputter/EBeam Dep
|Fall 2025–present
|-
|Trace Chadwick
|Highschool (no major)
|PECVD Glass Deps, Litho
|Jan 2026–present
|-
|Alex West
|Electrical Engineering
|Dry Etch/SEM, Litho
|Jan 2026–present
|}

===Alumni===
{| class="wikitable" border="1" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:left; font-size: 95%"
|- bgcolor="#D0E7FF"
! align="center" bgcolor="#D0E7FF" width="150" |'''Name'''
! align="center" bgcolor="#D0E7FF" width="250" |'''Major'''
! align="center" bgcolor="#D0E7FF" width="150" |'''Tasks'''
!Semesters
|-
|Diego Caceres Ceballos
|Physics
|Dry Etch, PECVD Dep, Sputter Development, Bosch etch development
|Summer 2025-Fall 2025
|-
|Ornob Barua
|Mechanical Engineering
|Dry Etch & Litho, LithoCal development
|Spring 2025–Fall 2025
|-
|Tanvi Kamath
|Chemical Engineering
|Glass Dep, Litho, Dry Etch
|Spring 2025–Fall 2025
|-
|William Cheng
|Electrical & Computer Engineering
|Dry Etch, Glass Dep & Litho
|Spring 2025–Fall 2025
|-
|Shiven Bhatt
|Electrical Engineering
|Dry Etch, PECVD Dep
|Spring 2025–Fall 2025
|-
|Terry Guerrero
|Physics
|Dry Etch, PECVD Dep, Dry Etch, Lithography, Metal Dep, ICP-PECVD, Ion-Beam Dep
|Fall 2024-Spring 2025
|-
|Javier Zamora Juarez
|Electrical Engineering
|PECVD Dep, Dry Etch, Lithography, E-Beam Dep (Developed), Litho Development
|Summer 2024-Spring 2025
|-
|Jiaheng "Robin" Teng
|Mechanical Engineering
|PECVD Deposition, Dry Etch, Lithography, Ion Beam Dep, ICP-PEVCD Dep, Litho Development
|Spring 2024–July 2025
|-
|Dhruv Patel
|Computer Science
|Dry Etch, PECVD Dep, Lithography
|Summer 2024–Winter 2025
|-
|Haley Hughes
|Electrical Engineering
|PECVD Dep, ICP-PECVD Dep., Dry Etch, Lithography
|Winter 2024–Winter 2025
|-
|William Matthews
|Dos Pueblos High School
|PECVD Dep, Dry Etch, Lithography
|Summer 2023–Summer 2024
|-
|Phineas Lehan
|Chemical Engineering
|Dry Etch, PECVD Deposition
|Winter 2023–Spring 2024
|-
|Allison Lebus
|Electrical Engineering
|PECVD Deposition, ICP-PECVD Dep, Ion Beam Dep., Traveler/spreadsheet Automation
|Winter 2023–Spring 2024
|-
|Judas Strayer
|Physics
|PECVD Dep., Dry Etch, Data Analysis
|Fall 2022–Summer 2023
|-
|Henry Allen
|Mechanical Engineering
|PECVD Deposition
|Summer 2022–Fall 2022
|-
|Noah Dutra
|Chemical Engineering
|Dry Etch, Lithography Development
|Spring 2022–Spring 2023
|-
|Nirav Pakala
|Electrical Engineering
|Dry Etch & Dry Etch Development/DOE
|Winter 2022–Summer 2022
|-
|Salim Tarazi
|Electrical Engineering
|PECVD Deposition
|Winter 2022–Summer 2022
|-
|Nastazia Moshirfatemi
|Physics
|PECVD Deposition, ICP-PECVD Dep, Ion Beam Dep, Data Analysis & Visualization
|Summer 2021–Winter 2022
|}

Oxford ICP Etcher (PlasmaPro 100 Cobra)

2026-02-12T19:00:31Z

Noahdutra:

{{tool2|{{PAGENAME}}
|picture=OxfordPlasmaPro.jpg
|type = Dry Etch
|super= Tony Bosch
|super2= Bill Millerski
|location=Bay 2
|description = ICP Etches for III-V/ALE
|manufacturer = [https://www.oxinst.com Oxford Instruments]
|materials = InP, GaAs, GaN, Silicon ALE
|model = PlasmaPro 100 Cobra 300
|toolid=
}}
==About==

The Oxford PlasmaPro 100 Cobra 300 is intended for etching InP-based, GaAs-baased and GaN-based epitaxies, in addition to Atomic Layer Etching (ALE) processes.
The system has a load lock, wide temperature range with rapid heating/cooling, Inductively Coupled Plasma (ICP) coil and a capactively coupled substrate HF (13.56MHz)
The fixturing is configured for 4" diameter Si wafers and uses a clamp to hold the sample on the RF chuck. Small pieces may be placed on Silicon carrier wafers, with or without mounting adhesive. Helium back-side cooling is used to keep the sample cool during the etch, but pieces do heat up when placed on carriers.

The in-situ laser monitor installed on this system allows for repeatable etches and endpoint detection via continuous optical monitoring of the wafer reflectivity in a user-determined location, through a porthole on the chamber.
The system also has an ''in situ'' optical emission monitor for plasma spectroscopy, utilized for chamber clean endpoint detection.

==Detailed Specifications==

*Temperature Range: –150°C to +400°C
*Gases Available: CH4, H2, Ar, Cl2, BCl3, SF6, SiCl4, O2, N2
*ICP Power (max): 3000 W
*RF Power (max): 600 W
*He-back-side cooling
*100mm wafer held down with ceramic clamp., single-load
**Users may place pieces onto carrier wafer with or without adhesive. Standard recipes use no adhesive.
**Pieces must be >7mm from edge of carrier to avoid wafer-clamping mechanism.
*Windows-based Cortex software control of process and wafer handling
*Allowed Materials:
**InP-based epitaxies - ''qualified and ready''
**GaAs-baased epitaxies - ''starter recipe is available''
**GaN-based epitaxies - ''starter recipe is available''
**GaSb-based epitaxies - ''starter recipe is available''
**Atomic Layer Etching on select materials - ''starter recipe is available''
*Standard masking materials include:
**SiO2
**Si3N4
**photoresist (at << 100°C).

Other materials can be exposed to the chamber only with staff approval.

*Laser monitoring with camera and etch simulation software: [[Laser Etch Monitoring|Intellemetrics LEP 500]]
*Optical Emission Spectroscopy (Ocean Optics) for endpoint detection of chamber cleans & etches - integrated into Oxford software

==Documentation==

*{{file|Oxford_Cobra_300_SOP_v2021-12-14.pdf|Oxford PlasmaPro Operating Instructions|}}
**''Includes "Travelers" and post-cleaning for each type of standard etch (InP, GaAs, GaN)''
*[[Laser Etch Monitoring|Laser Etch Monitoring procedures]]
*Online Training Video:
**[https://gauchocast.hosted.panopto.com/Panopto/Pages/Viewer.aspx?id=de1bb5fd-628f-4e70-b820-ae13010ee80b Oxford Cobra 300 Training]
**'''Important:''' ''This video is for reference only, and does not give you authorization to use the tool. You must be officially authorized by the supervisor before using this machine.''

==Recipes==

=== '''[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford PlasmaPro Recipes]]''' ← Recipes specific to this tool. ===
*All [[Dry Etching Recipes]] - use this list to see other options for dry etching various materials.

=== [[ICP Etching Recipes#Process Control Data .28Oxford ICP Etcher.29|Process Control Data]] ===
''Click above for calibration etch data for verifying tool performance over time.''

=== High-Temp (200°C) InP Etch Process ===

* InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
** Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
** Very dependent on open area, more area => lower E.R.s
** Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
** Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''

* [https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
* [https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

==== [https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Std InP Ridge Etch: Cl2/CH4/H2/60°C] ====
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

''No longer calibrating 60°C process as of 05-2025.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

==== GaN Etch (Cl2/BCl3/Ar/200°C) ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''
* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.

* CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data
* CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots

OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiO2 mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]]<hr style="height:5px">

Oxford ICP Etcher (PlasmaPro 100 Cobra)

2026-02-12T18:56:15Z

Noahdutra: /* Oxford PlasmaPro Recipes ← Recipes specific to this tool. */

{{tool2|{{PAGENAME}}
|picture=OxfordPlasmaPro.jpg
|type = Dry Etch
|super= Tony Bosch
|super2= Bill Millerski
|location=Bay 2
|description = ICP Etches for III-V/ALE
|manufacturer = [https://www.oxinst.com Oxford Instruments]
|materials = InP, GaAs, GaN, Silicon ALE
|model = PlasmaPro 100 Cobra 300
|toolid=
}}
==About==

The Oxford PlasmaPro 100 Cobra 300 is intended for etching InP-based, GaAs-baased and GaN-based epitaxies, in addition to Atomic Layer Etching (ALE) processes.
The system has a load lock, wide temperature range with rapid heating/cooling, Inductively Coupled Plasma (ICP) coil and a capactively coupled substrate HF (13.56MHz)
The fixturing is configured for 4" diameter Si wafers and uses a clamp to hold the sample on the RF chuck. Small pieces may be placed on Silicon carrier wafers, with or without mounting adhesive. Helium back-side cooling is used to keep the sample cool during the etch, but pieces do heat up when placed on carriers.

The in-situ laser monitor installed on this system allows for repeatable etches and endpoint detection via continuous optical monitoring of the wafer reflectivity in a user-determined location, through a porthole on the chamber.
The system also has an ''in situ'' optical emission monitor for plasma spectroscopy, utilized for chamber clean endpoint detection.

==Detailed Specifications==

*Temperature Range: –150°C to +400°C
*Gases Available: CH4, H2, Ar, Cl2, BCl3, SF6, SiCl4, O2, N2
*ICP Power (max): 3000 W
*RF Power (max): 600 W
*He-back-side cooling
*100mm wafer held down with ceramic clamp., single-load
**Users may place pieces onto carrier wafer with or without adhesive. Standard recipes use no adhesive.
**Pieces must be >7mm from edge of carrier to avoid wafer-clamping mechanism.
*Windows-based Cortex software control of process and wafer handling
*Allowed Materials:
**InP-based epitaxies - ''qualified and ready''
**GaAs-baased epitaxies - ''starter recipe is available''
**GaN-based epitaxies - ''starter recipe is available''
**GaSb-based epitaxies - ''starter recipe is available''
**Atomic Layer Etching on select materials - ''starter recipe is available''
*Standard masking materials include:
**SiO2
**Si3N4
**photoresist (at << 100°C).

Other materials can be exposed to the chamber only with staff approval.

*Laser monitoring with camera and etch simulation software: [[Laser Etch Monitoring|Intellemetrics LEP 500]]
*Optical Emission Spectroscopy (Ocean Optics) for endpoint detection of chamber cleans & etches - integrated into Oxford software

==Documentation==

*{{file|Oxford_Cobra_300_SOP_v2021-12-14.pdf|Oxford PlasmaPro Operating Instructions|}}
**''Includes "Travelers" and post-cleaning for each type of standard etch (InP, GaAs, GaN)''
*[[Laser Etch Monitoring|Laser Etch Monitoring procedures]]
*Online Training Video:
**[https://gauchocast.hosted.panopto.com/Panopto/Pages/Viewer.aspx?id=de1bb5fd-628f-4e70-b820-ae13010ee80b Oxford Cobra 300 Training]
**'''Important:''' ''This video is for reference only, and does not give you authorization to use the tool. You must be officially authorized by the supervisor before using this machine.''

==Recipes==

=== '''[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford PlasmaPro Recipes]]''' ← Recipes specific to this tool. ===
*All [[Dry Etching Recipes]] - use this list to see other options for dry etching various materials.

=== [[ICP Etching Recipes#Process Control Data .28Oxford ICP Etcher.29|Process Control Data]] ===
''Click above for calibration etch data for verifying tool performance over time.''

=== High-Temp (200°C) InP Etch Process ===

* InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
** Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
** Very dependent on open area, more area => lower E.R.s
** Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
** Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''

* "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables'''
* "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots'''

==== [https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Std InP Ridge Etch: Cl2/CH4/H2/60°C] ====
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

''No longer calibrating 60°C process as of 05-2025.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

==== GaN Etch (Cl2/BCl3/Ar/200°C) ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''
* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.

* CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data
* CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots

OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiO2 mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]]<hr style="height:5px">

Oxford ICP Etcher (PlasmaPro 100 Cobra)

2026-02-12T18:55:05Z

Noahdutra: /* Recipes */

{{tool2|{{PAGENAME}}
|picture=OxfordPlasmaPro.jpg
|type = Dry Etch
|super= Tony Bosch
|super2= Bill Millerski
|location=Bay 2
|description = ICP Etches for III-V/ALE
|manufacturer = [https://www.oxinst.com Oxford Instruments]
|materials = InP, GaAs, GaN, Silicon ALE
|model = PlasmaPro 100 Cobra 300
|toolid=
}}
==About==

The Oxford PlasmaPro 100 Cobra 300 is intended for etching InP-based, GaAs-baased and GaN-based epitaxies, in addition to Atomic Layer Etching (ALE) processes.
The system has a load lock, wide temperature range with rapid heating/cooling, Inductively Coupled Plasma (ICP) coil and a capactively coupled substrate HF (13.56MHz)
The fixturing is configured for 4" diameter Si wafers and uses a clamp to hold the sample on the RF chuck. Small pieces may be placed on Silicon carrier wafers, with or without mounting adhesive. Helium back-side cooling is used to keep the sample cool during the etch, but pieces do heat up when placed on carriers.

The in-situ laser monitor installed on this system allows for repeatable etches and endpoint detection via continuous optical monitoring of the wafer reflectivity in a user-determined location, through a porthole on the chamber.
The system also has an ''in situ'' optical emission monitor for plasma spectroscopy, utilized for chamber clean endpoint detection.

==Detailed Specifications==

*Temperature Range: –150°C to +400°C
*Gases Available: CH4, H2, Ar, Cl2, BCl3, SF6, SiCl4, O2, N2
*ICP Power (max): 3000 W
*RF Power (max): 600 W
*He-back-side cooling
*100mm wafer held down with ceramic clamp., single-load
**Users may place pieces onto carrier wafer with or without adhesive. Standard recipes use no adhesive.
**Pieces must be >7mm from edge of carrier to avoid wafer-clamping mechanism.
*Windows-based Cortex software control of process and wafer handling
*Allowed Materials:
**InP-based epitaxies - ''qualified and ready''
**GaAs-baased epitaxies - ''starter recipe is available''
**GaN-based epitaxies - ''starter recipe is available''
**GaSb-based epitaxies - ''starter recipe is available''
**Atomic Layer Etching on select materials - ''starter recipe is available''
*Standard masking materials include:
**SiO2
**Si3N4
**photoresist (at << 100°C).

Other materials can be exposed to the chamber only with staff approval.

*Laser monitoring with camera and etch simulation software: [[Laser Etch Monitoring|Intellemetrics LEP 500]]
*Optical Emission Spectroscopy (Ocean Optics) for endpoint detection of chamber cleans & etches - integrated into Oxford software

==Documentation==

*{{file|Oxford_Cobra_300_SOP_v2021-12-14.pdf|Oxford PlasmaPro Operating Instructions|}}
**''Includes "Travelers" and post-cleaning for each type of standard etch (InP, GaAs, GaN)''
*[[Laser Etch Monitoring|Laser Etch Monitoring procedures]]
*Online Training Video:
**[https://gauchocast.hosted.panopto.com/Panopto/Pages/Viewer.aspx?id=de1bb5fd-628f-4e70-b820-ae13010ee80b Oxford Cobra 300 Training]
**'''Important:''' ''This video is for reference only, and does not give you authorization to use the tool. You must be officially authorized by the supervisor before using this machine.''

==Recipes==

=== '''[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford PlasmaPro Recipes]]''' ← Recipes specific to this tool. ===
*All [[Dry Etching Recipes]] - use this list to see other options for dry etching various materials.

=== [[ICP Etching Recipes#Process Control Data .28Oxford ICP Etcher.29|Process Control Data]] ===
''Click above for calibration etch data for verifying tool performance over time.''

=== High-Temp (200°C) InP Etch Process ===

* InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
** Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
** Very dependent on open area, more area => lower E.R.s
** Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
** Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
[[/wiki/File:200C_InP.png|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281|alt=example SPC chart for Oxford ICP Etcher|thumb|218x218px|Click for Process Control Charts for 200°C InP Etch]]
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''

* "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables'''
* "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots'''

==== [https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Std InP Ridge Etch: Cl2/CH4/H2/60°C] ====
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

''No longer calibrating 60°C process as of 05-2025.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots'''][[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|none|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]

==== GaN Etch (Cl2/BCl3/Ar/200°C) ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''
* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.

* CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data
* CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots

OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' Sapphire substrate with SiO2 mask for GaN.
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots][[File:GaN SPC.png|alt=example of Process Control Charts|none|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279]]<hr style="height:5px">

ICP Etching Recipes

2026-02-12T18:43:49Z

Noahdutra: /* GaN Etch (Oxford ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''[[ICP Etching Recipes#Process Control Data (DSEiii)|Process Control Data below]]''' - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==Analogous FICP Recipes (DSEiii)==
Make sure to remove photoresist from edges of wafer. These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].

*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01
**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
**Smooth, Vertical, E.R. uniformity is within 5% on wafer
**Tested with 4" wafers that are ~50% open with UV6 PR
*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01
**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
**Vertical/Smooth
**Tested by mounting 1cmx1cm piece with oil on 4" Si

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with Al2O3 hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}

=== '''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)''' ===
[[File:DSE plot.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281|232x232px]]
* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots''']

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
We have a new wafer-mounting process for through-silicon etching, using the UV-Release Dicing tape. Contact [[Demis D. John|staff]] for more info.
-- [[Demis D. John|Demis]] 2026-02-10

'''NOTE''':
'''DO NOT RUN''' the wax-mounting process without discussing with staff first. The wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer!
''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11

{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
with wax-mounting (small pieces only)
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the [[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|'''Process Control Data below''']] - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

=== Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
[[File:FICP-Si.png|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots''']

==SiO2 Etch Recipes (Fluorine ICP Etcher)==
[[File:FL-ICP_50W_SiO2_etch_with_Ru_Hard_Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|thumb|266x266px|50W SiO2 Etch w/ Ru Hardmask]]
[[File:FL-ICP_200W_SiO2_Etch_with_Ru_Hardmask_-_Ning_Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|thumb|266x266px|200W SiO2 Etch w/ Ru Hardmask (Ning Cao)]]
*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.

=== [//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] ===

* Click above for [http://wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf Full Process Traveler]
** Process written for Sputtered Ru & I-Line GCA Stepper litho
** Can be transferred to ALD Ru or DUV/EBL Litho.

*''Ning Cao & Bill Mitchell, 2019-06''
*''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
*''Etch also works well with PR masking''
*''Chemistry: CHF3/CF4''
*''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
*Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
*50W Bias: ('''recommended''')
**Selectivity to photoresist: 1.10–1.20
**SiO2 selectivity to Ru: 36
**SiO2 etch rate: 263nm/min
**''Smoothest vertical etch for SiO2.''
*200W Bias: (higher etch rate)
**SiO2 selectivity to Ru: 38
**SiO2 etch rate: 471nm/min
*This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
*Updates: Many users have found that SiO2-masking the Ru hardmask results in vastly improved photoresist selectivity, making litho+etch of small features much better.
**Layer stack looks like: SiO2 (or other dielectric target layer to etch) / Ru hardmask / SiO2 hardmask (thin) / Photoresist.
**Typically strip the masks+PR with all dry etching. That means the entire etch process (all etches and strips) can be run ''in situ'' on the Panasonic ICP in a rapid single-tool etch process.
===Process Control: SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
[[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots''']

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===
[[File:SEM Image.png|thumb|New PR Strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Old PR strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**45sec-1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=
'''Panasonic ICP#1 is currently down -''' Use Panasonic ICP#2 instead. Most processes directly transfer with only small change in etch rate. Data kept here for historical purposes only.

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure & Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get on the ''back'' of the carrier wafer or you will get Helium cooling errors.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch, and see their SEM's.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
**''This etch is used in our Process Control weekly cals run by [[Process Group Interns|NanoFab Interns]]. Very stable over time ±5%.''
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

===Process Control: SiO2 Etch with CHF3/CF4 (Panasonic 2)===
[[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|thumb|269x269px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts] for SiO2 etching.|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]''Weekly cal etches of the CF4/CHF3 SiO2 etch, run by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots''']

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*GaAs Etch Cal - ''Noah Dutra & Fatt Foong, 2025-02-12''
**Etch Rates ~1um/min, Selectivity to SiO2 ~ 27:1, Sidewalls ~ 90°
**Etch Rate/Selectivity [https://wiki.nanofab.ucsb.edu/w/images/7/76/GaAs_pressure_experiment.png highly sensitive to pressure] (image credit: Terry Guerrero)
**Cal Sample: ~1cm sample etched mounted with oil onto 150mm Si carrier
**Recipe: 0.5Pa, 100/900W, N2/Cl2=10/20sccm
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf Non-Calibration GaAs Etch Recipes - Panasonic 2 - Cl2N2]

===Process Control: GaAs Etch with N2/Cl2 (Panasonic 2)===
[[File:GaAs Etch ICP2 SPC.png|alt=example ICP2 process control chart|thumb|249x249px|[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for GaAs etching.|link=https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281]]
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=0#gid=0 GaAs Etch with N2/Cl2 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 GaAs Etch with N2/Cl2 - '''Plots''']

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

=== Process Tips ===
* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* InP requires fairly high temperatures for making the Indium products volatile - so going to full-wafers (which are cooler) may requiring the table temperature. We have found that temperatures of ~150⁰C minimum may be required for preventing grassing etc.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==InP Ridge Etch (Oxford ICP Etcher)==
===High-Temp (200°C) InP Etch Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
[[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|thumb|218x218px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for 200°C InP Etch|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

===Low-Temp (60°C) InP Etch Process===
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: Low-Temp (60°C) InP Etch ====
[[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts] for 60°C InP Etch|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots''']

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''OLD 4" configuration: [https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: GaN Etch ====
CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''

* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.

* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]

[[File:GaN SPC.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279|219x219px]]OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]
==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning
*''[https://wiki.nanofab.ucsb.edu/w/images/d/d1/GaAs_Etch_Ver3_Recipe_Finalized_120925.pdf Std GaAs Etch - Cl2/N2 - 30C Etch Characterization] - F. Foong, 2025-12-10''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

ICP Etching Recipes

2026-02-12T18:43:28Z

Noahdutra: /* GaN Etch (Oxford ICP Etcher) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''[[ICP Etching Recipes#Process Control Data (DSEiii)|Process Control Data below]]''' - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==Analogous FICP Recipes (DSEiii)==
Make sure to remove photoresist from edges of wafer. These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].

*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01
**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
**Smooth, Vertical, E.R. uniformity is within 5% on wafer
**Tested with 4" wafers that are ~50% open with UV6 PR
*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01
**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
**Vertical/Smooth
**Tested by mounting 1cmx1cm piece with oil on 4" Si

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with Al2O3 hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}

=== '''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)''' ===
[[File:DSE plot.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281|232x232px]]
* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots''']

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
We have a new wafer-mounting process for through-silicon etching, using the UV-Release Dicing tape. Contact [[Demis D. John|staff]] for more info.
-- [[Demis D. John|Demis]] 2026-02-10

'''NOTE''':
'''DO NOT RUN''' the wax-mounting process without discussing with staff first. The wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer!
''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11

{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
with wax-mounting (small pieces only)
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the [[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|'''Process Control Data below''']] - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

=== Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
[[File:FICP-Si.png|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots''']

==SiO2 Etch Recipes (Fluorine ICP Etcher)==
[[File:FL-ICP_50W_SiO2_etch_with_Ru_Hard_Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|thumb|266x266px|50W SiO2 Etch w/ Ru Hardmask]]
[[File:FL-ICP_200W_SiO2_Etch_with_Ru_Hardmask_-_Ning_Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|thumb|266x266px|200W SiO2 Etch w/ Ru Hardmask (Ning Cao)]]
*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.

=== [//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] ===

* Click above for [http://wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf Full Process Traveler]
** Process written for Sputtered Ru & I-Line GCA Stepper litho
** Can be transferred to ALD Ru or DUV/EBL Litho.

*''Ning Cao & Bill Mitchell, 2019-06''
*''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
*''Etch also works well with PR masking''
*''Chemistry: CHF3/CF4''
*''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
*Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
*50W Bias: ('''recommended''')
**Selectivity to photoresist: 1.10–1.20
**SiO2 selectivity to Ru: 36
**SiO2 etch rate: 263nm/min
**''Smoothest vertical etch for SiO2.''
*200W Bias: (higher etch rate)
**SiO2 selectivity to Ru: 38
**SiO2 etch rate: 471nm/min
*This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
*Updates: Many users have found that SiO2-masking the Ru hardmask results in vastly improved photoresist selectivity, making litho+etch of small features much better.
**Layer stack looks like: SiO2 (or other dielectric target layer to etch) / Ru hardmask / SiO2 hardmask (thin) / Photoresist.
**Typically strip the masks+PR with all dry etching. That means the entire etch process (all etches and strips) can be run ''in situ'' on the Panasonic ICP in a rapid single-tool etch process.
===Process Control: SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
[[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots''']

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===
[[File:SEM Image.png|thumb|New PR Strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Old PR strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**45sec-1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=
'''Panasonic ICP#1 is currently down -''' Use Panasonic ICP#2 instead. Most processes directly transfer with only small change in etch rate. Data kept here for historical purposes only.

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure & Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get on the ''back'' of the carrier wafer or you will get Helium cooling errors.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch, and see their SEM's.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
**''This etch is used in our Process Control weekly cals run by [[Process Group Interns|NanoFab Interns]]. Very stable over time ±5%.''
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

===Process Control: SiO2 Etch with CHF3/CF4 (Panasonic 2)===
[[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|thumb|269x269px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts] for SiO2 etching.|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]''Weekly cal etches of the CF4/CHF3 SiO2 etch, run by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots''']

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*GaAs Etch Cal - ''Noah Dutra & Fatt Foong, 2025-02-12''
**Etch Rates ~1um/min, Selectivity to SiO2 ~ 27:1, Sidewalls ~ 90°
**Etch Rate/Selectivity [https://wiki.nanofab.ucsb.edu/w/images/7/76/GaAs_pressure_experiment.png highly sensitive to pressure] (image credit: Terry Guerrero)
**Cal Sample: ~1cm sample etched mounted with oil onto 150mm Si carrier
**Recipe: 0.5Pa, 100/900W, N2/Cl2=10/20sccm
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf Non-Calibration GaAs Etch Recipes - Panasonic 2 - Cl2N2]

===Process Control: GaAs Etch with N2/Cl2 (Panasonic 2)===
[[File:GaAs Etch ICP2 SPC.png|alt=example ICP2 process control chart|thumb|249x249px|[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for GaAs etching.|link=https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281]]
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=0#gid=0 GaAs Etch with N2/Cl2 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 GaAs Etch with N2/Cl2 - '''Plots''']

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

=== Process Tips ===
* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* InP requires fairly high temperatures for making the Indium products volatile - so going to full-wafers (which are cooler) may requiring the table temperature. We have found that temperatures of ~150⁰C minimum may be required for preventing grassing etc.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==InP Ridge Etch (Oxford ICP Etcher)==
===High-Temp (200°C) InP Etch Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
[[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|thumb|218x218px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for 200°C InP Etch|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

===Low-Temp (60°C) InP Etch Process===
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: Low-Temp (60°C) InP Etch ====
[[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts] for 60°C InP Etch|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots''']

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
*''OLD 4" configuration: [https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: GaN Etch ====
NEW Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''

* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.

* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]

[[File:GaN SPC.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279|219x219px]]OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]
==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning
*''[https://wiki.nanofab.ucsb.edu/w/images/d/d1/GaAs_Etch_Ver3_Recipe_Finalized_120925.pdf Std GaAs Etch - Cl2/N2 - 30C Etch Characterization] - F. Foong, 2025-12-10''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

Dry Etching Recipes

2026-02-10T01:16:18Z

Noahdutra:

===[[Process Group - Process Control Data#Etching .28Process Control Data.29|Process Control Data]]===
''See above [[Process Group - Process Control Data#Etching .28Process Control Data.29|linked page]] for [https://en.wikipedia.org/wiki/Statistical_process_control process control data] (dep rate/stress etc. over time), for a selection of often-used dry etches''

===Dry Etching Tools/Materials Table===

==== Process Maturity Ranking ====

* <code>'''R6'''</code> - most mature process with regular calibrations recorded on SPC charts.
* …
* <code>'''R1'''</code> - least mature - only run once ever.

''The Key/Legend for this table's <code>A...R6</code> values is at the [[Dry Etching Recipes#Process Ranking Table|bottom of the page]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center; font-size: 95%" border="1"
|-
! colspan="15" width="725" height="45" |<div style="font-size: 150%;">Dry Etching Recipes</div>
|- bgcolor="#d0e7ff"
| bgcolor="#eaecf0" |
! colspan="2" |'''[[RIE Etching Recipes|RIE Etching]]'''
! colspan="5" |'''[[ICP Etching Recipes|ICP Etching]]'''
! colspan="4" bgcolor="#d0e7ff" align="center" |'''[[Oxygen Plasma System Recipes|Oxygen Plasma Systems]]'''
! colspan="3" bgcolor="#d0e7ff" align="center" |'''[[Other Dry Etching Recipes|Other Dry Etchers]]'''
|- bgcolor="#d0e7ff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E646V)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ag
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Al Etch (Panasonic 1)|R1}}
|[[ICP Etching Recipes#Al Etch .28Panasonic 2.29|R2]]
|
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|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Au
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|
|
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|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Cr
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Cr Etch (Panasonic 1)}}
|R1
|
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Cu
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ge
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|A
|R1
|
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|
|[[Other Dry Etching Recipes|R2]]
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Mo
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|R1
|-
!Nb
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|A
|R1
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|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ni
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|[[Other Dry Etching Recipes|R3]]
|-
!Os
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|A
|R1
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|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Pt
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|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ru
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|A
|[[ICP Etching Recipes#Ru .28Ruthenium.29 Etch .28Panasonic 2.29|R3]]
|
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Si
|
|
|[[ICP Etching Recipes#High Rate Bosch Etch (DSEIII)|R6]], [[ICP Etching Recipes#Analogous FICP Recipes (DSEiii)|R3]]
|[[ICP Etching Recipes#Si Etch Recipes (Fluorine ICP Etcher)|R6]]
|
|
|R1
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ta
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|A
|R1
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|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ti
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|{{rl|ICP Etching Recipes|Ti Etch (Panasonic 1)}}
|R1
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |W
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|R3
|{{rl|ICP Etching Recipes|W-TiW Etch (Panasonic 1)}}
|R1
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|R1
|-
!TiW
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|R3
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|R1
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|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al2O3
|
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|A
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Al2O3 (Sapphire)
|
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|{{rl|ICP Etching Recipes|Sapphire Etch (Panasonic 1)}}
|R1
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlGaAs
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|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |AlGaN
|
|
|
|
|
|
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R2]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlN
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!BCB
|
|
|
|
|A
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |CdZnTe
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|[[ICP Etching Recipes#GaAs Etch .28Panasonic 2.29|R6]]
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |GaN
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaN Etch (Panasonic 1)}}
|R1
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R6]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaSb
|
|
|
|
|A
|R1
|R1
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |HfO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InGaAlAs
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|R1
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |InGaAsP
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InP
|[[RIE Etching Recipes|R3]]
|
|
|
|A
|R1
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R6]]
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ITO
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!LiNbO3
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
!Photoresist & Organics
|
|[[RIE Etching Recipes#Photoresist and ARC (RIE 5)|R3]]
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|[https://wiki.nanotech.ucsb.edu/wiki/ICP_Etching_Recipes#Photoresist_and_ARC_Etching_.28Panasonic_1.29 R3]
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|R3
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|R1
|-
!ARC (Anti Reflective Coating)
|
|
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiC
|
|
|
|
|{{rl|ICP Etching Recipes|SiC Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiN
|
|
|
|[[ICP Etching Recipes#Si3N4 Etching .28Fluorine ICP Etcher.29|R3]]
|{{rl|ICP Etching Recipes|SiNx Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiNx Etching .28Panasonic 2.29|R3]]
|
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiO2
|
|
|[[ICP Etching Recipes#Analogous FICP Recipes (DSEiii)|R3]]
|[[ICP Etching Recipes#SiO2 Etch Recipes (Fluorine ICP Etcher)|R6]]
|{{rl|ICP Etching Recipes|SiO2 Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiO2 Etching .28Panasonic 2.29|R6]]
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiOxNy
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|-
!SU8
|
|
|
|
|A
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ta2O5
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |TiN
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |TiO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZnS
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnSe
|[[RIE Etching Recipes|R2]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZrO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E640)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|}

===Process Ranking Table===
Processes in the table above are ranked by their "''Process Maturity Level''" as follows:
{| class="wikitable"
!Process Level
! colspan="11" |Description of Process Level Ranking
|-
|A
| colspan="11" |Process '''A'''llowed and materials available but never done
|-
|R1
| colspan="11" |Process has been ran at least once
|-
|R2
| colspan="11" |Process has been ran and procedure is documented
|-
|R3
| colspan="11" |Process has been ran, procedure is documented, and data is available
|-
|R4
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''no''' in-Situ control available
|-
|R5
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''and''' in-Situ control available
|-
|R6
| colspan="11" |Process has a documented procedure and control charts/limits available. Controlled process.
|}
[[Category:Processing]]

Dry Etching Recipes

2026-02-10T01:15:39Z

Noahdutra: Adding analogous FICP-DSE recipes

===[[Process Group - Process Control Data#Etching .28Process Control Data.29|Process Control Data]]===
''See above [[Process Group - Process Control Data#Etching .28Process Control Data.29|linked page]] for [https://en.wikipedia.org/wiki/Statistical_process_control process control data] (dep rate/stress etc. over time), for a selection of often-used dry etches''

===Dry Etching Tools/Materials Table===

==== Process Maturity Ranking ====

* <code>'''R6'''</code> - most mature process with regular calibrations recorded on SPC charts.
* …
* <code>'''R1'''</code> - least mature - only run once ever.

''The Key/Legend for this table's <code>A...R6</code> values is at the [[Dry Etching Recipes#Process Ranking Table|bottom of the page]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center; font-size: 95%" border="1"
|-
! colspan="15" width="725" height="45" |<div style="font-size: 150%;">Dry Etching Recipes</div>
|- bgcolor="#d0e7ff"
| bgcolor="#eaecf0" |
! colspan="2" |'''[[RIE Etching Recipes|RIE Etching]]'''
! colspan="5" |'''[[ICP Etching Recipes|ICP Etching]]'''
! colspan="4" bgcolor="#d0e7ff" align="center" |'''[[Oxygen Plasma System Recipes|Oxygen Plasma Systems]]'''
! colspan="3" bgcolor="#d0e7ff" align="center" |'''[[Other Dry Etching Recipes|Other Dry Etchers]]'''
|- bgcolor="#d0e7ff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E646V)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ag
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Al Etch (Panasonic 1)|R1}}
|[[ICP Etching Recipes#Al Etch .28Panasonic 2.29|R2]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Au
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Cr
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Cr Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Cu
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ge
|
|
|
|
|A
|R1
|
|
|
|
|
|[[Other Dry Etching Recipes|R2]]
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Mo
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!Nb
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ni
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|-
!Os
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Pt
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ru
|
|
|
|
|A
|[[ICP Etching Recipes#Ru .28Ruthenium.29 Etch .28Panasonic 2.29|R3]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Si
|
|
|[[ICP Etching Recipes#DSEIII .28PlasmaTherm.2FDeep Silicon Etcher.29|R6]], [[ICP Etching Recipes#Analogous FICP Recipes (DSEiii)|R3]]
|[[ICP Etching Recipes#Si Etch Recipes (Fluorine ICP Etcher)|R6]]
|
|
|R1
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ta
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ti
|
|
|
|
|{{rl|ICP Etching Recipes|Ti Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |W
|
|
|
|R3
|{{rl|ICP Etching Recipes|W-TiW Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|-
!TiW
|
|
|
|R3
|
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al2O3
|
|
|
|
|A
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Al2O3 (Sapphire)
|
|
|
|
|{{rl|ICP Etching Recipes|Sapphire Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlGaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |AlGaN
|
|
|
|
|
|
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R2]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlN
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!BCB
|
|
|
|
|A
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |CdZnTe
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|[[ICP Etching Recipes#GaAs Etch .28Panasonic 2.29|R6]]
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |GaN
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaN Etch (Panasonic 1)}}
|R1
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R6]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaSb
|
|
|
|
|A
|R1
|R1
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |HfO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InGaAlAs
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|R1
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |InGaAsP
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InP
|[[RIE Etching Recipes|R3]]
|
|
|
|A
|R1
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R6]]
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ITO
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!LiNbO3
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
!Photoresist & Organics
|
|[[RIE Etching Recipes#Photoresist and ARC (RIE 5)|R3]]
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|[https://wiki.nanotech.ucsb.edu/wiki/ICP_Etching_Recipes#Photoresist_and_ARC_Etching_.28Panasonic_1.29 R3]
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|R3
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|R1
|-
!ARC (Anti Reflective Coating)
|
|
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiC
|
|
|
|
|{{rl|ICP Etching Recipes|SiC Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiN
|
|
|
|[[ICP Etching Recipes#Si3N4 Etching .28Fluorine ICP Etcher.29|R3]]
|{{rl|ICP Etching Recipes|SiNx Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiNx Etching .28Panasonic 2.29|R3]]
|
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiO2
|
|
|[[ICP Etching Recipes#Analogous FICP Recipes (DSEiii)|R3]]
|[[ICP Etching Recipes#SiO2 Etch Recipes (Fluorine ICP Etcher)|R6]]
|{{rl|ICP Etching Recipes|SiO2 Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiO2 Etching .28Panasonic 2.29|R6]]
|
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|
|[[Other Dry Etching Recipes|R3]]
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiOxNy
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|A
|R1
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|R1
|-
!SU8
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|A
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|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ta2O5
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|A
|R1
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |TiN
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |TiO2
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnO2
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|
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZnS
|[[RIE Etching Recipes|R3]]
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnSe
|[[RIE Etching Recipes|R2]]
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|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZrO2
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|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E640)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|}

===Process Ranking Table===
Processes in the table above are ranked by their "''Process Maturity Level''" as follows:
{| class="wikitable"
!Process Level
! colspan="11" |Description of Process Level Ranking
|-
|A
| colspan="11" |Process '''A'''llowed and materials available but never done
|-
|R1
| colspan="11" |Process has been ran at least once
|-
|R2
| colspan="11" |Process has been ran and procedure is documented
|-
|R3
| colspan="11" |Process has been ran, procedure is documented, and data is available
|-
|R4
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''no''' in-Situ control available
|-
|R5
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''and''' in-Situ control available
|-
|R6
| colspan="11" |Process has a documented procedure and control charts/limits available. Controlled process.
|}
[[Category:Processing]]

ICP Etching Recipes

2026-02-10T01:13:31Z

Noahdutra: /* Analogous FICP Recipes (DSEiii) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''[[ICP Etching Recipes#Process Control Data (DSEiii)|Process Control Data below]]''' - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==Analogous FICP Recipes (DSEiii)==
Make sure to remove photoresist from edges of wafer. These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].

*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01
**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
**Smooth, Vertical, E.R. uniformity is within 5% on wafer
**Tested with 4" wafers that are ~50% open with UV6 PR
*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01
**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
**Vertical/Smooth
**Tested by mounting 1cmx1cm piece with oil on 4" Si

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with Al2O3 hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}

=== '''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)''' ===
[[File:DSE plot.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281|232x232px]]
* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots''']

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>

Staff is working on a dicing-tape mounted recipe, to be published here soon.
-- [[Demis D. John|Demis]] 2025-11-19
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the [[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|'''Process Control Data below''']] - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

=== Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
[[File:FICP-Si.png|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots''']

==SiO2 Etch Recipes (Fluorine ICP Etcher)==
[[File:FL-ICP_50W_SiO2_etch_with_Ru_Hard_Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|thumb|266x266px|50W SiO2 Etch w/ Ru Hardmask]]
[[File:FL-ICP_200W_SiO2_Etch_with_Ru_Hardmask_-_Ning_Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|thumb|266x266px|200W SiO2 Etch w/ Ru Hardmask (Ning Cao)]]
*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.

=== [//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] ===

* Click above for [http://wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf Full Process Traveler]
** Process written for Sputtered Ru & I-Line GCA Stepper litho
** Can be transferred to ALD Ru or DUV/EBL Litho.

*''Ning Cao & Bill Mitchell, 2019-06''
*''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
*''Etch also works well with PR masking''
*''Chemistry: CHF3/CF4''
*''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
*Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
*50W Bias: ('''recommended''')
**Selectivity to photoresist: 1.10–1.20
**SiO2 selectivity to Ru: 36
**SiO2 etch rate: 263nm/min
**''Smoothest vertical etch for SiO2.''
*200W Bias: (higher etch rate)
**SiO2 selectivity to Ru: 38
**SiO2 etch rate: 471nm/min
*This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
*Updates: Many users have found that SiO2-masking the Ru hardmask results in vastly improved photoresist selectivity, making litho+etch of small features much better.
**Layer stack looks like: SiO2 (or other dielectric target layer to etch) / Ru hardmask / SiO2 hardmask (thin) / Photoresist.
**Typically strip the masks+PR with all dry etching. That means the entire etch process (all etches and strips) can be run ''in situ'' on the Panasonic ICP in a rapid single-tool etch process.
===Process Control: SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
[[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots''']

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===
[[File:SEM Image.png|thumb|New PR Strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Old PR strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**45sec-1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=
'''Panasonic ICP#1 is currently down -''' Use Panasonic ICP#2 instead. Most processes directly transfer with only small change in etch rate. Data kept here for historical purposes only.

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure & Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get on the ''back'' of the carrier wafer or you will get Helium cooling errors.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch, and see their SEM's.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
**''This etch is used in our Process Control weekly cals run by [[Process Group Interns|NanoFab Interns]]. Very stable over time ±5%.''
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

===Process Control: SiO2 Etch with CHF3/CF4 (Panasonic 2)===
[[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|thumb|269x269px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts] for SiO2 etching.|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]''Weekly cal etches of the CF4/CHF3 SiO2 etch, run by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots''']

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*GaAs Etch Cal - ''Noah Dutra & Fatt Foong, 2025-02-12''
**Etch Rates ~1um/min, Selectivity to SiO2 ~ 27:1, Sidewalls ~ 90°
**Etch Rate/Selectivity [https://wiki.nanofab.ucsb.edu/w/images/7/76/GaAs_pressure_experiment.png highly sensitive to pressure] (image credit: Terry Guerrero)
**Cal Sample: ~1cm sample etched mounted with oil onto 150mm Si carrier
**Recipe: 0.5Pa, 100/900W, N2/Cl2=10/20sccm
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf Non-Calibration GaAs Etch Recipes - Panasonic 2 - Cl2N2]

===Process Control: GaAs Etch with N2/Cl2 (Panasonic 2)===
[[File:GaAs Etch ICP2 SPC.png|alt=example ICP2 process control chart|thumb|249x249px|[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for GaAs etching.|link=https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281]]
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=0#gid=0 GaAs Etch with N2/Cl2 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 GaAs Etch with N2/Cl2 - '''Plots''']

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

=== Process Tips ===
* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* InP requires fairly high temperatures for making the Indium products volatile - so going to full-wafers (which are cooler) may requiring the table temperature. We have found that temperatures of ~150⁰C minimum may be required for preventing grassing etc.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==InP Ridge Etch (Oxford ICP Etcher)==
===High-Temp (200°C) InP Etch Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
[[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|thumb|218x218px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for 200°C InP Etch|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

===Low-Temp (60°C) InP Etch Process===
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: Low-Temp (60°C) InP Etch ====
[[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts] for 60°C InP Etch|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots''']

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
[[File:Dot Facet 00.jpg|alt=Example SEM image|thumb|170x170px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]
*''[https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: GaN Etch ====
[[File:GaN SPC.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279|219x219px]]Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]
==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning
*''[https://wiki.nanofab.ucsb.edu/w/images/d/d1/GaAs_Etch_Ver3_Recipe_Finalized_120925.pdf Std GaAs Etch - Cl2/N2 - 30C Etch Characterization] - F. Foong, 2025-12-10''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

ICP Etching Recipes

2026-02-10T01:12:27Z

Noahdutra: /* Analogous FICP Recipes (DSEiii) */

{{recipes|Dry Etching}}

=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''[[ICP Etching Recipes#Process Control Data (DSEiii)|Process Control Data below]]''' - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==Edge-Bead Removal (DSEiii)==
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

==Analogous FICP Recipes (DSEiii)==
Make sure to remove photoresist from edges of wafer. These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf The comparison sheet of both cals].

*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01
**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
**Smooth, Vertical, E.R. uniformity is within 5% on wafer
**Tested with 4" wafers that are ~50% open with UV6 PR
*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01
**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
**Vertical/Smooth
**Tested by mounting 1cmx1cm piece with oil on 4" Si

==High Rate Bosch Etch (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png|alt=Example SEM image|thumb|188x188px|Example of 100µm Deep Bosch Etched Silicon posts with Al2O3 hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
***Old Recipe Name: "'''''Plasma-Therm Standard DSE'''''" - lower EtchA, less tolerant
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
***Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
***To reduce roughening/grassing ("black silicon"), Increase "''Etch A''" ''t''ime by ~50%. Alternatively, reduce "''Dep''" step time by ~20%.
**Patterns with different exposed/etched areas will have different "optimal" parameters.
**This recipe has 2s Etch A time compared to "'''''Plasma-Therm Standard DSE'''''" (which has 1.5s Etch A) below - this reduced the undercut of mask to ~1% of the etch depth and the effect of [https://wiki.nanofab.ucsb.edu/w/images/a/a1/Cal_vs_Legacy_DSE.png aspect ratio on etch rate]. All other recipe parameters are the same.
**Selectivity to Photoresist ~60.
**Selectivity to SiO2 should be higher, not yet measured.
**Selectivity to Al2O3 is extremely high, >9000. See below TSV process for processing tips with Al2O3 hardmask.
**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
**<1% center to edge variability in etch rate.
**Larger open area → lower selectivity & lower etch rate.
**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO2 hardmask or the Al2O3/SiO2 hardmask below.
{|
|[[File:Plasmatherm DSE - 40um deep Si etch Cal 241007 - 30D 002.jpg|alt=Tilted SEM of 40um deep etch|none|thumb|250x250px|~40µm deep Silicon etch, run as Process Control "EtchCal" (''Process Development and Image: [[Noah Dutra]], 2024-10-07'')]]
|[[File:DSE_16um_Bosch_Etch_-_22_013.jpg|alt=Example SEM image|none|thumb|250x250px|Example of 16.32µm Deep Etched Silicon with 650nm thick UV6 Photoresist mask, 2µm Pitch. (''Image Credit: [[Noah Dutra]] 2024-08'')]]
|}

=== '''Si Etching C4F8/SF6/Ar (PlasmaTherm DSEiii)''' ===
[[File:DSE plot.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281|232x232px]]
* Recipe: ''STD_Bosch_Si (⭐️Production),'' on 100mm Si Wafer with ~50% open area, photoresist mask, ~40µm deep

*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=0#gid=0 Si Etching with C4F8/SF6/Ar - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1xQcdUH560nT928miZMeP7xxQSwHz_a_EB9s_Kb1LSfg/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/Ar - '''Plots''']

===Through Silicon Via (TSV) etch (DSEiii)===
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:
<big>'''NOTE''': We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer! '''DO NOT RUN''' the wax-mounting process without discussing with staff first. ''(Through-wafer process with no wax is still acceptable.)'' -- [[Demis D. John|Demis]] 2024-03-11</big>

Staff is working on a dicing-tape mounted recipe, to be published here soon.
-- [[Demis D. John|Demis]] 2025-11-19
{| class="wikitable"
! colspan="2" |Process for Through-Wafer Silicon Etching
|-
|Process to etch through ~550µm Silicon
|''[[Demis D. John]] & [[Biljana Stamenic]] 2022-11-11. Please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]] if you use/modify this process.''
|-
|Deposit 150nm Al2O3 on either:

*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
|May need to do dep. rate check beforehand.
|-
|Deposit ~3nm SiO2, ''in situ'' (same machine as above)
|This improves adhesion to photoresist and prevents developer attacking the Al2O3.
|-
|Lithography - your preferred method. Needs approx. ≥500nm thick PR.
|
|-
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
|Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
|-
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
|''In situ'' PR strip appears to give better + faster results.
|-
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]

If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
|'''CONTACT [[Demis D. John|STAFF]]''' before attempting this step!

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
|-
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
'''''IMPORTANT''''' for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp.

Observe ''carefully'' for any wax protruding from between wafers - redo spin-clean as needed.
|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
|-
|DSEiii etch - reduce Dep step to eliminate grassing:

*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
*Rate ≈ 4.25µm / min
|Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

*Record Helium FLOW during recipe run, for next step (if He leaks).

*Ok to remove wafer, observe/measure, and re-load for etching.

*If see black grass and etch rate drops, may need to run an O2 plasma with [[Ashers (Technics PEII)|Technics PEii]] few min to remove polymer, Increase EtchA step time (eg. by 50-100%) and then continue the etch.
|-
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow out of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
Once this happens,

*Leave your wafer in the chamber, then

*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".
*Set to typical flow of normal process from above (Something like ~6sccm? Not sure. Exact value is not critical)
*Re-run the recipe with He on Flow-control only until etch is complete.
|
|-
|Strip Al2O3/SiO2 either with Buffered HF, or same Pan1/2 dry etch as above.
BHF: Eg. ~2min to fully remove SiO2 + Al2O3, with overetch.
|See etch BHF rates of the thin-films on [[Wet Etching Recipes#Table of Wet Etching Recipes|this table]].
|-
|IF wax-mounted - either

*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
**ACE/ISO clean (eg. POLOS) to remove wax.
|
|-
| colspan="2" |''If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.''
|}

==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
**Lower selectivity, lower etch rate, smoother sidewalls.

=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the [[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|'''Process Control Data below''']] - Staff/Intern-run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

===Recipe Tips===

*RF1: Bias Power (with DCV readback)
*RF2: ICP Power
*For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

==Si Etch Recipes (Fluorine ICP Etcher)==
[[File:PRStrip 019 (1).jpg|alt=Example SEM image|thumb|180x180px|Example of 1.65µm Deep Etched Silicon, 2µm Pitch. (Image Credit: Noah Dutra 2024-09)]]
*'''"SiVertHFv2" (⭐️Production)'''
**20mTorr, RF=18W, ICP=950W, C4F8/SF6/CF4=120/48/54sccm
***This recipe has 2x gas flow compared to "'''''SiVertHF'''''" below - this reduced the loading effect (dependence on % etched area).
**Selectivity Silicon:Photoresist ≈ 5
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
**89-90 degree etch angle, ie, vertical.
**High selectivity to Al2O3 masks.
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al2O3]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO2]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al2O3 etch] (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
**[[ICP Etching Recipes#Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher)|Process Control Data above]] - Staff/Intern-run Etches Weekly, tracked over time.
*Old Recipe: [//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask

===Process Notes/Observations===

*Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch. It's possible this is actually an effect of photoresist open-area - we have conflicting results.
**If you see very low etch rates, try the above SiO2 etch, or try a short [[ICP Etching Recipes#PR/BARC Etch (Fluorine ICP Etcher)|PR/BARC etch]].
*We have observed that full-wafers with small open area in ''photoresist masks'' might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

=== Process Control: Si Etching C4F8/SF6/CF4 (Fluorine ICP Etcher) ===
[[File:FICP-Si.png|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''

*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=0#gid=0 Si Etching with C4F8/SF6/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15iRs-JhfgkMto5rZVtG0hJjcLMiHy039_ahv2nus0UQ/edit?gid=1804752281#gid=1804752281 Si Etching with C4F8/SF6/CF4 - '''Plots''']

==SiO2 Etch Recipes (Fluorine ICP Etcher)==
[[File:FL-ICP_50W_SiO2_etch_with_Ru_Hard_Mask.png|alt=SEM of FL-ICP 50W SiO2 etch with Ru Hard Mask|thumb|266x266px|50W SiO2 Etch w/ Ru Hardmask]]
[[File:FL-ICP_200W_SiO2_Etch_with_Ru_Hardmask_-_Ning_Cao.png|alt=SEM of FL-ICP 200W SiO2 Etch with Ru Hardmask - Ning Cao|thumb|266x266px|200W SiO2 Etch w/ Ru Hardmask (Ning Cao)]]
*'''"SiO2 Etch-50W" (⭐️Production)'''
**3.8mT, RF=50W, ICP=900W, CHF3/CF4=10/30sccm
**SiO2 etch rate: ~250nm/min
**Selectivity SiO2:Photoresist ≈ 1.10–1.20
**Selectivity SiO2:Ru ≈ 36
**[[ICP Etching Recipes#SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)|Process Control Data Above]] - Staff/Intern-run Etches Weekly, tracked over time.

=== [//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] ===

* Click above for [http://wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf Full Process Traveler]
** Process written for Sputtered Ru & I-Line GCA Stepper litho
** Can be transferred to ALD Ru or DUV/EBL Litho.

*''Ning Cao & Bill Mitchell, 2019-06''
*''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
*''Etch also works well with PR masking''
*''Chemistry: CHF3/CF4''
*''Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.''
*Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
*50W Bias: ('''recommended''')
**Selectivity to photoresist: 1.10–1.20
**SiO2 selectivity to Ru: 36
**SiO2 etch rate: 263nm/min
**''Smoothest vertical etch for SiO2.''
*200W Bias: (higher etch rate)
**SiO2 selectivity to Ru: 38
**SiO2 etch rate: 471nm/min
*This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
*Updates: Many users have found that SiO2-masking the Ru hardmask results in vastly improved photoresist selectivity, making litho+etch of small features much better.
**Layer stack looks like: SiO2 (or other dielectric target layer to etch) / Ru hardmask / SiO2 hardmask (thin) / Photoresist.
**Typically strip the masks+PR with all dry etching. That means the entire etch process (all etches and strips) can be run ''in situ'' on the Panasonic ICP in a rapid single-tool etch process.
===Process Control: SiO2 Etching with CHF3/CF4 (Fluorine ICP Etcher)===
[[File:FL-ICP Process Control Data Example.jpg|alt=example of Process Control Charts|thumb|242x242px|[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281]]''Full Wafer Si etching with ~50% open area and resist mask, run weekly by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit?usp=sharing SiO2 Etching with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/15hYkCqL3UNNayt4sXrvVi4mBj-OSdnF7PE29mQW9AEY/edit#gid=1804752281 SiO2 Etching with CHF3/CF4 - '''Plots''']

==Si3N4 Etching (Fluorine ICP Etcher)==
<code>Developed by Bill Mitchell. Please see [[Frequently Asked Questions#Publications acknowledging the Nanofab|publication policy]].</code>

*ICP = 950/75W
*Pressure = 5mT
*Low Polymer Dep: CF4 = 60sccm
**Etch Rate = 420nm/min (PECVD Si3N4)
*Higher verticality: CF4 = 35 / CHF3 = 25 sccm
**Etch Rate = 380nm/min (PECVD Si3N4)

==Photoresist & ARC (Fluorine ICP Etcher)==
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.

===PR/BARC Etch (Fluorine ICP Etcher)===
[[File:SEM Image.png|thumb|New PR Strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)_V2''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
[[File:SEM Image of wafer after PR strip.png|thumb|294x294px|Old PR strip recipe: Wafer had UV6 or UVN30 as mask. 5min Si etch followed by '''PostBARC Etch/PR Strip (STD)''' with 2min over etch (Credit: [[Gopikrishnan G M|Gopi Meena]])]]
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
**~60nm thick (2500krpm)
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
**45sec-1min

=== Photoresist Strip/Polymer Removal (Fluorine ICP Etcher) ===
'''Old''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)'''
*O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
*75W Bias can be helpful for difficult to remove polymers, eg. 2min
*Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
*Not able to completely remove PR (both negative & positive) after prolonged over etching (over etching of +2min)
*Leaves behind residue on the sides

'''New''' PR strip recipe: '''PostBARC Etch/PR Strip (STD)_V2'''
*O2=100sccm / 5mT / RF1(bias)=100W / RF2(icp)=825W
*RF bias increased by 10x to 100W
*Able to completely remove PR (both negative & positive) after over etching (over etching of +2min)
*Clean surface with no residue

==Cleaning Procedures (Fluorine ICP Etcher)==
''To Be Added''

=[[ICP Etch 1 (Panasonic E646V)]]=
'''Panasonic ICP#1 is currently down -''' Use Panasonic ICP#2 instead. Most processes directly transfer with only small change in etch rate. Data kept here for historical purposes only.

==SiO2 Etching (Panasonic 1)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"]
**Etch rate ≈ 2300Å/min (users must calibrate)
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''

*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO2 CHF3 Etch Variations] - CHF3 with varying Bias and Pressure & Slanted SiO2 etching

==SiNx Etching (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiNx Etch Rates and Variations - CF4-O2]

==Al Etch (Panasonic 1)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl2BCl3]
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl3 Erosion Issue and the Solution]

==Cr Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl2O2]

==Ta Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3

==Ti Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl2Ar]
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].

==W-TiW Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF6Ar]

==GaAs-AlGaAs Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar]
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation]

==GaN Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl2N2]
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl3-SF6]

==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

==SiC Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF6]

==Sapphire Etch (Panasonic 1)==

*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl3-Cl2]

==Cleaning Recipes==
'''''To Be Added'''''

==Old Deleted Recipes==
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

==Process Control Data (Panasonic 1)==

===SiO2 Etch with CHF3/CF4 - Process Control Data (Panasonic 1)===

*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots'''][[File:ICP1 Process Control Data Example.jpg|alt=example chart of ICP1 SiO2 Process Control Chart|none|thumb|250x250px|[https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281 Click for Process Control Charts]|link=https://docs.google.com/spreadsheets/d/1gBqCYXSl7IqpNL-yI11cuURlfZpTWwXUVM9hY_gGpT8/edit#gid=1804752281]]

=[[ICP Etch 2 (Panasonic E626I)]]=
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

=== Process Tips ===

* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get on the ''back'' of the carrier wafer or you will get Helium cooling errors.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch, and see their SEM's.

==SiO2 Etching (Panasonic 2)==

===Recipes===

*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO2 Vertical Etch Recipe#2 - CF4/CHF3]
**''This etch is used in our Process Control weekly cals run by [[Process Group Interns|NanoFab Interns]]. Very stable over time ±5%.''
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO2 Nanoscale Etch Recipe - CHF3/O2]
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO2 Vertical Etch Recipe - CHF3 "SiOVert"]
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].

===Recipe Variations===
''Use these to determine how etch parameters affect the process.''

*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]

===Process Control: SiO2 Etch with CHF3/CF4 (Panasonic 2)===
[[File:ICP2 Process Control Data Example.jpg|alt=example ICP2 process control chart|thumb|269x269px|[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 Click for Process Control Charts] for SiO2 etching.|link=https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281]]''Weekly cal etches of the CF4/CHF3 SiO2 etch, run by [[Process Group Interns|NanoFab Interns]].''
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit?usp=sharing SiO2 Etch with CHF3/CF4 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/1m0l_UK2lDxlgww4f6nfXe4aQedNeDZsLs46jQ5wR4zw/edit#gid=1804752281 SiO2 Etch with CHF3/CF4 - '''Plots''']

==SiNx Etching (Panasonic 2)==

*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiNx Nanoscale Etch Recipe - CHF3/O2]

==Al Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]

==Al2O3 Etching (Panasonic 2)==
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)

''Contributed by Brian Markman, 2018''

*BCl3 = 30sccm
*Pressure = 0.50 Pa
*ICP Source RF = 500
*Bias RF = 50W or 250W (250W can burn PR)
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

==GaAs Etch (Panasonic 2)==

*GaAs Etch Cal - ''Noah Dutra & Fatt Foong, 2025-02-12''
**Etch Rates ~1um/min, Selectivity to SiO2 ~ 27:1, Sidewalls ~ 90°
**Etch Rate/Selectivity [https://wiki.nanofab.ucsb.edu/w/images/7/76/GaAs_pressure_experiment.png highly sensitive to pressure] (image credit: Terry Guerrero)
**Cal Sample: ~1cm sample etched mounted with oil onto 150mm Si carrier
**Recipe: 0.5Pa, 100/900W, N2/Cl2=10/20sccm
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf Non-Calibration GaAs Etch Recipes - Panasonic 2 - Cl2N2]

===Process Control: GaAs Etch with N2/Cl2 (Panasonic 2)===
[[File:GaAs Etch ICP2 SPC.png|alt=example ICP2 process control chart|thumb|249x249px|[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for GaAs etching.|link=https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281]]
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=0#gid=0 GaAs Etch with N2/Cl2 - '''Etch Data''']
*[https://docs.google.com/spreadsheets/d/16gHOO3PQn_LinrXGPeSTSBf5dnw3leSLh1gq0PLr43w/edit?gid=1804752281#gid=1804752281 GaAs Etch with N2/Cl2 - '''Plots''']

==Photoresist and ARC etching (Panasonic 2)==
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

===ARC Etching: DUV-42P or AR6 (Panasonic 2)===

*O2 = 40 sccm // 0.5 Pa
*ICP = 75W // RF = 75W
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])

===Photoresist Etch/Strip (Panasonic 2)===
Works very well for photoresist stripping

*O2 = 40 sccm // 1.0 Pa
*ICP = 350W // RF = 100W
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])

==Ru (Ruthenium) Etch (Panasonic 2)==

*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]

=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

=== Process Tips ===
* Use the Santovac oil for mounting small pieces to Silicon carrier wafers, or else your resist will burn! Increases thermal conduction to the cooled carrier wafer. (Full-wafers instead get direct Helium cooling.) Careful that the oil does not get anywhere near the outer clamp that holds the wafer down, or your wafer will get stuck.
** The oil fully dissolves in Acetone or NMP. You can clean oil off the back by wiping the back of the sample against an ACE-soaked wipe.
* InP requires fairly high temperatures for making the Indium products volatile - so going to full-wafers (which are cooler) may requiring the table temperature. We have found that temperatures of ~150⁰C minimum may be required for preventing grassing etc.
* See the '''Process Control sections below''' - [[Process Group Interns|NanoFab Interns]] run Etches Weekly, tracked over time.
** This tells you whether the chamber and tool are operating properly before you run your etch.
** You can follow the intern's travelers for details of their etch.

==InP Ridge Etch (Oxford ICP Etcher)==
===High-Temp (200°C) InP Etch Process===

*InP Ridge Etch 200°C - ''Noah Dutra & Fatt Foong, 2025-08-12''
**Etch rates ~2 um/min, Selectivity to SiO2 ~ 30:1, Sidewalls ~90°
**Very dependent on open area, more area => lower E.R.s
**Cal Sample: ~1cm sample etched with 1 quarter of blank 50mm InP seasoning wafer placed '''without''' mounting adhesive on blank Silicon carriers (rough side up).
**Recipe: Cl2/H2/Ar - 200°C

==== Process Control: High-Temp (200°C) InP Etch ====
[[File:200C InP.png|alt=example SPC chart for Oxford ICP Etcher|thumb|218x218px|[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 Click for Process Control Charts] for 200°C InP Etch|link=https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281]]''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/H2/Ar @ 200°C, 1cm piece with ~50% SiO2 hardmask.''
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=0#gid=0 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1LE5Cug9uJFYEwu0ZsNsp0W1dTRzcO2EKFhC0wu3w0n4/edit?gid=1804752281#gid=1804752281 "Std InP Ridge Etch" Cl2/H2/Ar 200°C - '''Plots''']

===Low-Temp (60°C) InP Etch Process===
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
**''No longer calibrating 60°C process as of 05-2025''.
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2 - 60°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: Low-Temp (60°C) InP Etch ====
[[File:Oxford-ICP-Etch Process Control Data Example.jpg|alt=example SPC chart for Oxford ICP Etcher|thumb|225x225px|[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 Click for Process Control Charts] for 60°C InP Etch|link=https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281]]
2025-08-12: No longer run as weekly cal process, replaced by above 200°C Cl2/H2/Ar etch. Data below is for historical purposes only.
''Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.''

*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit?usp=sharing "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Etch Data Tables''']
*[https://docs.google.com/spreadsheets/d/1cEUB7K5BAg9N4vp3rPZw7g0orFkxeQmRkX34Fb4eZco/edit#gid=1804752281 "Std InP Ridge Etch" Cl2/CH4/H2/60°C - '''Plots''']

====[[Oxford Etcher - Sample Size Effect on Etch Rate|Sample Size effect on Etch Rate]]====
''See the above table for data showing effect on sample size/exposed etched area.''

==InP Grating Etch (Oxford ICP Etcher)==

*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
**Recipe: Cl2/CH4/H2/Ar - 20°C
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

== GaN Etch (Oxford ICP Etcher) ==
[[File:Dot Facet 00.jpg|alt=Example SEM image|thumb|170x170px|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]
*''[https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.

==== Process Control: GaN Etch ====
[[File:GaN SPC.png|alt=example of Process Control Charts|thumb|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279|219x219px]]Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]
==GaAs Etch (Oxford ICP Etcher)==
*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**Also tested etch with PR mask.
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning
*''[https://wiki.nanofab.ucsb.edu/w/images/d/d1/GaAs_Etch_Ver3_Recipe_Finalized_120925.pdf Std GaAs Etch - Cl2/N2 - 30C Etch Characterization] - F. Foong, 2025-12-10''
**Etch characterization on 1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has SiO hard mask
**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning

==GaN Atomic Layer Etching (Oxford ICP Etcher)==
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''

==Cleaning Recipes (Oxford ICP Etcher)==
'''''To Be Added: Required cleaning time & recipes'''''

Dry Etching Recipes

2026-02-10T01:11:18Z

Noahdutra:

===[[Process Group - Process Control Data#Etching .28Process Control Data.29|Process Control Data]]===
''See above [[Process Group - Process Control Data#Etching .28Process Control Data.29|linked page]] for [https://en.wikipedia.org/wiki/Statistical_process_control process control data] (dep rate/stress etc. over time), for a selection of often-used dry etches''

===Dry Etching Tools/Materials Table===

==== Process Maturity Ranking ====

* <code>'''R6'''</code> - most mature process with regular calibrations recorded on SPC charts.
* …
* <code>'''R1'''</code> - least mature - only run once ever.

''The Key/Legend for this table's <code>A...R6</code> values is at the [[Dry Etching Recipes#Process Ranking Table|bottom of the page]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center; font-size: 95%" border="1"
|-
! colspan="15" width="725" height="45" |<div style="font-size: 150%;">Dry Etching Recipes</div>
|- bgcolor="#d0e7ff"
| bgcolor="#eaecf0" |
! colspan="2" |'''[[RIE Etching Recipes|RIE Etching]]'''
! colspan="5" |'''[[ICP Etching Recipes|ICP Etching]]'''
! colspan="4" bgcolor="#d0e7ff" align="center" |'''[[Oxygen Plasma System Recipes|Oxygen Plasma Systems]]'''
! colspan="3" bgcolor="#d0e7ff" align="center" |'''[[Other Dry Etching Recipes|Other Dry Etchers]]'''
|- bgcolor="#d0e7ff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E646V)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ag
|
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|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Al Etch (Panasonic 1)|R1}}
|[[ICP Etching Recipes#Al Etch .28Panasonic 2.29|R2]]
|
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|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Au
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Cr
|
|[[RIE Etching Recipes|R2]]
|
|
|{{rl|ICP Etching Recipes|Cr Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Cu
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ge
|
|
|
|
|A
|R1
|
|
|
|
|
|[[Other Dry Etching Recipes|R2]]
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Mo
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!Nb
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ni
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|-
!Os
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Pt
|
|
|
|
|
|
|
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ru
|
|
|
|
|A
|[[ICP Etching Recipes#Ru .28Ruthenium.29 Etch .28Panasonic 2.29|R3]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Si
|
|
|[[ICP Etching Recipes#DSEIII .28PlasmaTherm.2FDeep Silicon Etcher.29|R6]]
|[[ICP Etching Recipes#Si Etch Recipes (Fluorine ICP Etcher)|R6]]
|
|
|R1
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Ta
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ti
|
|
|
|
|{{rl|ICP Etching Recipes|Ti Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |W
|
|
|
|R3
|{{rl|ICP Etching Recipes|W-TiW Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|-
!TiW
|
|
|
|R3
|
|R1
|
|
|
|
|
|
|
|
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |Al2O3
|
|
|
|
|A
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Al2O3 (Sapphire)
|
|
|
|
|{{rl|ICP Etching Recipes|Sapphire Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlGaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |AlGaN
|
|
|
|
|
|
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R2]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |AlN
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!BCB
|
|
|
|
|A
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |CdZnTe
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaAs
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaAs-AlGaAs Etch (Panasonic 1)}}
|[[ICP Etching Recipes#GaAs Etch .28Panasonic 2.29|R6]]
|[[ICP Etching Recipes#GaAs Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |GaN
|
|[[RIE Etching Recipes|R3]]
|
|
|{{rl|ICP Etching Recipes|GaN Etch (Panasonic 1)}}
|R1
|[[ICP Etching Recipes#GaN Etch .28Oxford ICP Etcher.29|R6]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |GaSb
|
|
|
|
|A
|R1
|R1
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |HfO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InGaAlAs
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|R1
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |InGaAsP
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R3]]
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |InP
|[[RIE Etching Recipes|R3]]
|
|
|
|A
|R1
|[[ICP Etching Recipes#InP Ridge Etch .28Oxford ICP Etcher.29|R6]]
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ITO
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|-
!LiNbO3
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
!Photoresist & Organics
|
|[[RIE Etching Recipes#Photoresist and ARC (RIE 5)|R3]]
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|[https://wiki.nanotech.ucsb.edu/wiki/ICP_Etching_Recipes#Photoresist_and_ARC_Etching_.28Panasonic_1.29 R3]
|[[ICP Etching Recipes#Al2O3 Etching .28Panasonic 2.29|R3]]
|
|R3
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|R1
|-
!ARC (Anti Reflective Coating)
|
|
|
|[[ICP Etching Recipes#Photoresist .26 ARC .28Fluorine ICP Etcher.29|R3]]
|
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiC
|
|
|
|
|{{rl|ICP Etching Recipes|SiC Etch (Panasonic 1)}}
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiN
|
|
|
|[[ICP Etching Recipes#Si3N4 Etching .28Fluorine ICP Etcher.29|R3]]
|{{rl|ICP Etching Recipes|SiNx Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiNx Etching .28Panasonic 2.29|R3]]
|
|[[Oxygen Plasma System Recipes#O2 Ashing|R3]]
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |SiO2
|
|
|R3
|[[ICP Etching Recipes#SiO2 Etch Recipes (Fluorine ICP Etcher)|R6]]
|{{rl|ICP Etching Recipes|SiO2 Etching (Panasonic 1)}}
|[[ICP Etching Recipes#SiO2 Etching .28Panasonic 2.29|R6]]
|
|
|
|
|
|
|[[Other Dry Etching Recipes|R3]]
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |SiOxNy
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|-
!SU8
|
|
|
|
|A
|
|
|
|
|
|
|
|
|
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |Ta2O5
|
|
|
|
|A
|R1
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |TiN
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |TiO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZnS
|[[RIE Etching Recipes|R3]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |ZnSe
|[[RIE Etching Recipes|R2]]
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#ffffff"
! bgcolor="#d0e7ff" align="center" |ZrO2
|
|
|
|
|
|
|
|
|
|
|
|
|
|R1
|- bgcolor="#eeffff"
! bgcolor="#d0e7ff" align="center" |'''Material'''
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_2_.28MRC.29|RIE 2 (MRC)]]
| bgcolor="#daf1ff" |[[RIE_Etching_Recipes#RIE_5_.28PlasmaTherm.29|RIE 5 (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP_Etching_Recipes#DSEIII_.28PlasmaTherm.2FDeep_Silicon_Etcher.29|DSEIII (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#PlasmaTherm.2FSLR Fluorine Etcher|Fluorine ICP (PlasmaTherm)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 1 .28Panasonic E646V.29|ICP Etch 1 (Panasonic E626I)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#ICP Etch 2 .28Panasonic E626I.29|ICP Etch 2 (Panasonic E640)]]
| bgcolor="#daf1ff" |[[ICP Etching Recipes#Oxford ICP Etcher .28PlasmaPro 100 Cobra.29|Oxford ICP (PlasmaPro 100)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29|Ashers (Technics PEII)]]
| bgcolor="#daf1ff" |[[Oxygen Plasma System Recipes#Plasma Clean .28YES EcoClean.29|Plasma Clean (YES EcoClean)]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#UV_Ozone_Reactor|UV Ozone Reactor]]
| bgcolor="#daf1ff" |[[Oxygen_Plasma_System_Recipes#Plasma_Activation_.28EVG_810.29|Plasma Activation (EVG 810)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#XeF2_Etch_.28Xetch.29|XeF2 Etch (Xetch)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#Vapor_HF_Etch_.28uETCH.29|Vapor HF Etch (uETCH)]]
| bgcolor="#daf1ff" |[[Other_Dry_Etching_Recipes#CAIBE_.28Oxford_Ion_Mill.29|CAIBE (Oxford)]]
|}

===Process Ranking Table===
Processes in the table above are ranked by their "''Process Maturity Level''" as follows:
{| class="wikitable"
!Process Level
! colspan="11" |Description of Process Level Ranking
|-
|A
| colspan="11" |Process '''A'''llowed and materials available but never done
|-
|R1
| colspan="11" |Process has been ran at least once
|-
|R2
| colspan="11" |Process has been ran and procedure is documented
|-
|R3
| colspan="11" |Process has been ran, procedure is documented, and data is available
|-
|R4
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''no''' in-Situ control available
|-
|R5
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''and''' in-Situ control available
|-
|R6
| colspan="11" |Process has a documented procedure and control charts/limits available. Controlled process.
|}
[[Category:Processing]]

2025-08-21T21:15:26Z

Noahdutra: /* Process Ranking Table */ changed ranking table and all R4s to R3s

__NOTOC__
{| class="wikitable"
|+
!Table of Contents
|-
|
==='''<big>Photolithography Processes</big>'''===

#'''UV Optical Lithography'''
#*[[#PositivePR |'''Stocked Lithography Chemical + Datasheets''']]
#**''Lists all stocked photolith. chemicals, PRs, strippers, developers, and links to the chemical's application notes/datasheet, which detail the spin curves and nominal processes.''
#*[[#Photolithography_Recipes |'''Photo Lithography Recipe section''']]
#**''Starting recipes (spin, bake, exposure, develop etc.) for all photolith. tools.''
#**''Substrate/surface materials/pattern size can affect process parameters. Users may need to run Focus/Exposure Arrays/Matrix (FEA's/FEM's) with these processes to achieve high-resolution.''
#**[[Contact Alignment Recipes|Contact Aligner Recipes]]
#***[[Contact Alignment Recipes#Suss Aligners .28SUSS MJB-3.29|Suss MJB Aligners]]
#***[[Contact Alignment Recipes#Contact Aligner .28SUSS MA-6.29|Suss MA6]]
#**[[Stepper Recipes|Stepper Recipes]]
#***[[Stepper Recipes#Stepper 1 .28GCA 6300.29|Stepper #1: GCA 6300]] (I-Line)
#***[[Stepper Recipes#Stepper 2 .28AutoStep 200.29|Stepper #2: GCA Autostep 200]] (I-Line)
#***[[Stepper Recipes#Stepper 3 .28ASML DUV.29|Stepper #3: ASML PAS 5500/300]] (DUV)
#**[[Direct-Write Lithography Recipes|Direct-Write Recipes]]
#***[[Direct-Write Lithography Recipes#Maskless Aligner .28Heidelberg MLA150.29|Heidelberg MLA150]]
#***[[Lithography Recipes#E-Beam Lithography Recipes|JEOL JBX-6300FS EBL]]
#***[[Lithography Recipes#FIB Lithography Recipes .28Raith Velion.29|Raith Velion FIB]]
#**[[Lithography Recipes#Automated Coat.2FDevelop System Recipes .28S-Cubed Flexi.29|Automated Coater Recipes (S-Cubed Flexi)]]
#[[Lithography Recipes#General Photolithography Techniques|'''General Photolithography Techniques''']]
#*''Techniques for improving litho. or solving common photolith. problems.''
#*[[Photolithography - Improving Adhesion Photoresist Adhesion|HMDS Process for Improving Adhesion]]
#*[[Photolithography - Manual Edge-Bead Removal Techniques|Edge-Bead Removal Techniques]]
#*[https://www.microchemicals.com/technical_information/reflow_photoresist.pdf Photoresist reflow (MicroChem)]
#*[[Lithography Calibration - Analyzing a Focus-Exposure Matrix]]
#'''[[Lithography Recipes#Lift-Off Recipes|Lift-Off Recipes]]'''
#*''Verified Recipes for lift-off using various photolith. tools''
#*''General educational description of this technique and it's limitations/considerations.''
#'''E-beam Lithography'''
#*[[#E-Beam_Lithography_Recipes |E-Beam Lithography Recipes]]
#**''Has links to starting recipes. Substrates and patterns play a large role in process parameters.''
#*[[#EBLPR |EBL Photoresist Datasheets]]
#**''Provided for reference, also showing starting recipes and usage info.''
#'''[[Lithography Recipes#Holography Recipes|Holography]]'''
#*''For 1-D and 2-D gratings with 220nm nominal period, available on substrates up to 1 inch square.''
#*''Recipes for silicon substrates are provided, and have been translated to other substrates by users.''
#*''Datasheets are provided with starting recipes and usage info.''
#'''[[Lithography Recipes#Edge-Bead Removal Techniques|Edge-Bead Removal]]'''
#*''Edge photoresist removal methods needed for clamp-based etchers''
#*''Improves resolution for contact lithography''
|-
|

==='''<big>Photolithography Chemicals/Materials</big>'''===

#'''[[#Underlayers |Underlayers]]'''
#*''These are used beneath resists for both adhesive purposes and to enable bi-layer lift-off profiles for use with photoresist.''
#*''Datasheets are provided.''
#'''[[#AntiReflectionCoatings |Anti-Reflection Coatings]]''':
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Bottom Anti-Reflection Coatings (BARC) are used in the stepper systems, underneath the resists to eliminate substrate reflections that can affect resolution and repeatability for small, near resolution limited, feature sizes.''
#*''Datasheets are provided for reference on use of the materials.''
#'''[[#ContrastEnhancement |Contrast Enhancement Materials (CEM)]]'''
#*[[#Photolithography_Recipes |The Photoresist Recipes]] section contains recipes using these materials.
#*''Used for resolution enhancement. Not for use in contact aligners, typically used on I-Line Steppers.''
#*''Datasheets provided with usage info.''
#'''[[#AdhesionPromoters |Adhesion Promoters]]'''
#*''These are used to improve wetting of photoresists to your substrate.''
#*''Datasheets are provided on use of these materials.''
#'''[[#SpinOnDielectrics |Low-K Spin-on Dielectrics]]'''
#*[[Lithography Recipes#SpinOnDielectrics|Spin-On Dielectrics]]
#**''Datasheets for BCB, Photo-BCB, and SOG (spin-on-glass) for reference on use.''
#*[[#Low-K_Spin-On_Dielectric_Recipes |Low-K Spin-On Dielectric Recipes]]
#**''Recipes for usage of some spin-on dielectrics.''
#'''[[#Developers |Developers and Removers]]'''
#*''Datasheets provided for reference.''
#*''Remover and Photoresist Strippers are used to dissolve PR during lift-off or after etching.''
|}

==General Photolithography Techniques==

====[[Photolithography - Improving Adhesion Photoresist Adhesion|'''HMDS Process for Improving Adhesion''']]====

*''Use these procedures if you are finding poor adhesion PR lifting-off), or for chemicals (like BHF) that attack the PR adhesion interface strongly.''

====[[Photolithography - Manual Edge-Bead Removal Techniques|'''Edge-Bead Removal Techniques''']]====

*''These techniques are required for loading full-wafers into etchers that use top-side clamps, to prevent photoresist from sticking to the clamp (and potentially destroying your wafer).''
*''For contact lithography, this improves the proximity of the mask plate and sample, improving resolution. For some projection systems, such as the [[Maskless Aligner (Heidelberg MLA150)|Maskless Aligner]], EBR can help with autofocus issues.''

====[https://www.microchemicals.com/technical_information/reflow_photoresist.pdf '''Photoresist reflow (MicroChem)''']====

*''To create slanted sidewalls or curved surfaces.''
[[Lithography Calibration - Analyzing a Focus-Exposure Matrix|'''Lithography Calibration - Analyzing a Focus-Exposure Matrix''']]

* ''On tools with autofocus (steppers & direct-write litho tools), you calibrate your litho by shooting a "Focus Exposure Matrix/Array", or "FEM/FEA", which exposes a grid with Dose varying in one axis, and Focus varying in the other.''
* ''Explains how to locate the'' ''"Process Window" for your lithography.''

==Photolithography Recipes==

*'''R''': ''Recipe is available. Clicking this link will take you to the recipe.''
*'''A''': ''Material is available for use, but no recipes are provided.''

==='''Process Ranking Table'''===
Processes in the table above are ranked by their "''Process Maturity Level''" as follows:
{| class="wikitable"
!Process Level
! colspan="11" |Description of Process Level Ranking
|-
|A
| colspan="11" |Process '''A'''llowed and materials available but never done
|-
|R1
| colspan="11" |Process has been ran at least once
|-
|R2
| colspan="11" |Process has been ran and procedure is documented
|-
|R3
| colspan="11" |Process has been ran, procedure is documented, and data is available
|-
|R4
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data
|-
|R5
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''and''' in-Situ control available
|-
|R6
| colspan="11" |Process has a documented procedure and control charts/limits available. Controlled process.
|}
''Click the tool title to go to recipes for that tool.''

''Click the photoresist title to get the datasheet, also found in [[Lithography Recipes#Chemicals Stocked .2B Datasheets|Stocked Chemicals + Datasheets]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|-
! colspan="7" height="45" |<div style="font-size: 150%;">Photolithography Recipes</div>

|-
| bgcolor="#EAECF0" |
! colspan="2" align="center" |'''[[Contact Alignment Recipes|<big>Contact Aligner Recipes</big>]]'''
! colspan="3" align="center" |'''[[Stepper Recipes|<big>Stepper Recipes</big>]]'''
! align="center" |[[Direct-Write Lithography Recipes|Direct-Write Litho. Recipes]]
|-
! width="150" bgcolor="#D0E7FF" align="center" |'''Positive Resists'''
{{LithRecipe Table}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[[:File:AXP4000pb-Datasheet.pdf|AZ4110]]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)|R1}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4210]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)|R1}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/fc/AXP4000pb-Datasheet.pdf AZ4330RS]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|A
|
|{{rl|MLA_Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/a2/Az_p4620_photoresist_data_package.pdf AZ4620]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/8b/OCG825-Positive-Resist-Datasheet.pdf OCG 825-35CS]
|A
|A
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-0.9]
|A
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)|R3}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)|R5}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)|R3}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/29/SPR955-Positive-Resist-Datasheet.pdf SPR 955 CM-1.8]
|A
|A
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)|R3}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)|R3}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)|R3}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-3.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)|R3}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)|R3}}
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/3f/SPR220-Positive-Resist-Datasheet.pdf SPR 220-7.0]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|{{rl|Stepper Recipes|Positive Resist (GCA 6300)|R3}}
|{{rl|Stepper Recipes|Positive Resist (AutoStep 200)|R3}}
|
|{{rl|MLA Recipes|Positive_Resist_.28MLA150.29}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/be/3600_D%2C_D2v_Spin_Speed_Curve.pdf THMR-IP3600 HP D]
|
|
|A
|A
|
|{{rl|MLA Recipes|Positive Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)|R5}}
|
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/f/ff/UV210-Positive-Resist-Datasheet.pdf UV210-0.3]
|
|
|
|
|{{rl|Stepper Recipes|Positive Resist (ASML DUV)}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/UV26-Positive-Resist-Datasheet.pdf UV26-2.5]
|
|
|
|
|A
|
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Negative Resists'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/b/b0/AZ5214-Negative-Resist-Datasheet.pdf AZ5214-EIR]
|{{rl|Contact_Alignment_Recipes|Negative Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2020]
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)|R3}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)|R3}}
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)|R3}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2035]
| bgcolor="#D0E7FF" |A
| {{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)|R1}}
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |A
| bgcolor="EEFFFF" |
| bgcolor="EEFFFF" |A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/5/5e/AZnLOF2020-Negative-Resist-Datasheet.pdf AZnLOF 2070]
|A
|A
|{{Rl|Stepper_Recipes|Negative_Resist_.28GCA_6300.29|R2}}
|A
|
|A
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/8/82/AZnLOF5510-Negative-Resist-Datasheet.pdf AZnLOF 5510]
|A
|A
|{{rl|Stepper Recipes|Negative Resist (GCA 6300)}}
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)}}
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/c/c9/UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf UVN30-0.8]
|
|
|
|
|{{rl|Stepper Recipes|Negative Resist (ASML DUV)|R6}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/7/78/SU-8-2015-revA.pdf SU-8 2005,2010,2015]
|A
|{{rl|Contact_Alignment_Recipes|Negative Resist (MA-6)}}
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/2/2c/SU-8-2075-revA.pdf SU-8 2075]
|A
|A
|A
|A
|
|{{rl|MLA Recipes|Negative Resist (MLA 150)}}
|-
| bgcolor="#D0E7FF" align="center" |NR9-[//wiki.nanotech.ucsb.edu/w/images/8/8f/NR9-1000PY-revA.pdf 1000],[//wiki.nanotech.ucsb.edu/w/images/7/71/NR9-3000PY-revA.pdf 3000],[//wiki.nanotech.ucsb.edu/w/images/f/f9/NR9-6000PY-revA.pdf 6000]PY
|{{rl|Contact_Alignment_Recipes|Positive Resist (MJB-3)}}
|{{rl|Contact_Alignment_Recipes|Positive Resist (MA-6)}}
|A
|{{rl|Stepper Recipes|Negative Resist (AutoStep 200)|R3}}
|
|A
|- bgcolor="EEFFFF"
! bgcolor="#D0E7FF" align="center" |'''Anti-Reflection Coatings'''
{{LithRecipe Table}}
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/3/33/XHRiC-Anti-Reflective-Coating.pdf XHRiC-11]
|
|
|A
|A
|
|A
|- bgcolor="EEFFFF"
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/0/07/DUV42P-Anti-Reflective-Coating.pdf DUV42-P]
|
|
|
|
|{{rl|Stepper Recipes|DUV-42P-6|R3}}
|
|-
| bgcolor="#D0E7FF" align="center" |[//wiki.nanotech.ucsb.edu/w/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101-304]
|
|
|
|
|{{rl|Stepper Recipes|DS-K101-304|R3}}
|
|-
! bgcolor="#D0E7FF" align="center" |
{{LithRecipe Table}}
|}


==Lift-Off Recipes==

*{{fl|Liftoff-Techniques.pdf|Lift-Off Description/Tutorial}}
**How it works, process limits and considerations for designing your process
*[[Lift-Off with I-Line Imaging Resist + LOL2000 Underlayer|I-Line Lift-Off: Bi-Layer Process with LOL2000 Underlayer]]
**''Single Expose/Develop process for simplicity''
**''Up to ~130nm metal thickness & ≥500nm-1000nm gap between metal.''
**''Can use any I-Line litho tool (GCA Stepper, Contact aligner, MLA)''
*{{fl|Bi-LayerContactprocesswithPMGI.pdf|I-Line Lift-Off: Bi-Layer Process with PMGI Underlayer and Contact Aligner}}
**''Multiple processes for Metal thicknesses ~800nm to ~2.5µm''
**''Uses multiple DUV Flood exposure/develop cycles to create undercut.''
**''Can be transferred to other I-Line litho tools (Stepper, MLA etc.)''
*[[Lift-Off with DUV Imaging + PMGI Underlayer|DUV Lift-Off: UV6 Imaging Resist + PMGI Underlayer]]
**''Single-expose/develop process''
**''Up to ~65nm metal thickness & ~350nm gap between metal''
**''Use thicker PMGI for thicker metals''

==[[E-Beam Lithography System (JEOL JBX-6300FS)|E-Beam Lithography Recipes (JEOL JBX-6300FS)]]==

*Under Development.

==[[Focused Ion-Beam Lithography (Raith Velion)|FIB Lithography Recipes (Raith Velion)]]==
''To Be Added''

==[[Automated Coat/Develop System (S-Cubed Flexi)|Automated Coat/Develop System Recipes (S-Cubed Flexi)]]==
Recipes pre-loaded on the S-Cubed Flexi automated coat/bake/develop system. Only staff may write new recipes, contact the tool supervisor for more info.

===Available Variations===

*We have different recipes with varyious UV6 spin speeds - the same spin speed optionss as found on our manual Headway spinners. This allows for PR thickness control. See the linked UV6 datasheets below for thickness vs. rpm spin curves. '''Note''' that exact spin RPM may be slightly different between Headway spinners (on benches) vs. S-Cubed.
*DSK is recommended to be spun at 1.5krpm (~40nm) for best anti-reflection properties. 5krpm (~20nm) recipes are also provided for historical/legacy processes.
*DSK can be baked at either 220C to act as a Dry-etchable BARC (similar to DUV-42P), or at lower temps as a developable BARC (no dry etch required).
*"Chain" recipes (with DSK+UV6 spin/cured in succession) are only available for DSK Baked at 185C & 220C, and all UV6 Spin-speed variations. For the other DSK temps you can use the single-PR "Routes".
*Developer recipes are now available for 300 MiF Developer. '''Note''' that developer is flowing continuously during the develop, so develop times are shorter by ~50% compared to beaker developing.
**'''DO NOT EDIT developer recipes''', they can damage the tool when programmed incorrectly!
*"Chain" recipes for 135*C Post-exposure Bake + Develop have been made.
*ASML cassettes can be placed directly on this tool for spin / exposure / develop process. Please make sure all cassettes are kept back at their respecting tools when done.

===Recipes Table (S-Cubed Flexi)===
{| class="wikitable"
|+''Ask [[Tony Bosch|Staff]] if you need a new recipe.''
|'''''Coating Material'''''
|'''''Route/Chain'''''
|'''''Name''': (User: "UCSB Users")''
|'''''Spin Speed (krpm)'''''
|'''''Bake Temp'''''
|'''''Notes'''''
|-
! colspan="6" |
|-
! colspan="6" |BEFORE LITHOGRAPHY (PR Coat and Bake)
|-
! colspan="6" |
|-
|'''''Hotplate Set'''''
|Route
| colspan="4" |To pre-set the DSK Hotplate temp (HP4).
Note: Only HP4 can be changed.

HP1-HP3 remains fixed at: HP1=135°C, HP2=170°C & HP3=170°C
|-
|
|
|HP4-SET-'''220C'''
|
|220°C
|Will over shoot +-2°C when done.
|-
|
|
|HP4-SET-'''210C'''
|
|210°C
|
|-
|
|
|HP4-SET-'''200C'''
|
|200°C
|
|-
|
|
|HP4-SET-'''185C'''
|
|185°C
|
|-
| colspan="6" |'''''Bottom Anti-Reflection Coating (BARC), DSK101 only:'''''
|-
|'''''[https://wiki.nanotech.ucsb.edu/wiki/images/a/af/DS-K101-304-Anti-Reflective-Coating.pdf DS-K101]'''''
|Route
| colspan="4" |''DSK101 Develop Rate depends on Bake temp - you can use this to control undercut.'' ''See: [[DS-K101-304 Bake Temp. versus Develop Rate|DSK Bake vs. Dev rate]]''
DSK101 spun at 1.5K is equivalent to DUV-42P. See: [[Stepper Recipes#Anti-Reflective Coatings]]

'''185°C bake''' allows the DSK to dissolve during develop, and allows for undercut (may lift-off small features)

'''220°C bake''' allows DSK to be used as dry-etchable BARC (equiv. to DUV42P), requiring O2 etch to remove. Better for small features. See [[Stepper Recipes#Anti-Reflective Coatings|here for relevant processing info from DUV42P]].

'''Note: All PR coat recipes have EBR backside clean steps included in the recipe.'''
|-
|''1.5krpm recipes''
|
|COAT-DSK101-304[1.5K]-'''185C'''
|1.5krpm
|185°C
|Requires: HP4=185°C,
|-
|
|
|COAT-DSK101-304[1.5K]-'''200C'''
|1.5krpm
|200°C
|Requires: HP4=200°C
|-
|
|
|COAT-DSK101-304[1.5K]-'''210C'''
|1.5krpm
|210°C
|Requires: HP4=210°C
|-
|
|
|COAT-DSK101-304[1.5K]-'''220C'''
|1.5krpm
|220°C
|Requires: HP4=220°C,
|-
| colspan="6" |
|-
|''5krpm recipes''
|
|COAT-DSK101-304[5K]-'''185C'''
|5.0krpm
|185°C
|Requires: HP4=185°C,
|-
|
|
|COAT-DSK101-304[5K]-'''200C'''
|5.0krpm
|200°C
|Requires: HP4=200°C
|-
|
|
|COAT-DSK101-304[5K]-'''210C'''
|5.0krpm
|210°C
|Requires: HP4=210°C
|-
|
|
|COAT-DSK101-304[5K]-'''220C'''
|5.0krpm
|220°C
|Requires: HP4=220°C,
|-
| colspan="6" |'''''Imaging resist (UV6) only:'''''
|-
|'''''[https://wiki.nanofab.ucsb.edu/w/images/3/38/UV6-Positive-Resist-Datasheet.pdf UV6-0.8]'''''
|Route
|COAT-UV6['''2K''']-135C
|2.0krpm
|135°C
|Requires: HP1=135°C
|-
|''varying spin speed''
|
|COAT-UV6['''2.5K''']-135C
|2.5krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6['''3K''']-135C
|3.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6['''3.5K''']-135C
|3.5krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6['''4K''']-135C
|4.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6['''5K''']-135C
|5.0krpm
|135°C
|Requires: HP1=135°C
|-
|
|
|COAT-UV6['''6K''']-135C
|6.0krpm
|135°C
|Requires: HP1=135°C
|-
| colspan="6" |'''''UV6 Coat with Developable BARC underlayer:'''''
|-
|'''''DS-K101 @ 185°C'''''
'''''+ UV6'''''
|Chain
|COAT-DSK101['''1.5K''']-185C-UV6['''2K''']-135C
|DSK: 1.5krpm
UV6: 2.0krpm
|DSK: 185°C
UV6: 135°C
|Requires:
– HP4=185°C

– HP1=135°C

Plan for ~10-15 min per wafer.
|-
|''1.5krpm DSK recipes with''
''UV6- various spin speeds''
|
|COAT-DSK101['''1.5K''']-185C-UV6['''2.5K''']-135C
|DSK: 1.5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''1.5K''']-185C-UV6['''3K''']-135C
|DSK: 1.5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''1.5K''']-185C-UV6['''3.5K''']-135C
|DSK: 1.5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''1.5K''']-185C-UV6['''4K''']-135C
|DSK: 1.5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''1.5K''']-185C-UV6['''5K''']-135C
|DSK: 1.5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''1.5K''']-185C-UV6['''6K''']-135C
|DSK: 1.5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |
|-
|''5krpm DSK recipes with''
''UV6- various spin speeds''
|
|COAT-DSK101['''5K''']-185C-UV6['''2K''']-135C
|DSK: 5krpm
UV6: 2.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''5K''']-185C-UV6['''2.5K''']-135C
|DSK: 5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''5K''']-185C-UV6['''3K''']-135C
|DSK: 5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''5K''']-185C-UV6['''3.5K''']-135C
|DSK: 5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''5K''']-185C-UV6['''4K''']-135C
|DSK: 5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''5K''']-185C-UV6['''5K''']-135C
|DSK: 5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''5K''']-185C-UV6['''6K''']-135C
|DSK: 5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |'''''UV6 Coat with Dry-Etchable BARC underlayer:'''''
|-
|'''''DS-K101 @ 220°C'''''
'''''+ UV6'''''
|Chain
|COAT-DSK101['''1.5K''']-220C-UV6['''2K''']-135C
|DSK: 1.5krpm
UV6: 2.0krpm
|DSK: 220°C
UV6: 135°C
|Requires:
– HP4=220°C

– HP1=135°C

Plan for ~10-15 min per wafer.
|-
|''1.5krpm DSK recipes with''
''UV6- various spin speeds''
|
|COAT-DSK101['''1.5K''']-220C-UV6['''2.5K''']-135C
|DSK: 1.5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''1.5K''']-220C-UV6['''3K''']-135C
|DSK: 1.5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''1.5K''']-220C-UV6['''3.5K''']-135C
|DSK: 1.5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''1.5K''']-220C-UV6['''4K''']-135C
|DSK: 1.5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''1.5K''']-220C-UV6['''5K''']-135C
|DSK: 1.5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''1.5K''']-220C-UV6['''6K''']-135C
|DSK: 1.5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
| colspan="6" |
|-
|''5krpm DSK recipes with''
''UV6- various spin speeds''
|
|COAT-DSK101['''5K''']-220C-UV6['''2K''']-135C
|DSK: 5krpm
UV6: 2.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''5K''']-220C-UV6['''2.5K''']-135C
|DSK: 5krpm
UV6: 2.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''5K''']-220C-UV6['''3K''']-135C
|DSK: 5krpm
UV6: 3.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''5K''']-220C-UV6['''3.5K''']-135C
|DSK: 5krpm
UV6: 3.5krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''5K''']-220C-UV6['''4K''']-135C
|DSK: 5krpm
UV6: 4.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''5K''']-220C-UV6['''5K''']-135C
|DSK: 5krpm
UV6: 5.0krpm
|same as above
|same as above
|-
|
|
|COAT-DSK101['''5K''']-220C-UV6['''6K''']-135C
|DSK: 5krpm
UV6: 6.0krpm
|same as above
|same as above
|-
! colspan="6" |
|-
! colspan="6" |AFTER LITHOGRAPHY (PEB and Developing)
|-
! colspan="6" |
|-
|'''''PEB Wafer Bake'''''
|Route
| colspan="4" |To bake wafer with UV6 after exposure (PEB) for 90sec and cool for 15sec
|-
|
|
|BAKE-135C-90S
|
|135°C
|Requires: HP1=135°C
|-
| colspan="6" |
|-
|'''''PEB and Developing'''''
|Route
| colspan="4" |To post-exposure bake wafer after exposure (std. PEB for UV6) 90sec, cool 15sec, develop using AZ300MIF and water rinse 60sec

'''WARNING''': DO NOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE (or equipment damage may occur!)
|-
|''Varying developer time''
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-'''10S'''
|Developer chuck: 300rpm
|135°C
|Requires: HP1=135°C
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-'''15S'''
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-'''20S'''
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-'''25S'''
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-'''30S'''
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-'''35S'''
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-'''40S'''
|same as above
|same as above
|same as above
|-
|
|
|BAKE-135C-90S-DEV[MIF300]-SPIN[300RPM]-'''45S'''
|same as above
|same as above
|same as above
|-
| colspan="6" |
|-
|'''Developing'''
|Route
| colspan="4" |To only develop wafer using AZ300MIF and water rinse 60sec (No PEB)

'''WARNING''': DO NOT USE ANY OTHER DEVELOPER RECIPES OTHER THAN THE ONES LISTED HERE (or equipment damage may occur!)
|-
|''Varying developer time''
|
|DEV[MIF300]-SPIN[300RPM]-'''10S'''
|Developer chuck: 300rpm
|135°C
|Requires: HP1=135°C
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-'''15S'''
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-'''20S'''
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-'''25S'''
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-'''30S'''
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-'''35S'''
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-'''40S'''
|same as above
|same as above
|same as above
|-
|
|
|DEV[MIF300]-SPIN[300RPM]-'''45S'''
|same as above
|same as above
|same as above
|-
|
|
|
|
|
|
|}
==[[Holographic Lith/PL Setup (Custom)|Holography Recipes]]==
''The Holography recipes here use the BARC layer XHRiC-11 & the high-res. I-Line photoresist THMR-IP3600HP-D.''

*{{fl|Holography_Process_for_1D-lines_and_2D-dots_%28ARC-11_%26_THMR-IP3600HP-D%29-updated-4-8-2021.pdf|Standard Holography Process - on SiO2 on Si}}
*{{fl|Holography-Process-Variation-revA.pdf|Holography Process Variations - Set-up Angle - Etching into SiO2 and Si}}
*{{fl|05-SiO2_Nano-structure_Etch.pdf|Etch SiO2 Nano-structure - Changing Side-wall Angle - Etching into Si with a different line-width}}
*{{fl|30-Redicing_Nanowire_Diameter_by_Thermal_Oxidation_and_Vapored_HF_Etch.pdf|Reduce SiO2 Nanowire Diameter - Thermal Oxidation - Vapor HF Etching}}

==Low-K Spin-On Dielectric Recipes==

*{{fl|Lithography-BCB-photo-lowk-dielectric-spinon-4024-40-revA.docx|Photo BCB (4024-40)}}
*{{fl|BCB-cyclotene-3000-revA.pdf|Standard BCB (3022-46)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|SOG (T512B)}}

==Chemicals Stocked + Datasheets==
''The following is a list of the lithography chemicals we stock in the lab, with links to the datasheets for each. The datasheets will often have important processing info such as spin-speed vs. thickness curves, typical process parameters, bake temps/times etc.''

Item numbers in (parentheses) indicate the specific stocked formulation, when the datasheet shows multiple formulations.
{|
|- valign="top"
| width="400" |
;<div id="PositivePR"><big>Positive Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AXP4000pb-Datasheet.pdf|AZP4000 (AZ4110, AZ4210, AZ4330)}}
*{{Fl|Az_p4620_photoresist_data_package.pdf|AZ P4620}}
*{{fl|OCG825-Positive-Resist-Datasheet.pdf|OCG825}}
*{{fl|SPR220-Positive-Resist-Datasheet.pdf|SPR220 (SPR220-3, SPR220-7)}}
*{{fl|SPR955-Positive-Resist-Datasheet.pdf|SPR955CM (SPR955CM-0.9, SPR955CM-1.8)}}
*THMR-3600HP (Thin I-Line & Holography)
**{{fl|THMR_iP_3500_iP3600.pdf|Evaluation Results: THMR-3600HP}}
**{{fl|3600_D,_D2v_Spin_Speed_Curve.pdf|Spin Curves for THMR-3600HP}}
**{{fl|THMR-iP3600_HP_D_20140801_(B)_GHS_US.pdf|Safety Datasheet for THMR-3600HP}}

'''''DUV-248nm'''''

*{{fl|UV210-Positive-Resist-Datasheet.pdf|UV210-0.3}}
*{{fl|UV6-Positive-Resist-Datasheet.pdf|UV6-0.8}}
*{{fl|UV26-Positive-Resist-Datasheet.pdf|UV26-2.5}}

;<div id="NegativePR"><big>Negative Photoresists</big></div>

'''''i-line and broadband'''''

*{{fl|AZ5214-Negative-Resist-Datasheet.pdf|AZ5214}}
*{{fl|AZnLOF5510-Negative-Resist-Datasheet.pdf|AZnLOF5510}}
*{{fl|AZnLOF2020-Negative-Resist-Datasheet.pdf|AZnLOF2000 (AZnLOF2020, AZnLOF2035, AZnLOF2070)}}
*{{fl|NR9-1000PY-revA.pdf|Futurrex NR9-1000PY(use AZ300MIF dev)}}
*{{fl|NR9-3000PY-revA.pdf|Futurrex NR9-3000PY(use AZ300MIF dev)}}
*{{fl|NR9-6000PY-revA.pdf|Futurrex NR9-6000PY(use AZ300MIF dev)}}
*{{fl|SU-8-2015-revA.pdf|SU-8-2005,2010, 2015}}
*{{fl|SU-8-2075-revA.pdf|SU-8-2075}}

'''''DUV-248nm'''''

*{{fl|UVN-30_-_Negative-Resist-Datasheet_-_Apr_2004.pdf|UVN-30-0.8}}

;<div id="Underlayers"><big>Underlayers</big></div>

*{{fl|PMGI-Underlayer-Datasheet.pdf|PMGI (PMGI SF3,5,8,11,15)}}
*{{fl|LOL2000-Underlayer-Datasheet.pdf|Shipley LOL2000}}

;<div id="EBLPR"><big>E-beam resists</big></div>

*{{fl|PMMA-E-Beam-Resist-Datasheet.pdf|PMMA (PMMA, P(MMA-MAA) copolymer)}}
*{{fl|maN2403-E-Beam-Resist-Datasheet.pdf|maN 2403}}

;<div id="NanoImprinting"><big>Nanoimprinting</big></div>

*{{fl|NX1020-Nanoimprinting-Datasheet.pdf|NX1020}}
*{{fl|MRI-7020-Nanoimprinting-Datasheet.pdf|MRI-7020}}
*{{fl|Mr-UVCur21.pdf|MR-UVCur21}}
*{{fl|OrmoStamp-NIL-Lithography-UV-Soft-RevA.pdf|Ormostamp}}

|
;<div id="ContrastEnhancement"><big>Contrast Enhancement Materials</big></div>

*{{fl|CEM365iS-Contrast-Enhancement-Datasheet.pdf|CEM365iS}}

;<div id="AntiReflectionCoatings"><big>Anti-Reflection Coatings</big></div>

*{{fl|XHRiC-Anti-Reflective-Coating.pdf|XHRiC-11 (i-line)}}
*{{fl|DUV42P-Anti-Reflective-Coating.pdf|DUV42P-6 (DUV) (For AR2 replacement)}}
*{{fl|DS-K101-304-Anti-Reflective-Coating.pdf|DS-K101-304 (DUV developable BARC)}}

;<div id="AdhesionPromoters"><big>Adhesion Promoters</big></div>

*HMDS
*AP3000 BCB Adhesion Promoter
*{{fl|OMNICOAT-revA.pdf|Omnicoat, SU-8 Adhesion Promoter}}
*{{fl|OrmoPrime-NIL-Adhesion-RevA.pdf|Ormoprime08-Ormostsmp Adhesion Promoter}}

;<div id="SpinOnDielectrics"><big>Spin-On Dielectrics</big></div>

''Low-K Spin-On Dielectrics such as Benzocyclobutane and Spin-on Glass''

*{{fl|BCB-cyclotene-3000-revA.pdf|BCB, Cyclotene 3022-46(Not Photosensitive)}}
*{{fl|BCB-cyclotene-4000-revA.pdf|PhotoBCB, Cyclotene 4024-40(Negative Polarity)}}
*{{fl|BCB-adhesion.pdf|BCB Adhesion Notes from Vendor}}
*{{fl|BCB-rework.pdf|BCB rework Notes from Vendor}}
*{{fl|512B-Datasheet-revA.pdf|Spin-on-Glass, Honeywell 512B (Not Photosensitive)}}
*{{fl|512B-Application-Data-Bake-revA.pdf|Honeywell 512B Apps Data}}

;<div id="Developers"><big>Developers</big></div>

*{{fl|AZ400K-Developer-Datasheet.pdf|AZ400K (AZ400K, AZ400K1:4)}}
*{{fl|AZ300MIF-Developer-Datasheet.pdf|AZ300MIF}}
*DS2100 BCB Developer
*SU-8 Developer
*101A Developer (for DUV Flood Exposed PMGI)

;<div id="PRRemovers"><big>Photoresist Removers</big></div>

*[http://www.microchemicals.com/products/remover_stripper/nmp.html AZ NMP]
**''This replaces {{fl|1165-Resist-Remover.pdf|1165}}''
*{{fl|AZ300T-Resist-Remover.pdf|AZ300T}}
*{{fl|RemoverPG-revA.pdf|Remover PG, SU-8 stripper}}
*AZ EBR ("Edge Bead Remover", PGMEA)

|}

[[Category: Processing]]
[[category: Lithography]]
[[category: Recipes]]

Vacuum Deposition Recipes

2025-08-21T21:10:42Z

Noahdutra: /* Process Ranking Table */ adjusted R4s to R3s, and added new table definition at bottom

===[[Process Group - Process Control Data#Deposition .28Process Control Data.29|Process Control Data]]===
''See [[Process Group - Process Control Data#Deposition .28Process Control Data.29|linked page]] for process control data (calibration data over time, such as dep. rate, refractive index, stress etc.) over time, for a selection of highly used tools/films.''

===Deposition Tools/Materials Table===

==== Process Maturity Ranking ====

* <code>'''R6'''</code> - most mature process with regular calibrations recorded on SPC charts.
* …
* <code>'''R1'''</code> - least mature - "possible" but you'll have to figure it out.

''The Key/Legend for this table's <code>R1...R6</code> values is at the [[Vacuum Deposition Recipes#Process Ranking Table|bottom of the page]].''
{| class="wikitable" style="border: 1px solid #D0E7FF; background-color:#ffffff; text-align:center;" border="1"
|- bgcolor="#d0e7ff"
! colspan="16" width="1675" height="45" |<div style="font-size: 150%;">Vacuum Deposition Recipes</div>
|- bgcolor="#d0e7ff"
| 
! colspan="4" bgcolor="#d0e7ff" align="center" |'''[[E-Beam Evaporation Recipes|E-Beam Evaporation]]'''
! colspan="4" |'''[[Sputtering Recipes|Sputtering]]'''
! colspan="2" bgcolor="#d0e7ff" align="center" |'''[[Thermal Evaporation Recipes|Thermal Evaporation]]'''
! colspan="3" bgcolor="#d0e7ff" align="center" |'''[[PECVD Recipes|Plasma Enhanced Chemical Vapor Deposition (PECVD)]]'''
! width="90" bgcolor="#d0e7ff" align="center" |'''[[Atomic Layer Deposition Recipes|Atomic Layer Deposition]]'''
! width="80" bgcolor="#d0e7ff" align="center" |'''[[Molecular Vapor Deposition Recipes|Molecular Vapor Deposition]]'''
|-
! width="20" bgcolor="#d0e7ff" align="center" |'''Material'''
| width="65" bgcolor="#daf1ff" |[[E-Beam Evaporation Recipes#E-Beam_1_.28Sharon.29|E-Beam 1 (Sharon)]]
| width="65" bgcolor="#daf1ff" |[[E-Beam Evaporation Recipes#E-Beam_2_.28Custom.29|E-Beam 2 (Custom)]]
| width="65" bgcolor="#daf1ff" |[[E-Beam Evaporation Recipes#E-Beam_3_.28Temescal.29|E-Beam 3 (Temescal)]]
| width="65" bgcolor="#daf1ff" |[[E-Beam Evaporation Recipes#E-Beam_4_.28CHA.29|E-Beam 4 (CHA)]]
| width="65" bgcolor="#daf1ff" |[[Sputtering_Recipes#Sputter_3_.28AJA_ATC_2000-F.29|Sputter 3 (AJA ATC 2000-F)]]
| width="65" bgcolor="#daf1ff" |[[Sputtering_Recipes#Sputter_4_.28AJA_ATC_2200-V.29|Sputter 4 (AJA ATC 2200-V)]]
| width="65" bgcolor="#daf1ff" |[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Sputter_5_.28AJA_ATC_2200-V.29 Sputter 5 (AJA ATC 2200-V)]
| width="55" bgcolor="#daf1ff" |[[Sputtering_Recipes#Ion_Beam_Deposition_.28Veeco_NEXUS.29|Ion Beam Deposition (Veeco Nexus)]]
| width="45" bgcolor="#daf1ff" |[[Thermal Evaporation Recipes#Thermal_Evap_1|Thermal Evap 1]]
| width="65" bgcolor="#daf1ff" |[[Thermal Evaporation Recipes#Thermal_Evap_2_.28Solder.29|Thermal Evap 2 (Solder)]]
| width="65" bgcolor="#daf1ff" |[[PECVD Recipes#PECVD_1_.28PlasmaTherm_790.29|PECVD 1 (PlasmaTherm 790)]]
| width="65" bgcolor="#daf1ff" |[[PECVD Recipes#PECVD_2_.28Advanced_Vacuum.29|PECVD 2 (Advanced Vacuum)]]
| width="65" bgcolor="#daf1ff" |[[PECVD_Recipes#ICP-PECVD_.28Unaxis_VLR.29|Unaxis VLR ICP-PECVD]]
| width="65" bgcolor="#daf1ff" |[[Atomic_Layer_Deposition_Recipes|Atomic Layer Deposition (Oxford FlexAL)]]
| width="65" bgcolor="#daf1ff" |[[Molecular Vapor Deposition|Molecular Vapor Deposition (Tool)]]
|-
! bgcolor="#d0e7ff" align="center" |Ag
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 3 .28Temescal.29|R2]]
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 4 .28CHA.29|R2]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R1]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R1]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |[[Thermal Evaporation Recipes#Thermal Evaporator 1|R1]]
| bgcolor="#eeffff" |[[Thermal Evaporation Recipes#Thermal Evaporator 2|R1]]
| bgcolor="#eeffff" | 
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!AgBr
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!AgCl
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! bgcolor="#d0e7ff" align="center" |Al
|[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
| 
|[[E-Beam Evaporation Recipes#E-Beam 3 .28Temescal.29|R2]]
|[[E-Beam Evaporation Recipes#E-Beam 4 .28CHA.29|R2]]
|[[Sputtering Recipes|R1]]
|[[Sputtering Recipes|R3]]
|[[Sputtering Recipes|R6]]
|R1
|[[Thermal Evaporation Recipes#Thermal Evaporator 1|R3]]
|[[Thermal Evaporation Recipes#Thermal Evaporator 2|R1]]
| 
| 
| 
| 
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|-
! bgcolor="#d0e7ff" align="center" |Al2O3
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 2 .28Custom.29|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Sputtering Recipes|R3]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R3]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R1]]
| bgcolor="#eeffff" |[[Sputtering Recipes#Si3N4 deposition .28IBD.29|R3]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|R3]]
| bgcolor="#eeffff" | 
|-
!AuPd
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|[[Thermal Evaporation Recipes#Thermal Evaporator 1|R1]]
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!AuZn
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|[[Thermal Evaporation Recipes#Thermal Evaporator 1|R1]]
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|[[Thermal Evaporation Recipes#Thermal Evaporator 1|R1]]
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!AuGe
|[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R1]]
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! bgcolor="#d0e7ff" align="center" |AlN
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|[[Sputtering Recipes|R1]]
|[[Sputtering Recipes|R1]]
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|R1
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|[[Atomic Layer Deposition Recipes#AlN deposition .28ALD CHAMBER 3.29|R3]]
| 
|-
! bgcolor="#d0e7ff" align="center" |Au
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R6]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 3 .28Temescal.29|R2]]
| bgcolor="#eeffff" |[[Process Group - Process Control Data#E-Beam 4: Au|R6]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R1]]
| bgcolor="#eeffff" |R2
| bgcolor="#eeffff" |R3
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Thermal Evaporation Recipes#Thermal Evaporator 1|R3]]
| bgcolor="#eeffff" |[[Thermal Evaporation Recipes#Thermal Evaporator 2|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
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|-
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! bgcolor="#d0e7ff" align="center" |C
| bgcolor="#eeffff" align="center" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R3]]
| bgcolor="#eeffff" align="center" |
| bgcolor="#eeffff" align="center" |
| bgcolor="#eeffff" align="center" |
| bgcolor="#eeffff" align="center" |
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| bgcolor="#eeffff" align="center" |
|-
!CaF2
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|[[Thermal Evaporation Recipes#Thermal Evaporator 2|R2]]
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! bgcolor="#d0e7ff" align="center" |CeO2
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 2 .28Custom.29|R3]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |Co
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 4 .28CHA.29|R2]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R3]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Thermal Evaporation Recipes#Thermal Evaporator 1|R1]]
| bgcolor="#eeffff" |[[Thermal Evaporation Recipes#Thermal Evaporator 2|R1]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |Cr
|[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R6]]
| 
| 
|[[Process Group - Process Control Data#E-Beam 4: Cr|R6]]
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Sputter_3_.28AJA_ATC_2000-F.29 R3]
| 
|{{Rl|Sputtering_Recipes|Sputter_5_.28AJA_ATC_2200-V.29|R6}}
| 
|[[Thermal Evaporation Recipes#Thermal Evaporator 1|R3]]
|[[Thermal Evaporation Recipes#Thermal Evaporator 2|R2]]
| 
| 
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|-
! bgcolor="#d0e7ff" align="center" |Cu
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R1]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Sputtering Recipes|R3]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Thermal Evaporation Recipes#Thermal Evaporator 1|R2]]
| bgcolor="#eeffff" |[[Thermal Evaporation Recipes#Thermal Evaporator 2|R1]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |Fe
|[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
| 
| 
|[[E-Beam Evaporation Recipes#E-Beam 4 .28CHA.29|R2]]
|[[Sputtering Recipes|R3]]
| 
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| 
|[[Thermal Evaporation Recipes#Thermal Evaporator 1|R1]]
|[[Thermal Evaporation Recipes#Thermal Evaporator 2|R1]]
| 
| 
| 
| 
| 
|-
! bgcolor="#d0e7ff" align="center" |Ge
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 3 .28Temescal.29|R2]]
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 4 .28CHA.29|R2]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R1]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R1]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |GeO2
|
|[[E-Beam Evaporation Recipes#E-Beam 2 .28Custom.29|R1]]
|
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! bgcolor="#d0e7ff" align="center" |Gd
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 4 .28CHA.29|R1]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |Hf
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R1]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | [[E-Beam Evaporation Recipes#E-Beam 4 .28CHA.29|R1]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |HfO2
| 
| 
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|R1
| 
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| 
| 
|[[Atomic Layer Deposition Recipes#AlN deposition .28ALD CHAMBER 3.29|R3]]
| 
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!Hg
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! bgcolor="#d0e7ff" align="center" |In
| bgcolor="#eeffff" | 
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| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Thermal Evaporation Recipes#Thermal Evaporator 2|R3]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |Ir
|[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R1]]
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|[[E-Beam Evaporation Recipes#E-Beam 4 .28CHA.29|R1]]
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! bgcolor="#d0e7ff" align="center" |ITO
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 2 .28Custom.29|R4]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Sputtering Recipes|R1]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R1]]
| bgcolor="#eeffff" |R1
| bgcolor="#eeffff" |R1
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
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!KCl
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!LiF
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!Mg
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|[[Thermal Evaporation Recipes#Thermal Evaporator 1|R1]]
|[[Thermal Evaporation Recipes#Thermal Evaporator 2|R1]]
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! bgcolor="#d0e7ff" align="center" |MgF2
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|[[Sputtering Recipes|R1]]
|[[Sputtering Recipes|R1]]
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|[[Thermal Evaporation Recipes#Thermal Evaporator 2|R1]]
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! bgcolor="#d0e7ff" align="center" |MgO
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|[[E-Beam Evaporation Recipes#E-Beam 2 .28Custom.29|R2]]
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!Mn
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!MnS
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! bgcolor="#d0e7ff" align="center" |Mo
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Sputtering Recipes|R3]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R1]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
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!Na
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!NaCl
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! bgcolor="#d0e7ff" align="center" |Nb
|[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
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|[[Sputtering Recipes|R4]]
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!NbO5
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! bgcolor="#d0e7ff" align="center" |Nd
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|[[Sputtering Recipes|R1]]
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|-
! bgcolor="#d0e7ff" align="center" |Ni
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R6]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 3 .28Temescal.29|R2]]
| bgcolor="#eeffff" |[[Process Group - Process Control Data#E-Beam 4: Ni|R6]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R3]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |R1
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Thermal Evaporation Recipes#Thermal Evaporator 1|R3]]
| bgcolor="#eeffff" |[[Thermal Evaporation Recipes#Thermal Evaporator 2|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |NiCr
|[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
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|[[E-Beam Evaporation Recipes#E-Beam 4 .28CHA.29|R2]]
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|[[Thermal Evaporation Recipes#Thermal Evaporator 1|R3]]
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|-
! bgcolor="#d0e7ff" align="center" |NiFe
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R1]]
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 4 .28CHA.29|R2]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R1]]
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |[[Thermal Evaporation Recipes#Thermal Evaporator 1|R3]]
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |
|-
! bgcolor="#d0e7ff" align="center" |Pd
|[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
| 
|[[E-Beam Evaporation Recipes#E-Beam 3 .28Temescal.29|R2]]
|[[E-Beam Evaporation Recipes#E-Beam 4 .28CHA.29|R2]]
|[[Sputtering Recipes|R1]]
|[[Sputtering Recipes|R1]]
|R1
| 
|[[Thermal Evaporation Recipes#Thermal Evaporator 1|R3]]
|[[Thermal Evaporation Recipes#Thermal Evaporator 2|R1]]
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|-
! bgcolor="#d0e7ff" align="center" |Pt
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 3 .28Temescal.29|R2]]
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 4 .28CHA.29|R2]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R3]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R4]]
| bcolor="EEFFFF" |[[Sputtering Recipes|R4]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Atomic Layer Deposition Recipes#Pt deposition .28ALD CHAMBER 1.29|R3]]
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |Ru
|[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
| 
| 
|[[E-Beam Evaporation Recipes#E-Beam 4 .28CHA.29|R2]]
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|[[Sputtering Recipes#Ru Deposition .28Sputter 4.29|R4]]
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|[[Atomic Layer Deposition Recipes#Pt deposition .28ALD CHAMBER 1.29|R3]]
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|-
! bgcolor="#d0e7ff" align="center" |Si
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 2 .28Custom.29|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Sputtering Recipes|R3]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R1]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |R1
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[https://wiki.nanotech.ucsb.edu/w/index.php?title=PECVD_Recipes#Amorphous-Si_deposition_.28PECVD_.232.29 R3]
| bgcolor="#eeffff" |
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |SiN
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|[[Sputtering Recipes|R3]]
|[[Sputtering Recipes|R1]]
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|[[Sputtering Recipes#Si3N4 deposition .28IBD.29|R6]]
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| 
|[[PECVD Recipes#SiN deposition .28PECVD .231.29|R6]]
|[[PECVD Recipes#SiN deposition .28PECVD .232.29|R6]]
|[[PECVD Recipes#ICP-PECVD .28Unaxis VLR.29|R6]]
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! bgcolor="#d0e7ff" align="center" |SiN - Low Stress
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|[[PECVD Recipes#Low Stress Si3N4 .28PECVD.231.29|R3]]
|[[PECVD Recipes#Low-Stress SiN deposition .28PECVD .232.29|R6]]
|[[PECVD Recipes#ICP-PECVD .28Unaxis VLR.29|R6]]
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!SiN - Low Stress 3xTime
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|[[PECVD Recipes#Low-Stress SiN 3xTime (PECVD #2)|R6]]
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! bgcolor="#d0e7ff" align="center" |SiO2
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 2 .28Custom.29|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Sputtering Recipes|R3]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R1]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R2]]
| bgcolor="#eeffff" |[[Sputtering_Recipes#SiO2_deposition_.28IBD.29|R6]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |[[PECVD Recipes#SiO2 deposition .28PECVD .231.29|R6]]
| bgcolor="#eeffff" |[[PECVD Recipes#SiO2 deposition .28PECVD .232.29|R6]]
| bgcolor="#eeffff" |[[PECVD Recipes#ICP-PECVD .28Unaxis VLR.29|R6]]
| bgcolor="#eeffff" |[[Atomic Layer Deposition Recipes#Pt deposition .28ALD CHAMBER 1.29|R3]]
| bgcolor="#eeffff" | 
|-
!SiO
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|[[Thermal Evaporation Recipes#Thermal Evaporator 1|R1]]
|[[Thermal Evaporation Recipes#Thermal Evaporator 2|R1]]
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|-
! bgcolor="#d0e7ff" align="center" |SiOxNy
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| 
|[[Sputtering Recipes#Si3N4 deposition .28IBD.29|R3]]
| 
| 
|[[PECVD Recipes#SiO2 deposition .28PECVD .231.29|R3]]
| 
| 
| 
| 
|-
! bgcolor="#d0e7ff" align="center" |Sn
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Thermal Evaporation Recipes#Thermal Evaporator 2|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |SrF2
| 
|[[E-Beam Evaporation Recipes#E-Beam 2 .28Custom.29|R2]]
| 
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| 
|[[Thermal Evaporation Recipes#Thermal Evaporator 1|R1]]
| 
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| 
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|-
! bgcolor="#d0e7ff" align="center" |Ta
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R1]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Sputtering Recipes|R3]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R1]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |R1
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |Ta2O5
| 
|[[E-Beam Evaporation Recipes#E-Beam 2 .28Custom.29|R1]]
| 
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|[[Sputtering Recipes#Si3N4 deposition .28IBD.29|R6]]
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|-
! bgcolor="#d0e7ff" align="center" |Ti
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R6]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 3 .28Temescal.29|R2]]
| bgcolor="#eeffff" |[[Process Group - Process Control Data#E-Beam 4: Ti|R6]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R3]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R4]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R6]]
| bgcolor="#eeffff" |R1
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |TiN
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| 
| 
| 
| 
|[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Sputter_4_.28AJA_ATC_2200-V.29 R4]
| 
|R1
| 
| 
| 
| 
| 
|[[Atomic Layer Deposition Recipes#Pt deposition .28ALD CHAMBER 1.29|R3]]
| 
|-
! bgcolor="#d0e7ff" align="center" |TiW
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R1]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Sputtering Recipes|R2]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R4]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |TiO2
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 2 .28Custom.29|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Sputtering Recipes|R1]]
| bgcolor="#eeffff" |[[Sputtering Recipes|R4]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Sputtering Recipes#Si3N4 deposition .28IBD.29|R3]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Atomic Layer Deposition Recipes#Pt deposition .28ALD CHAMBER 1.29|R3]]
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |V
| 
| 
| 
| 
|[[Sputtering Recipes|R1]]
|[[Sputtering Recipes|R1]]
| 
| 
| 
|
| 
| 
| 
| 
| 
|-
! bgcolor="#d0e7ff" align="center" |W
| bgcolor="#eeffff" |[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |R3
| bgcolor="#eeffff" |[[Sputtering Recipes|R4]]
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
|-
!WC
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|-
! bgcolor="#d0e7ff" align="center" |Zn
| 
| 
| 
| 
| 
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| 
| 
|[[Thermal Evaporation Recipes#Thermal Evaporator 1|R3]]
|[[Thermal Evaporation Recipes#Thermal Evaporator 2|R2]]
| 
| 
| 
| 
| 
|-
! bgcolor="#d0e7ff" align="center" |ZnO
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |
| bgcolor="#eeffff" |
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Atomic Layer Deposition Recipes#Pt deposition .28ALD CHAMBER 1.29|R3]]
| bgcolor="#eeffff" | 
|-
! bgcolor="#d0e7ff" align="center" |Zr
|[[E-Beam Evaporation Recipes#E-Beam 1 .28Sharon.29|R2]]
| 
| 
|[[E-Beam Evaporation Recipes#E-Beam 4 .28CHA.29|R2]]
|[[Sputtering Recipes|R1]]
|[[Sputtering Recipes|R1]]
| 
| 
| 
|[[Thermal Evaporation Recipes#Thermal Evaporator 2|R1]]
| 
| 
| 
| 
| 
|-
! bgcolor="#d0e7ff" align="center" |ZrO2
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" | 
| bgcolor="#eeffff" |[[Atomic Layer Deposition Recipes#Pt deposition .28ALD CHAMBER 1.29|R3]]
| bgcolor="#eeffff" | 
|-
! width="20" bgcolor="#d0e7ff" align="center" |'''Material'''
| width="65" bgcolor="#daf1ff" |[[E-Beam Evaporation Recipes#E-Beam_1_.28Sharon.29|E-Beam 1 (Sharon)]]
| width="65" bgcolor="#daf1ff" |[[E-Beam Evaporation Recipes#E-Beam_2_.28Custom.29|E-Beam 2 (Custom)]]
| width="65" bgcolor="#daf1ff" |[[E-Beam Evaporation Recipes#E-Beam_3_.28Temescal.29|E-Beam 3 (Temescal)]]
| width="65" bgcolor="#daf1ff" |[[E-Beam Evaporation Recipes#E-Beam_4_.28CHA.29|E-Beam 4 (CHA)]]
| width="65" bgcolor="#daf1ff" |[[Sputtering Recipes#Sputter_3_.28ATC_2000-F.29|Sputter 3 (ATC 2000-F)]]
| width="65" bgcolor="#daf1ff" |[[Sputtering_Recipes#Sputter_4_.28AJA_ATC_2200-V.29|Sputter 4 (ATC 2200-V)]]
| width="65" bgcolor="#daf1ff" |[[Sputtering Recipes|Sputter 5 (ATC 2200-V)]]
| width="55" bgcolor="#daf1ff" |[[Sputtering_Recipes#Ion_Beam_Deposition_.28Veeco_NEXUS.29|Ion Beam Deposition (Veeco Nexus)]]
| width="45" bgcolor="#daf1ff" |[[Thermal Evaporation Recipes#Thermal_Evap_1|Thermal Evap 1]]
| width="65" bgcolor="#daf1ff" |[[Thermal Evaporation Recipes#Thermal_Evap_2_.28Solder.29|Thermal Evap 2 (Solder)]]
| width="65" bgcolor="#daf1ff" |[[PECVD Recipes#PECVD_1_.28PlasmaTherm_790.29|PECVD 1 (PlasmaTherm 790)]]
| width="65" bgcolor="#daf1ff" |[[PECVD Recipes#PECVD_2_.28Advanced_Vacuum.29|PECVD 2 (Advanced Vacuum)]]
| width="65" bgcolor="#daf1ff" |[[PECVD_Recipes#ICP-PECVD_.28Unaxis_VLR.29|Unaxis VLR ICP-PECVD]]
| width="65" bgcolor="#daf1ff" |[[Atomic_Layer_Deposition_Recipes|Atomic Layer Deposition (Oxford FlexAl)]]
| width="65" bgcolor="#daf1ff" |[[Molecular Vapor Deposition|Molecular Vapor Deposition (Tool)]]
|}

===Process Ranking Table===
Processes in the table above are ranked by their "''Process Maturity Level''" as follows:
{| class="wikitable"
!Process Level
! colspan="11" |Description of Process Level Ranking
|-
|A
| colspan="11" |Process '''A'''llowed and materials available but never done
|-
|R1
| colspan="11" |Process has been ran at least once
|-
|R2
| colspan="11" |Process has been ran and procedure is documented
|-
|R3
| colspan="11" |Process has been ran, procedure is documented, and data is available
|-
|R4
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data
|-
|R5
| colspan="11" |Process has a documented procedure with regular (≥4x per year) data '''and''' in-Situ control available
|-
|R6
| colspan="11" |Process has a documented procedure and control charts/limits available. Controlled process.
|}
[[Category:Processing]]