ICP Etching Recipes - Revision history

John d: /* GaN Etch (Oxford ICP Etcher) */ added that the link includes Taguchi/L9 DOE explanation

2026-06-13T01:30:54Z

GaN Etch (Oxford ICP Etcher): added that the link includes Taguchi/L9 DOE explanation

← Older revision		Revision as of 01:30, 13 June 2026
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	*''OLD 4" configuration: [https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''		*''OLD 4" configuration: [https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
	**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.		**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
			**Also includes explanation of the Taguchi (L9) DOE method for learning how process variables interact.
	**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]		**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
	**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation\|Operating Procedure]] for full traveler and post-cleaning.		**See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation\|Operating Procedure]] for full traveler and post-cleaning.

John d: /* Through Silicon Via (TSV) etch (DSEiii) */ updated TSV DSE etch to ↑ EtchA bias + time

2026-04-28T15:23:43Z

Through Silicon Via (TSV) etch (DSEiii): updated TSV DSE etch to ↑ EtchA bias + time

← Older revision		Revision as of 15:23, 28 April 2026
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	\|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.		\|Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
	\|-		\|-
	\|DSEiii etch - ~~reduce Dep step~~ to eliminate grassing:		\|DSEiii etch - to eliminate grassing:

			* Increase EtchA LF-Bias Power and Duration
			** EtchA: 300W for 3.5–4sec
			** New method as of ~2025
			Old method: reduce Dep step:

	*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec		*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec

John d: /* Cleaning Procedures (Fluorine ICP Etcher) */ linked to cleaning rules.

2026-04-28T00:32:23Z

Cleaning Procedures (Fluorine ICP Etcher): linked to cleaning rules.

← Older revision		Revision as of 00:32, 28 April 2026
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	==Cleaning Procedures (Fluorine ICP Etcher)==		==Cleaning Procedures (Fluorine ICP Etcher)==

	''To Be Added''
			* [https://wiki.nanotech.ucsb.edu/w/images/6/69/Cleaning_Rules_for_Fluorine_ICP_Etch_tool.pdf '''Cleaning Rules'''] - for various etches. All cleans are O2 plasma.

	=[[ICP Etch 1 (Panasonic E646V)]]=		=[[ICP Etch 1 (Panasonic E646V)]]=

John d: /* High Rate Bosch Etch (DSEIII) */ added Plasma Dicing section with "coming soon" info

2026-04-20T22:54:45Z

High Rate Bosch Etch (DSEIII): added Plasma Dicing section with "coming soon" info

← Older revision		Revision as of 22:54, 20 April 2026
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	**Selectivity to Al<sub>2</sub>O<sub>3</sub> is extremely high, >9000. See below TSV process for processing tips with Al<sub>2</sub>O<sub>3</sub> hardmask.		**Selectivity to Al<sub>2</sub>O<sub>3</sub> is extremely high, >9000. See below TSV process for processing tips with Al<sub>2</sub>O<sub>3</sub> hardmask.
	**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).		**If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).
⚫	**<1% center to edge variability in etch rate.
	**Larger open area → lower selectivity & lower etch rate.		**Larger open area → lower selectivity & lower etch rate.
		⚫	***<1% center to edge variability in etch rate for small open area.
			***More variation across wafer for larger open area (eg. plasma dicing)
	**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO<sub>2</sub> hardmask or the Al<sub>2</sub>O<sub>3</sub>/SiO<sub>2</sub> hardmask below.		**Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult. Instead use an SiO<sub>2</sub> hardmask or the Al<sub>2</sub>O<sub>3</sub>/SiO<sub>2</sub> hardmask below.
	{\|		{\|
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	\| colspan="2" \|''<small>If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab\|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.</small>''		\| colspan="2" \|''<small>If you '''publish''' using the above process, please consider our [[Frequently Asked Questions#Publications acknowledging the Nanofab\|publication policy]]. This process was developed by [[Biljana Stamenic]] and [[Demis D. John]], 2022.</small>''
	\|}		\|}

			=== Plasma Dicing (DSEIII) ===
			'''''Coming Soon''''': Plasma Dicing process with Dicing Tape as backing film.

			This process has been developed by staff, is currently in the final stages of finalizing a public recipe. [[Demis D. John\|'''''Contact staff''''']] if you want to use it sooner.

	==Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)==		==Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)==

John d: /* DSEIII_(PlasmaTherm/Deep_Silicon_Etcher) */ FICP backup recipes to bottom, renamed "low etch rate" to "Silicon..."

2026-03-03T00:18:17Z

DSEIII_(PlasmaTherm/Deep_Silicon_Etcher): FICP backup recipes to bottom, renamed "low etch rate" to "Silicon..."

← Older revision		Revision as of 00:18, 3 March 2026
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	**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29\|mount to a carrier wafer using wax]].		**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29\|mount to a carrier wafer using wax]].
	*[[Photolithography - Manual Edge-Bead Removal Techniques\|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!		*[[Photolithography - Manual Edge-Bead Removal Techniques\|Manual PR Edge-Bead Removal]] - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

⚫	==~~Analogous~~ ~~FICP~~ Recipes (DSEiii)==
⚫	These recipes were developed to serve as backup processes for the calibrated [[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)\|'''Fluorine-ICP''']] SiO2 and Si etches [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control\|here]].

⚫	[https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing FICP to DSE etch processes].

⚫	*'''[[ICP Etching Recipes#Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)\|Si Etch v1 (⭐️Production)]]'''
⚫	*'''[[ICP Etching Recipes#SiO2 Etch (DSEiii)\|SiO2 Etch v1 (⭐️Production)]]'''

	==High Rate Bosch Etch (DSEIII)==		==High Rate Bosch Etch (DSEIII)==

	*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png\|alt=Example SEM image\|thumb\|188x188px\|Example of 100µm Deep Bosch Etched Silicon posts with Al<sub>2</sub>O<sub>3</sub> hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]		*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.[[File:DSEiii Bosch Ecth SEM Example 01.png\|alt=Example SEM image\|thumb\|188x188px\|Example of 100µm Deep Bosch Etched Silicon posts with Al<sub>2</sub>O<sub>3</sub> hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: [[Demis D. John]], 2021-07)]]
	**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10		**'''STD_Bosch_Si (⭐️Production)''' - Developed 2024-10
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	\|}		\|}

	==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==		==Silicon: Single-Step, Low Etch Rate, Smooth Sidewall Process (DSEIII)==

	*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]		*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
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	**Vertical/Smooth		**Vertical/Smooth
	**Tested by mounting 1cmx1cm piece with oil on 4" Si		**Tested by mounting 1cmx1cm piece with oil on 4" Si

		⚫	==F-ICP Backup Recipes (DSEiii)==
		⚫	These recipes were developed to serve as backup processes for the calibrated [[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)\|'''Fluorine-ICP''']] SiO2 and Si etches [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control\|here]].

		⚫	[https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing FICP to DSE etch processes].

		⚫	*'''[[ICP Etching Recipes#Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)\|Si Etch v1 (⭐️Production)]]'''
		⚫	*'''[[ICP Etching Recipes#SiO2 Etch (DSEiii)\|SiO2 Etch v1 (⭐️Production)]]'''

	=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)\|PlasmaTherm/SLR Fluorine Etcher]]=		=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)\|PlasmaTherm/SLR Fluorine Etcher]]=

John d: linked to recipe sections on this page.

2026-03-03T00:16:58Z

linked to recipe sections on this page.

@@ Line 19: / Line 19: @@
 ==Analogous FICP Recipes (DSEiii)==
-Make sure to remove photoresist from edges of wafer. These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].
+These recipes were developed to serve as backup processes for the calibrated [[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|'''Fluorine-ICP''']] SiO2 and Si etches [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control|here]].
 ==High Rate Bosch Etch (DSEIII)==

John d: /* DSEIII_(PlasmaTherm/Deep_Silicon_Etcher) */ copied into new Sio2 and Si recipes sections

2026-03-03T00:14:21Z

DSEIII_(PlasmaTherm/Deep_Silicon_Etcher): copied into new Sio2 and Si recipes sections

← Older revision		Revision as of 00:14, 3 March 2026
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	==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==		==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==

			*'''SF6-C4F8-CF4 Si Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
			**12mT, 20/850W, C4F8/SF6/CF4=68.3/32.5/32.4sccm
			**E.R. = 339.4nm/min, Selectivity (to UV6) = 4.9
			**Smooth, Vertical, E.R. uniformity is within 5% on wafer
			**Tested with 4" wafers that are ~50% open with UV6 PR
	*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]		*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
			**Older, alternate Si "shallow/smooth" etch recipe.
	**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)		**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
	**Used instead of Bosch Process, to avoid scalloping on the sidewall.		**Used instead of Bosch Process, to avoid scalloping on the sidewall.
	**Lower selectivity, lower etch rate, smoother sidewalls.		**Lower selectivity, lower etch rate, smoother sidewalls.

			== SiO2 Etch (DSEiii) ==
			These recipes were developed to serve as secondary pathways to the calibrated FICP SiO2 and Si etch calibrations [[Process Group - Process Control Data#PlasmaTherm SLR Fluorine Etcher - Process Control\|here]]. [https://wiki.nanofab.ucsb.edu/w/images/b/b3/FICP-DSE_Analogous_Recipes.pdf Click here for SEMs comparing both cals].
			*'''CF4-C4F8 SiO2 Etch v1 (⭐️Production)''' - Developed 2026-01 by [[Noah Dutra]]
			**3mT, 70/800W, C4F8/CF4=7.5/32.5sccm
			**E.R. = 270nm/min, Selectivity (to SPR955) = 1.3
			**Vertical/Smooth
			**Tested by mounting 1cmx1cm piece with oil on 4" Si

	=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)\|PlasmaTherm/SLR Fluorine Etcher]]=		=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)\|PlasmaTherm/SLR Fluorine Etcher]]=

Noahdutra: /* GaN Etch (Oxford ICP Etcher) */

2026-02-12T18:43:49Z

GaN Etch (Oxford ICP Etcher)

← Older revision		Revision as of 18:43, 12 February 2026
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	==== Process Control: GaN Etch ====		==== Process Control: GaN Etch ====
	~~NEW~~ Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''		CURRENT Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''

	* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.		* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.

Noahdutra: /* GaN Etch (Oxford ICP Etcher) */

2026-02-12T18:43:28Z

GaN Etch (Oxford ICP Etcher)

← Older revision		Revision as of 18:43, 12 February 2026
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	== GaN Etch (Oxford ICP Etcher) ==		== GaN Etch (Oxford ICP Etcher) ==
		⚫	*''OLD 4" configuration: [https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
	[[File:Dot Facet 00.jpg\|alt=Example SEM image\|thumb\|170x170px\|Example of 1.2um etched GaN, "Dot Facet". (Image Credit: Gopikrishnan Meena 2024-10)]]
⚫	*''[https://drive.google.com/file/d/1B-Xg254T-RdALisnms0jvpJQ34i5TNXN/view?usp=drive_link Std GaN Etch - BCl3/Cl2/Ar - 200C Etch Characterization] - G.G.Meena, 2024-11-01''
	**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.		**Etches characterized on ~1cmx1cm die, on 4<nowiki>''</nowiki> Si carrier wafer. Die has a SiN hard mask.
	**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]		**[https://docs.google.com/spreadsheets/d/1QELHE6VUgq-xIfwIE50ddnsDtm7yfiOM/edit?usp=drive_link&ouid=103527106727572807737&rtpof=true&sd=true Etch development traveler with detailed characterization data]
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	==== Process Control: GaN Etch ====		==== Process Control: GaN Etch ====
	~~[[File:GaN~~ SPC.png\|alt=example of Process Control Charts\|thumb\|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch\|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279\|219x219px]]Recipe: ''~~Std~~ GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm ''~~~1.2µm~~ deep GaN ~~etch~~ with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''		NEW Recipe: ''6" STD GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 6" configuration, ''~850nm deep GaN Etch with Cl2/BCl3/Ar at 200°C. GaN-on-Sapphire substrate with SiN mask.''

⚫	*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
			* This recipe is the same as the 4" (old) Std recipe but with 140% flows. Current recipe is 200c, 4.5mT, 700W/50W, Cl2/Ar/BCl3 = 49.1/16.4/12.2sccm.
⚫	*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]

			* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
			* [https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 CURRENT 6" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]

			[[File:GaN SPC.png\|alt=example of Process Control Charts\|thumb\|[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 Click for Process Control Charts] for GaN Etch\|link=https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279\|219x219px]]OLD Recipe: ''Std GaN Etch - BCl3/Cl2/Ar - 200C (Public)'', on 1cm x 1cm with 4" configuration, ''~1.2µm deep GaN etch with Cl2/BCl3/Ar at 200°C.'' ''GaN-on-Sapphire substrate with SiN mask.''
		⚫	*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=0#gid=0 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Etch Data]
		⚫	*[https://docs.google.com/spreadsheets/d/1Pk8VwZlZ2lUf3aL9J2El5ZygqHY040TX3ZAMwa33LpE/edit?gid=507237279#gid=507237279 OLD 4" configuration: GaN Etching with Cl2/BCl3/Ar at 200°C - Plots]
	==GaAs Etch (Oxford ICP Etcher)==		==GaAs Etch (Oxford ICP Etcher)==
	*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''		*''[https://drive.google.com/file/d/1Q4pmX5M9v9dCD1xOg74kYguV12Szh9be/view?usp=drive_link Std GaAs Etch - BCl3/Ar - 20C Etch Characterization] - G.G.Meena, 2025-01-09''

John d: /* Through Silicon Via (TSV) etch (DSEiii) */

2026-02-10T21:26:50Z

Through Silicon Via (TSV) etch (DSEiii)

← Older revision		Revision as of 21:26, 10 February 2026
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	{\| class="wikitable"		{\| class="wikitable"
	! colspan="2" \|Process for Through-Wafer Silicon Etching		! colspan="2" \|Process for Through-Wafer Silicon Etching
			with wax-mounting (small pieces only)
	\|-		\|-
	\|Process to etch through ~550µm Silicon		\|Process to etch through ~550µm Silicon