ICP Etching Recipes: Difference between revisions
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{{recipes|Dry Etching}} |
{{recipes|Dry Etching}} |
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=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher |
=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]= |
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==High Rate Bosch Etch (Si Deep RIE)== |
==High Rate Bosch Etch (Si Deep RIE)== |
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*[[media:10-Si_Etch_Bosch_DSEIII.pdf|Bosch Process]] |
*[[media:10-Si_Etch_Bosch_DSEIII.pdf|Bosch Process]] |
Revision as of 22:12, 6 November 2017
Back to Dry Etching Recipes.
DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)
High Rate Bosch Etch (Si Deep RIE)
Si Deep RIE (PlasmaTherm/Bosch Etch)
Bosch and Release Etch (Si Deep RIE)
- Bosch and Release Processes
- Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
- Etch rate depends on area of exposed silicon being etched.
- Al2O3 mask (ALD or Sputter) has >9000:1 selectivity
- SiO2 (PECVD) mask has ~100:1 selectivity
- Thermal SiO2 has ~300:1 selectivity.
Single-step Si Etching (not Bosch Process!) (Si Deep RIE)
ICP Etch 1 (Panasonic E626I)
SiO2 Etching (Panasonic 1)
- SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"
- Etch rate ≈ 2300Å/min (users must calibrate)
- Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)
- SiO2 CHF3 Etch Variations
- CF4/CHF4/O2 "NanoEtch" (TBA)
SiNx Etching (Panasonic 1)
Al Etch (Panasonic 1)
Cr Etch (Panasonic 1)
Ti Etch (Panasonic 1)
W-TiW Etch (Panasonic 1)
GaAs-AlGaAs Etch (Panasonic 1)
- GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar
- AlGaAs Etch Recipes - Cl2N2
- GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation
GaN Etch (Panasonic 1)
SiC Etch (Panasonic 1)
Sapphire Etch (Panasonic 1)
ICP Etch 2 (Panasonic E640)
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.
SiO2 Etching (Panasonic 2)
- SiO2 Vertical Etch Recipe - CHF3 "SiOVert"
- Direct copy of "SiOVert" from ICP#1, see parameters there.
- SiO2 Vertical Etch Recipe#2 - CF4/CHF3
- SiO2 Nanoscale Etch Recipe - CHF3/O2
SiNx Etching (Panasonic 2)
Al Etch (Panasonic 2)
GaAs Etch (Panasonic 2)
ICP-Etch (Unaxis VLR)
GaAs-AlGaAs Etch (Unaxis VLR)
InP-InGaAs-InAlAs Etch (Unaxis VLR)
- InP Etch Recipe (Cl2N2Ar 200C)
- InP-based Material Etch Profile (Cl2N2Ar200C)
- Unaxis InP Etch Recipe (Cl2H2 Ar 200C) Parameters
- InP-InGaAs Etch Profile (Cl2H2 Ar 200C)
- InGaAs-InAlAs Etch Issure (Cl2H2 Ar 200C)
- InP Etch (Cl2H2Ar 200C)2-17-2016
- InP Etch (Cl2H2Ar 200C) Start on 6-3-2016
- Lower etch-rate InP Etch (Cl2N2 200C)