ICP Etching Recipes

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DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)

Process Control Data (DSEiii)

• To Be Added

Edge-Bead Removal (DSEiii)

Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

• Edge Bead Removal via Photolithography: use a custom metal mask to pattern the photoresist with a flood exposure.
  • If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can mount to a carrier wafer using wax.
• Manual PR Edge-Bead Removal - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

High Rate Bosch Etch (DSEIII)

• Bosch Process Recipe and Characterization - Standard recipe on the tool.
  • Recipe Name: "Plasma-Therm Standard DSE" (Production - copy to your Personal category)
  • Standard Bosch Process for high aspect-ratio, high-selectivity Silicon etching.
  • Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
    • To reduce roughening/grassing (black silicon), Increase "Etch A" time by ~50%. Alternatively, reduce "Dep" step time by ~20%.
  • Patterns with different exposed/etched areas will have different "optimal" parameters.
  • Approx Selectivity to Photoresist: ~80 or better.
    • Larger open area, lower selectivity and lower etch rate.
    • Thick PR's approx ≥10µm tend to burn, avoid thick PR's. They also make edge-bead removal very difficult.
  • Selectivity to SiO2 should be higher, not yet measured.
  • Selectivity to Al₂O₃ is extremely high, >9000. See below TSV process for processing notes on this film.
  • If you need to pattern all the way to the edge of the wafer, PR won't work because you have to remove the edge-bead of photoresist (see above). Instead use hardmask process (See "Through Silicon Via" etch below).

Example of 100µm Deep Bosch Etched Silicon posts with hard mask. Close inspection shows the horizontal "scalloping" from the cycling nature of the etch. (Image Credit: Demis D. John, 2021-07)

Through Silicon Via (TSV) etch (DSEiii)

Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al₂O₃ hardmask:

NOTE: We have recently found that the wax-mounting process process can leave wax on the wafer clamp, causing the next user's wafer to get stuck and fail transfer!  DO NOT RUN the wax-mounting process without discussing with staff first. (Through-wafer process with no wax is still acceptable.) -- Demis 2024-03-11

Process for Through-Wafer Silicon Etching
Process to etch through ~550µm Silicon	Demis D. John & Biljana Stamenic 2022-11-11. Please consider our publication policy if you use/modify this process.
Deposit 150nm Al2O3 on either: Veeco Nexus IBD AJA Sputter 3/4/5 (Check which has Al target installed)	May need to do dep. rate check beforehand.
Deposit ~3nm SiO2, in situ (same machine as above)	This improves adhesion to photoresist and prevents developer attacking the Al2O3.
Lithography - your preferred method. Needs approx. ≥500nm thick PR.
Etch the Al2O3 in Panasonic ICP 1/2	Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
Strip PR - either in situ, or via NMP 80°C soak followed by PEii Technics ashing.	In situ PR strip appears to give better + faster results.
If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer: Logitech Wax Mounting Recipe - Bulk Crystal Bond If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.	Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
Use POLOS spinners with ACE/ISO to clean front and back of wafer. IMPORTANT for wax-mounting, to ensure wax does not stick your wafer to the DSE clamp. Observe carefully for any wax protruding from between wafers - redo spin-clean as needed.	Also make sure wax thickness is not too thick, of long etches could cause wax to seep out from between the wafers.
DSEiii etch - reduce Dep step to eliminate grassing: Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec Rate ≈ 4.25µm / min	Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched. Record Helium FLOW during recipe run, for next step (if He leaks). Ok to remove wafer, observe/measure, and re-load for etching. If see black grass and etch rate drops, may need to run an O2 plasma with Technics PEii few min to remove polymer, reduce Dep step time and then continue.
If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow our of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through. Once this happens, Leave your wafer in the chamber, then Edit recipe to set Helium Cooling (first step only) to "Flow Control Only". Choose typical flow of normal process from above (Something like ~6sccm? Not sure.)
Strip Al2O3/SiO2 either with HF, or same Pan1/2 dry etch as above.
IF wax-mounted - either dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse OR place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then ACE/ISO clean to remove wax.
If you publish using the above process, please consider our publication policy. This process was developed by Biljana Stamenic and Demis D. John, 2022.

Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)

• Single Step Silicon Etch Recipe and Characterization
  • Recipe Name: "Nano Trench Etch" (Production - copy to your Personal category)
  • Used instead of Bosch Process, to avoid scalloping on the sidewall.
  • Lower selectivity, lower etch rate, smoother sidewalls.

PlasmaTherm/SLR Fluorine Etcher

Recipe Tips

• RF1: Bias Power (with DCV readback)
• RF2: ICP Power
• For trouble igniting ICP plasma, add 15 to 75 W of bias power during ignition step. Typical ignition pressures 5 to 10 mT.

Process Control Data (Fluorine ICP Etcher)

SiO₂ Etching with CHF3/CF4 (Fluorine ICP Etcher)

• SiO₂ Etching with CHF3/CF4 - Etch Data
• SiO₂ Etching with CHF3/CF4 - Plots
  

  Click for Process Control Charts

Si Etching (Fluorine ICP Etcher)

• SiVertHF - Si Vertical Etch using C₄F₈/SF₆/CF₄ and resist mask
  • Etch Rates: Si ≈ 300-350 nm/min; SiO₂ ≈ 30-35 nm/min
  • 89-90 degree etch angle, ie, vertical.
  • High selectivity to Al2O3 masks.
    • For high aspect ratio Si etching, try ALD Al₂O₃ (~20-30nm) + SiO₂ (2nm, for PR adhesion) hardmasks followed by Pan2 Al₂O₃ etch (will go straight through the thin SiO₂ without additional etch time). Works well for allowing thin PR's (eg. DUV or EBL PR's) to enable deep etches.

Process Notes/Observations

• Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO₂ etch (below) to remove native oxide on Si. This can be performed in situ before the Si etch.
• We have observed that full-wafers with small open area in photoresist masks might require a recalibration of the C4F8/SF6 ratio in order to prevent very low etch rates.

SiO2 Etching (Fluorine ICP Etcher)

• SiO2 Etching using Ruthenium Hardmask - Full Process Traveler
  • Ning Cao & Bill Mitchell, 2019-06
  • High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.
  • Etch also works well with PR masking
  • Chemistry: CHF3/CF4
  • Variations in SiO₂ etch Bias Power: 50 / 200 / 400W bias.
  • Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
  • 50W Bias: (recommended)
    • Selectivity to photoresist: 1.10–1.20
    • SiO₂ selectivity to Ru: 36
    • SiO₂ etch rate: 263nm/min
  • 200W Bias:
    • SiO₂ selectivity to Ru: 38
    • SiO₂ etch rate: 471nm/min
  • This etch is detailed in the following article: W.J. Mitchell et al., JVST-A, May 2021

Si₃N₄ Etching (Fluorine ICP Etcher)

Developed by Bill Mitchell. Please see publication policy.

• ICP = 950/75W
• Pressure = 5mT
• Low Polymer Dep: CF4 = 60sccm
  • Etch Rate = 420nm/min (PECVD Si₃N₄)
• Higher verticality: CF4 = 35 / CHF3 = 25 sccm
  • Etch Rate = 380nm/min (PECVD Si₃N₄)

Photoresist & ARC (Fluorine ICP Etcher)

Chain multiple Recipes in a Flow, to allow you to to do in situ BARC etching, and follow up with in situ Photoresist Strip.

PR/BARC Etch (Fluorine ICP Etcher)

• Etching DUV42P-6 Bottom Anti-Reflection Coating
  • ~60nm thick (2500krpm)
  • O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
  • 1min

Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)

• • O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
  • 75W Bias can be helpful for difficult to remove polymers, eg. 2min
  • Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.

Cleaning Procedures (Fluorine ICP Etcher)

To Be Added

ICP Etch 1 (Panasonic E646V)

Process Control Data (Panasonic 1)

SiO₂ Etch with CHF₃/CF₄ - Process Control Data (Panasonic 1)

• SiO₂ Etch with CHF₃/CF₄ - Etch Data
• SiO₂ Etch with CHF₃/CF₄ - Plots
  

  Click for Process Control Charts

SiO₂ Etching (Panasonic 1)

Recipes

• SiO₂ Vertical Etch Recipe Parameters - CHF₃ "SiOVert"
  • Etch rate ≈ 2300Å/min (users must calibrate)
  • Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

Recipe Variations

Use these to determine how each etch parameter affects the process.

• SiO₂ CHF₃ Etch Variations - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

SiN_x Etching (Panasonic 1)

• SiN_x Etch Rates and Variations - CF₄-O₂

Al Etch (Panasonic 1)

• Al Etch Recipes - Cl₂BCl₃
• AlCl₃ Erosion Issue and the Solution

Cr Etch (Panasonic 1)

• Cr Etch Recipes - Cl₂O₂

Ta Etch (Panasonic 1)

• Ta Etch Recipe - Cl2/BCl3

Ti Etch (Panasonic 1)

• Ti Deep Etch Recipes - Cl₂Ar
  • See E. Parker, et. al. Jnl. Electrochem. Soc., 152 (10) C675-C683 2005.

W-TiW Etch (Panasonic 1)

• Ti-TiW Etch Recipes - SF₆Ar

GaAs-AlGaAs Etch (Panasonic 1)

• GaAs-Nanoscale Etch Recipe - PR mask - Cl₂-BCl₃-Ar
• AlGaAs Etch Recipes - Cl₂N₂
• GaAs DRIE via Etch Recipes - Cl₂-BCl₃-Ar PR passivation

GaN Etch (Panasonic 1)

• GaN Etch Recipes Cl₂N₂
• GaN Selective Etch over AlGaN Recipes BCl₃-SF₆

Photoresist and ARC Etching (Panasonic 1)

Please see the recipes for Panasonic ICP#2 - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

SiC Etch (Panasonic 1)

• SiC Etch Recipes Ni Mask - SF₆

Sapphire Etch (Panasonic 1)

• Sapphire Etch Recipes Ni and PR Mask - BCl₃-Cl₂

Cleaning Recipes

To Be Added

Old Deleted Recipes

Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the tool's Supervisor and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

ICP Etch 2 (Panasonic E626I)

Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

Process Control Data (Panasonic 2)

SiO₂ Etch with CHF₃/CF₄ - Process Control Data (Panasonic 2)

• SiO2 Etch with CHF3/CF4 - Etch Data
• SiO2 Etch with CHF3/CF4 - Plots
  

  Click for Process Control Charts

SiO₂ Etching (Panasonic 2)

Recipes

• SiO₂ Vertical Etch Recipe - CHF₃ "SiOVert"
  • Direct copy of "SiOVert" from ICP#1, see parameters there.
• SiO₂ Vertical Etch Recipe#2 - CF₄/CHF₃
• SiO₂ Nanoscale Etch Recipe - CHF₃/O₂

Recipe Variations

Use these to determine how etch parameters affect the process.

• Angled SiO2 sidewall recipes

SiN_x Etching (Panasonic 2)

• SiN_x Nanoscale Etch Recipe - CHF₃/O₂

Al Etch (Panasonic 2)

• Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher

Al2O3 Etching (Panasonic 2)

ALD Al2O3 Etch Rates in BCl3 Chemistry (click for plots of etch rate)

Contributed by Brian Markman, 2018

• BCl3 = 30sccm
• Pressure = 0.50 Pa
• ICP Source RF = 500
• Bias RF = 50W or 250W (250W can burn PR)
• Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
• Etch Rate 50W: 39.6nm/min (0.66nm/sec)
• Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

GaAs Etch (Panasonic 2)

• GaAs Etch Recipes - Panasonic 2 - Cl₂N₂

Photoresist and ARC etching (Panasonic 2)

Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

ARC Etching: DUV-42P or AR6 (Panasonic 2)

• O2 = 40 sccm // 0.5 Pa
• ICP = 75W // RF = 75W
• 45 sec for full etching (incl. overetch) of ~60nm DUV-42P (same as for AR6; 2018-2019, Demis/BrianT)

Photoresist Etch/Strip (Panasonic 2)

Works very well for photoresist stripping

• O2 = 40 sccm // 1.0 Pa
• ICP = 350W // RF = 100W
• Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, Demis)
• 2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, Demis)

Ru (Ruthenium) Etch (Panasonic 2)

• Ru Etch - Bill Mitchell 2019-09-19
  • This etch is used in the following publication: W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)

Oxford ICP Etcher (PlasmaPro 100 Cobra)

Process Control Data (Oxford ICP Etcher)

Process Control Data for "Std InP Ridge Etch" Cl₂/CH₄/H₂/60°C

Calibration / Process testing data taken using the "InP Ridge Etch" process: Cl2/CH4/H2 @ 60°C, 1cm piece with ~50% SiO2 hardmask.

• "Std InP Ridge Etch" Cl₂/CH₄/H₂/60°C - Etch Data Tables
• "Std InP Ridge Etch" Cl₂/CH₄/H₂/60°C - Plots
  

  Click for Process Control Charts

InP Ridge Etch (Oxford ICP Etcher)

Low-Temp (60°C) Process

• Low-Temp InP Ridge Etch Characterization - Ning Cao, 2021-09-08
  • InP etches were characterized with no mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
  • Recipe: Cl2/CH4/H2 - 60°C
  • NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
• See Operating Procedure for full traveler and post-cleaning.

Sample Size effect on Etch Rate

See the above table for data showing effect on sample size/exposed etched area.

InP Grating Etch (Oxford ICP Etcher)

• InP/InGaAsP Grating Etch Characterization - Ning Cao, 2021-08-26
  • InP/InGaAsP etches were characterized with no mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
  • Recipe: Cl2/CH4/H2/Ar - 20°C
  • NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
• See Operating Procedure for full traveler and post-cleaning.

GaAs Etch (Oxford ICP Etcher)

This recipe also provides a starting point for GaSb-based etches.

• GaAs-based materials - etch recipe available on tool - provided by Oxford, not yet qualified internally
• See Operating Procedure for full traveler and post-cleaning.

GaN Etch (Oxford ICP Etcher)

• GaN-based materials - etch recipe available on tool - provided by Oxford, not yet qualified internally
• See Operating Procedure for full traveler and post-cleaning.

GaN Atomic Layer Etching (Oxford ICP Etcher)

GaN-ALE Recipe written and tested by users - contact supervisor for use.

Cleaning Recipes (Oxford ICP Etcher)

To Be Added: Required cleaning time & recipes