ICP Etching Recipes: Difference between revisions
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(→ICP Etch 2 (Panasonic E640): unfinished Al2O3 etching on ICP2) |
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=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]= |
=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]= |
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==High Rate Bosch Etch (DSEIII)== |
==High Rate Bosch Etch (DSEIII)== |
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*[[media:10- |
*[[media:10-Si Etch Bosch DSEIII.pdf|Bosch Process]] |
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==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)== |
==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)== |
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*[[media:10- |
*[[media:10-Si Etch Single Step Smooth Sidewall DSEIII.pdf|Single Step Process]] |
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=[[Si Deep RIE (PlasmaTherm/Bosch Etch)]]= |
=[[Si Deep RIE (PlasmaTherm/Bosch Etch)]]= |
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==Bosch and Release Etch (Si Deep RIE)== |
==Bosch and Release Etch (Si Deep RIE)== |
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*[[media:10- |
*[[media:10-Si Etch Bosch Release DRIE.pdf|Bosch and Release Processes]] |
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**Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer). |
**Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer). |
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**Etch rate depends on area of exposed silicon being etched. |
**Etch rate depends on area of exposed silicon being etched. |
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==Al Etch (Panasonic 1)== |
==Al Etch (Panasonic 1)== |
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*[[media:Panasonic-1-Al-Etch-RevA.pdf|Al Etch Recipes - Cl<sub>2</sub>BCl<sub>3</sub>]] |
*[[media:Panasonic-1-Al-Etch-RevA.pdf|Al Etch Recipes - Cl<sub>2</sub>BCl<sub>3</sub>]] |
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*[[media:32- |
*[[media:32-Reducing AlCl3 Corrosion with CHF3 plasma.pdf|AlCl<sub>3</sub> Erosion Issue and the Solution]] |
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==Cr Etch (Panasonic 1)== |
==Cr Etch (Panasonic 1)== |
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==GaAs-AlGaAs Etch (Panasonic 1)== |
==GaAs-AlGaAs Etch (Panasonic 1)== |
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*[[media:Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf|GaAs-Nanoscale Etch Recipe - PR mask - Cl<sub>2</sub>-BCl<sub>3</sub>-Ar]] |
*[[media:Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf|GaAs-Nanoscale Etch Recipe - PR mask - Cl<sub>2</sub>-BCl<sub>3</sub>-Ar]] |
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*[[media:12- |
*[[media:12-Plasma Etching of AlGaAs-Panasonic ICP-1-Etcher.pdf|AlGaAs Etch Recipes - Cl<sub>2</sub>N<sub>2</sub>]] |
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*[[media:Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf|GaAs DRIE via Etch Recipes - Cl<sub>2</sub>-BCl<sub>3</sub>-Ar PR passivation]] |
*[[media:Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf|GaAs DRIE via Etch Recipes - Cl<sub>2</sub>-BCl<sub>3</sub>-Ar PR passivation]] |
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==GaN Etch (Panasonic 1)== |
==GaN Etch (Panasonic 1)== |
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*[[media:07- |
*[[media:07-GaN Etch-Panasonic-ICP-1.pdf|GaN Etch Recipes Cl<sub>2</sub>N<sub>2</sub>]] |
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*[[media:Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf|GaN Selective Etch over AlGaN Recipes BCl<sub>3</sub>-SF<sub>6</sub>]] |
*[[media:Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf|GaN Selective Etch over AlGaN Recipes BCl<sub>3</sub>-SF<sub>6</sub>]] |
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*[[media:Panasonic2-SiOx-Recipe.pdf|SiO<sub>2</sub> Vertical Etch Recipe - CHF<sub>3</sub> "SiOVert"]] |
*[[media:Panasonic2-SiOx-Recipe.pdf|SiO<sub>2</sub> Vertical Etch Recipe - CHF<sub>3</sub> "SiOVert"]] |
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**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]]. |
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]]. |
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*[[media:33- |
*[[media:33-Etching SiO2 with Vertical Side-wall.pdf|SiO<sub>2</sub> Vertical Etch Recipe#2 - CF<sub>4</sub>/CHF<sub>3</sub>]] |
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*[[media:Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf|SiO<sub>2</sub> Nanoscale Etch Recipe - CHF<sub>3</sub>/O<sub>2</sub>]] |
*[[media:Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf|SiO<sub>2</sub> Nanoscale Etch Recipe - CHF<sub>3</sub>/O<sub>2</sub>]] |
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==Al Etch (Panasonic 2)== |
==Al Etch (Panasonic 2)== |
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*[[media:Panasonic-1-Al-Etch-RevA.pdf|Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]] |
*[[media:Panasonic-1-Al-Etch-RevA.pdf|Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]] |
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== Al2O3 Etching (Panasonic 2) == |
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ALD Al2O3 Etch Rates in BCl3 Chemistry |
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==GaAs Etch (Panasonic 2)== |
==GaAs Etch (Panasonic 2)== |
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*[[media:16- |
*[[media:16-GaAs etch-ICP-2.pdf|GaAs Etch Recipes - Panasonic 2 - Cl<sub>2</sub>N<sub>2</sub>]] |
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=[[ICP-Etch (Unaxis VLR)]]= |
=[[ICP-Etch (Unaxis VLR)]]= |
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==GaAs-AlGaAs Etch (Unaxis VLR) == |
==GaAs-AlGaAs Etch (Unaxis VLR) == |
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*[[media:15- |
*[[media:15-GaAs etch-Unaxis ICP etcher.pdf|GaAs Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 30C)]] |
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*[[media:14-AlAs-GR- |
*[[media:14-AlAs-GR-cal etch-Unaxis ICP etcher.pdf|AlGaAs Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 30C)]] |
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==InP-InGaAs-InAlAs Etch (Unaxis VLR)== |
==InP-InGaAs-InAlAs Etch (Unaxis VLR)== |
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*[[media:UNAXIS-VLR-InP-Etch-200C-Recipe.pdf|InP Etch Recipe (Cl<sub>2</sub>N<sub>2</sub>Ar 200C)]] |
*[[media:UNAXIS-VLR-InP-Etch-200C-Recipe.pdf|InP Etch Recipe (Cl<sub>2</sub>N<sub>2</sub>Ar 200C)]] |
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*[[media:18-InP- |
*[[media:18-InP-based etching-Cl2N2Ar.pdf|InP-based Material Etch Profile (Cl<sub>2</sub>N<sub>2</sub>Ar200C)]] |
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*[[media:UNAXIS-VLR-InP-Etch-Ar-200C-Recipe.pdf|Unaxis InP Etch Recipe (Cl<sub>2</sub>H<sub>2</sub> Ar 200C) Parameters]] |
*[[media:UNAXIS-VLR-InP-Etch-Ar-200C-Recipe.pdf|Unaxis InP Etch Recipe (Cl<sub>2</sub>H<sub>2</sub> Ar 200C) Parameters]] |
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*[[media:17-InP |
*[[media:17-InP&InGaAs etch-Cl2H2Ar-Unaxis-VLR.pdf|InP-InGaAs Etch Profile (Cl<sub>2</sub>H<sub>2</sub> Ar 200C)]] |
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*[[media:43- |
*[[media:43-Issue with the etch of InP-InGaAs-and- InAlAs-b.pdf|InGaAs-InAlAs Etch Issure (Cl<sub>2</sub>H<sub>2</sub> Ar 200C)]] |
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*[[media:50- |
*[[media:50-InP Etch-2-17-2016.pdf|InP Etch (Cl<sub>2</sub>H<sub>2</sub>Ar 200C)2-17-2016]] |
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*[[media: |
*[[media:InP Etch using Unaxis PM1 at 200 C-S6.pdf|InP Etch (Cl<sub>2</sub>H<sub>2</sub>Ar 200C) Start on 6-3-2016]] |
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*[[media:Lower-Etch- |
*[[media:Lower-Etch-Rate InP Etch using Unaxis PM1 tool at 200 C.pdf|Lower etch-rate InP Etch (Cl<sub>2</sub>N<sub>2</sub> 200C)]] |
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==GaN Etch (Unaxis VLR)== |
==GaN Etch (Unaxis VLR)== |
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*[[media:09- |
*[[media:09-Plasma Etching of GaN-UnaxisPM1.pdf|GaN Etch Recipe (Cl<sub>2</sub>BCl<sub>3</sub>N<sub>2</sub>Ar 85C)]] |
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==GaSb Etch (Unaxis VLR)== |
==GaSb Etch (Unaxis VLR)== |
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*[[media: |
*[[media:InGaAsSb etch.pdf|GaSb Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 80C)]] |
Revision as of 01:46, 7 February 2018
Back to Dry Etching Recipes.
DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)
High Rate Bosch Etch (DSEIII)
Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)
Si Deep RIE (PlasmaTherm/Bosch Etch)
Bosch and Release Etch (Si Deep RIE)
- Bosch and Release Processes
- Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
- Etch rate depends on area of exposed silicon being etched.
- Al2O3 mask (ALD or Sputter) has >9000:1 selectivity
- SiO2 (PECVD) mask has ~100:1 selectivity
- Thermal SiO2 has ~300:1 selectivity.
Single-step Si Etching (not Bosch Process!) (Si Deep RIE)
ICP Etch 1 (Panasonic E626I)
SiO2 Etching (Panasonic 1)
- SiO2 Vertical Etch Recipe Parameters - CHF3 "SiOVert"
- Etch rate ≈ 2300Å/min (users must calibrate)
- Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)
- SiO2 CHF3 Etch Variations
- CF4/CHF4/O2 "NanoEtch" (TBA)
SiNx Etching (Panasonic 1)
Al Etch (Panasonic 1)
Cr Etch (Panasonic 1)
Ti Etch (Panasonic 1)
W-TiW Etch (Panasonic 1)
GaAs-AlGaAs Etch (Panasonic 1)
- GaAs-Nanoscale Etch Recipe - PR mask - Cl2-BCl3-Ar
- AlGaAs Etch Recipes - Cl2N2
- GaAs DRIE via Etch Recipes - Cl2-BCl3-Ar PR passivation
GaN Etch (Panasonic 1)
SiC Etch (Panasonic 1)
Sapphire Etch (Panasonic 1)
ICP Etch 2 (Panasonic E640)
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.
SiO2 Etching (Panasonic 2)
- SiO2 Vertical Etch Recipe - CHF3 "SiOVert"
- Direct copy of "SiOVert" from ICP#1, see parameters there.
- SiO2 Vertical Etch Recipe#2 - CF4/CHF3
- SiO2 Nanoscale Etch Recipe - CHF3/O2
SiNx Etching (Panasonic 2)
Al Etch (Panasonic 2)
Al2O3 Etching (Panasonic 2)
ALD Al2O3 Etch Rates in BCl3 Chemistry
GaAs Etch (Panasonic 2)
ICP-Etch (Unaxis VLR)
GaAs-AlGaAs Etch (Unaxis VLR)
InP-InGaAs-InAlAs Etch (Unaxis VLR)
- InP Etch Recipe (Cl2N2Ar 200C)
- InP-based Material Etch Profile (Cl2N2Ar200C)
- Unaxis InP Etch Recipe (Cl2H2 Ar 200C) Parameters
- InP-InGaAs Etch Profile (Cl2H2 Ar 200C)
- InGaAs-InAlAs Etch Issure (Cl2H2 Ar 200C)
- InP Etch (Cl2H2Ar 200C)2-17-2016
- InP Etch (Cl2H2Ar 200C) Start on 6-3-2016
- Lower etch-rate InP Etch (Cl2N2 200C)